llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

---

name:            ffbl_b32_s32_s_s
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ffbl_b32_s32_s_s
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[S_FF1_I32_B32_:%[0-9]+]]:sreg_32 = S_FF1_I32_B32 [[COPY]]
    ; CHECK: S_ENDPGM 0, implicit [[S_FF1_I32_B32_]]
  %0:sgpr(s32) = COPY $sgpr0
  %1:sgpr(s32) = G_AMDGPU_FFBL_B32 %0
  S_ENDPGM 0, implicit %1

...

---

name:            ffbl_b32_s32_v_v
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: ffbl_b32_s32_v_v
    ; CHECK: liveins: $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[V_FFBL_B32_e64_:%[0-9]+]]:vgpr_32 = V_FFBL_B32_e64 [[COPY]], implicit $exec
    ; CHECK: S_ENDPGM 0, implicit [[V_FFBL_B32_e64_]]
  %0:vgpr(s32) = COPY $vgpr0
  %1:vgpr(s32) = G_AMDGPU_FFBL_B32 %0
  S_ENDPGM 0, implicit %1

...

---

name:            ffbl_b32_v_s
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ffbl_b32_v_s
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[V_FFBL_B32_e64_:%[0-9]+]]:vgpr_32 = V_FFBL_B32_e64 [[COPY]], implicit $exec
    ; CHECK: S_ENDPGM 0, implicit [[V_FFBL_B32_e64_]]
  %0:sgpr(s32) = COPY $sgpr0
  %1:vgpr(s32) = G_AMDGPU_FFBL_B32 %0
  S_ENDPGM 0, implicit %1

...