llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

---
name:            test_f16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_f16
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[TRUNC]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FABS]](s16)
    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s16) = G_TRUNC %0:_(s32)
    %2:_(s16) = G_FNEG %1:_
    %3:_(s16) = G_FABS %2:_
    %4:_(s32) = G_ANYEXT %3:_(s16)
    $vgpr0 = COPY %4:_(s32)

...
---
name:            test_f32
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_f32
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FABS]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_FNEG %0
    %2:_(s32) = G_FABS %1
    $vgpr0 = COPY %2(s32)

...
---
name:            test_f64
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_f64
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FABS]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_FNEG %0
    %2:_(s64) = G_FABS %1
    $vgpr0_vgpr1 = COPY %2(s64)

...
---
name:            test_v2f16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_v2f16
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(<2 x s16>) = G_FABS [[COPY]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
    %0:_(<2 x s16>) = COPY $vgpr0
    %1:_(<2 x s16>) = G_FNEG %0
    %2:_(<2 x s16>) = G_FABS %1
    $vgpr0 = COPY %2(<2 x s16>)

...
---
name:            test_v3f32
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2

    ; CHECK-LABEL: name: test_v3f32
    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(<3 x s32>) = G_FABS [[COPY]]
    ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[FABS]](<3 x s32>)
    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    %1:_(<3 x s32>) = G_FNEG %0
    %2:_(<3 x s32>) = G_FABS %1
    $vgpr0_vgpr1_vgpr2 = COPY %2(<3 x s32>)

...