| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s |
| # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes=machine-scheduler -o - %s | FileCheck %s |
| # The DBG_VALUE in bb.5 ends a scheduling region, and its uses should |
| # not be tracked like a normal instruction. |
| |
| --- | |
| define void @dbg_value_ends_sched_region() { |
| unreachable |
| } |
| |
| !llvm.dbg.cu = !{!0} |
| !llvm.module.flags = !{!3, !4} |
| |
| !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 12.0.0 (/src/external/llvm-project/clang ff12a3768d17240b01cbe9957e3c9e8f8ffe9854)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, splitDebugInlining: false, nameTableKind: None) |
| !1 = !DIFile(filename: "/tmp/comgr-054202/input/CompileSource", directory: "/home/matt/bugs/SWDEV-253507") |
| !2 = !{} |
| !3 = !{i32 2, !"Debug Info Version", i32 3} |
| !4 = !{i32 7, !"PIC Level", i32 1} |
| !5 = !{!6, !9, i64 68} |
| !6 = !{!"ShaderData", !7, i64 0, !7, i64 16, !7, i64 32, !7, i64 48, !9, i64 64, !9, i64 68, !9, i64 72, !9, i64 76, !9, i64 80, !10, i64 84, !10, i64 88, !9, i64 92, !9, i64 96, !10, i64 100, !10, i64 104, !11, i64 112, !11, i64 144, !12, i64 176, !12, i64 184, !7, i64 192, !7, i64 208, !7, i64 224, !11, i64 240, !9, i64 272, !9, i64 276, !9, i64 280, !10, i64 284, !7, i64 288, !7, i64 304, !7, i64 320, !7, i64 336} |
| !7 = !{!"omnipotent char", !8, i64 0} |
| !8 = !{!"Simple C/C++ TBAA"} |
| !9 = !{!"int", !7, i64 0} |
| !10 = !{!"float", !7, i64 0} |
| !11 = !{!"differential3", !7, i64 0, !7, i64 16} |
| !12 = !{!"differential", !10, i64 0, !10, i64 4} |
| !13 = !{!6, !9, i64 280} |
| !16 = !DILocalVariable(name: "data", scope: !17, file: !18, line: 24) |
| !17 = distinct !DISubprogram(name: "svm_node_geometry", scope: !18, file: !18, line: 21, type: !19, scopeLine: 23, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2) |
| !18 = !DIFile(filename: "source/kernel/svm/svm_geometry.h", directory: "/home/matt/bugs/SWDEV-253507") |
| !19 = !DISubroutineType(types: !20) |
| !20 = !{null} |
| !21 = !DILocation(line: 0, scope: !17) |
| |
| ... |
| --- |
| name: dbg_value_ends_sched_region |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' |
| frameOffsetReg: '$sgpr33' |
| stackPtrOffsetReg: '$sgpr32' |
| body: | |
| ; CHECK-LABEL: name: dbg_value_ends_sched_region |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.1(0x80000000) |
| ; CHECK-NEXT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 |
| ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF |
| ; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.2(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: undef [[V_ADD_CO_U32_e64_:%[0-9]+]].sub0:vreg_64, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[DEF3]].sub0, [[DEF5]].sub0, 0, implicit $exec |
| ; CHECK-NEXT: dead undef [[V_ADD_CO_U32_e64_:%[0-9]+]].sub1:vreg_64, dead [[V_ADDC_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 [[DEF3]].sub1, [[DEF5]].sub1, [[V_ADD_CO_U32_e64_1]], 0, implicit $exec |
| ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, implicit $exec :: (load (s64), addrspace 1) |
| ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_64 = IMPLICIT_DEF |
| ; CHECK-NEXT: dead [[COPY2:%[0-9]+]]:vreg_64 = COPY [[DEF8]] |
| ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[DEF2]] |
| ; CHECK-NEXT: dead [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[DEF1]] |
| ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[DEF4]].sub1 |
| ; CHECK-NEXT: dead [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]].sub0 |
| ; CHECK-NEXT: dead [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_I32_e64 4, [[DEF6]], implicit $exec |
| ; CHECK-NEXT: GLOBAL_STORE_DWORDX2 [[COPY]], [[DEF7]], 288, 0, implicit $exec :: (store (s64), addrspace 1) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.3(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: undef [[DEF4:%[0-9]+]].sub1:vreg_64 = COPY [[COPY5]] |
| ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.4: |
| ; CHECK-NEXT: successors: %bb.5(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: dead [[COPY7:%[0-9]+]]:sreg_64 = COPY $exec |
| ; CHECK-NEXT: dead [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[COPY1]], 0, 0, implicit $exec :: (load (s128), addrspace 1) |
| ; CHECK-NEXT: DBG_VALUE [[GLOBAL_LOAD_DWORDX4_]], $noreg, <0x{{[0-9a-f]+}}>, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !DILocation(line: 0, scope: <0x{{[0-9a-f]+}}>) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.5: |
| ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec |
| ; CHECK-NEXT: S_BRANCH %bb.1 |
| bb.0: |
| liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 |
| |
| %0:vreg_64 = COPY $vgpr0_vgpr1 |
| %1:vreg_64 = COPY $vgpr2_vgpr3 |
| %2:vreg_64 = IMPLICIT_DEF |
| %3:vreg_64 = IMPLICIT_DEF |
| %4:vgpr_32 = IMPLICIT_DEF |
| %5:vgpr_32 = IMPLICIT_DEF |
| %6:vreg_64 = IMPLICIT_DEF |
| %7:vreg_64 = IMPLICIT_DEF |
| %8:vreg_64 = IMPLICIT_DEF |
| %9:vgpr_32 = IMPLICIT_DEF |
| %10:vreg_64 = IMPLICIT_DEF |
| undef %11.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec |
| |
| bb.1: |
| %12:vreg_64 = COPY %2 |
| %13:vgpr_32 = COPY %5 |
| dead %14:vgpr_32 = COPY %4 |
| %15:vgpr_32 = COPY %7.sub1 |
| dead %16:vgpr_32 = COPY %11.sub0 |
| undef %17.sub0:vreg_64, %18:sreg_64_xexec = V_ADD_CO_U32_e64 %6.sub0, %8.sub0, 0, implicit $exec |
| dead %17.sub1:vreg_64, dead %19:sreg_64_xexec = V_ADDC_U32_e64 %6.sub1, %8.sub1, %18, 0, implicit $exec |
| %6:vreg_64 = GLOBAL_LOAD_DWORDX2 %3, 0, 0, implicit $exec :: (load (s64), addrspace 1) |
| dead %20:sreg_64 = V_CMP_GT_I32_e64 4, %9, implicit $exec |
| GLOBAL_STORE_DWORDX2 %0, %10, 288, 0, implicit $exec :: (store (s64), addrspace 1) |
| |
| bb.2: |
| %5:vgpr_32 = COPY %13 |
| |
| bb.3: |
| undef %7.sub1:vreg_64 = COPY %15 |
| S_CBRANCH_EXECZ %bb.2, implicit $exec |
| |
| bb.4: |
| dead %21:sreg_64 = COPY $exec |
| %22:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 0, 0, implicit $exec :: (load (s128), addrspace 1) |
| DBG_VALUE %22, $noreg, !16, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !21 |
| |
| bb.5: |
| S_CBRANCH_EXECZ %bb.3, implicit $exec |
| S_BRANCH %bb.1 |
| |
| ... |
