llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -run-pass ppc-pre-emit-peephole %s -o - | FileCheck %s

---
name:            t1
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1

    ; CHECK-LABEL: name: t1
    ; CHECK: liveins: $x1
    ; CHECK: renamable $x3 = LI8 0
    ; CHECK: STD renamable $x3, 16, $x1
    ; CHECK: STD killed renamable $x3, 8, $x1
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    renamable $x3 = LI8 0
    STD killed renamable $x3, 16, $x1
    renamable $x3 = LI8 0
    STD killed renamable $x3, 8, $x1
    BLR8 implicit $lr8, implicit $rm

...
---
name:            t2
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1

    ; CHECK-LABEL: name: t2
    ; CHECK: liveins: $x1
    ; CHECK: renamable $x3 = LI8 0
    ; CHECK: STD renamable $x3, 32, $x1
    ; CHECK: STD renamable $x3, 24, $x1
    ; CHECK: STD renamable $x3, 16, $x1
    ; CHECK: STD killed renamable $x3, 8, $x1
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    renamable $x3 = LI8 0
    STD killed renamable $x3, 32, $x1
    renamable $x3 = LI8 0
    STD killed renamable $x3, 24, $x1
    renamable $x3 = LI8 0
    STD killed renamable $x3, 16, $x1
    renamable $x3 = LI8 0
    STD killed renamable $x3, 8, $x1
    BLR8 implicit $lr8, implicit $rm

...
---
name:            t3
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1

    ; CHECK-LABEL: name: t3
    ; CHECK: liveins: $x1
    ; CHECK: renamable $x3 = LI8 0
    ; CHECK: STD renamable $x3, 32, $x1
    ; CHECK: STD renamable $x3, 24, $x1
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    renamable $x3 = LI8 0
    STD killed renamable $x3, 32, $x1
    renamable $x3 = LI8 0
    STD renamable $x3, 24, $x1
    BLR8 implicit $lr8, implicit $rm

...
---
name:            t4
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1

    ; CHECK-LABEL: name: t4
    ; CHECK: liveins: $x1
    ; CHECK: renamable $x3 = LI8 0
    ; CHECK: STD renamable $x3, 16, $x1
    ; CHECK: renamable $x4 = ADDI8 renamable $x3, 8
    ; CHECK: STD killed renamable $x3, 8, $x1
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    renamable $x3 = LI8 0
    STD killed renamable $x3, 16, $x1
    renamable $x3 = LI8 0
    renamable $x4 = ADDI8 killed renamable $x3, 8
    renamable $x3 = LI8 0
    STD killed renamable $x3, 8, $x1
    BLR8 implicit $lr8, implicit $rm

...
---
name:            t5
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1

    ; CHECK-LABEL: name: t5
    ; CHECK: liveins: $x1
    ; CHECK: renamable $r3 = LI 0
    ; CHECK: STW renamable $r3, 16, $x1
    ; CHECK: STW killed renamable $r3, 12, $x1
    ; CHECK: renamable $r3 = LI 1
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    renamable $r3 = LI 0
    STW killed renamable $r3, 16, $x1
    renamable $r3 = LI 0
    STW killed renamable $r3, 12, $x1
    renamable $r3 = LI 1
    BLR8 implicit $lr8, implicit $rm

...
---
name:            t6
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1

    ; CHECK-LABEL: name: t6
    ; CHECK: liveins: $x1
    ; CHECK: renamable $x3 = LI8 0
    ; CHECK: renamable $x4 = LI8 1
    ; CHECK: STD renamable $x3, 32, $x1
    ; CHECK: STD renamable $x4, 24, $x1
    ; CHECK: STD killed renamable $x3, 16, $x1
    ; CHECK: STD killed renamable $x4, 8, $x1
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    renamable $x3 = LI8 0
    renamable $x4 = LI8 1
    STD killed renamable $x3, 32, $x1
    STD killed renamable $x4, 24, $x1
    renamable $x3 = LI8 0
    renamable $x4 = LI8 1
    STD killed renamable $x3, 16, $x1
    STD killed renamable $x4, 8, $x1
    BLR8 implicit $lr8, implicit $rm

...
---
name:            t7
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1, $x4

    ; CHECK-LABEL: name: t7
    ; CHECK: liveins: $x1, $x4
    ; CHECK: renamable $x3 = LI8 0
    ; CHECK: STD killed renamable $x3, 32, $x1
    ; CHECK: renamable $x3 = ADDI8 $x4, 6
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    renamable $x3 = LI8 0
    STD killed renamable $x3, 32, $x1
    renamable $x3 = ADDI8 $x4, 6
    BLR8 implicit $lr8, implicit $rm

...
---
name:            t8
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1

    ; CHECK-LABEL: name: t8
    ; CHECK: liveins: $x1
    ; CHECK: renamable $x3 = LI8 0
    ; CHECK: STD renamable $x3, 32, $x1
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    renamable $x3 = LI8 0
    STD killed renamable $x3, 32, $x1
    renamable $x3 = LI8 0
    BLR8 implicit $lr8, implicit $rm

...
---
name:            t9
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: t9
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK:   liveins: $x3
  ; CHECK:   renamable $r4 = LI 0, implicit-def $x4
  ; CHECK:   renamable $x24 = RLDICL renamable $x4, 0, 32
  ; CHECK:   renamable $cr0 = CMPLDI renamable $x3, 0
  ; CHECK:   BCC 68, killed renamable $cr0, %bb.1
  ; CHECK:   B %bb.2
  ; CHECK: bb.1:
  ; CHECK:   liveins: $r4, $x1
  ; CHECK:   STW killed renamable $r4, 16, $x1
  ; CHECK:   BLR8 implicit $lr8, implicit $rm
  ; CHECK: bb.2:
  ; CHECK:   liveins: $r4, $x1
  ; CHECK:   STW killed renamable $r4, 32, $x1
  ; CHECK:   BLR8 implicit $lr8, implicit $rm
  bb.0.entry:
    liveins: $x3
    successors: %bb.8, %bb.7

    renamable $r4 = LI 0, implicit-def $x4
    renamable $x24 = RLDICL killed renamable $x4, 0 , 32
    renamable $cr0 = CMPLDI renamable $x3, 0
    renamable $r4 = LI 0
    BCC 68, killed renamable $cr0, %bb.7
    B %bb.8

  bb.7:
    liveins: $r4, $x1
    STW killed renamable $r4, 16, $x1
    BLR8 implicit $lr8, implicit $rm

  bb.8:
    liveins: $r4, $x1
    STW killed renamable $r4, 32, $x1
    BLR8 implicit $lr8, implicit $rm

...
---
name:            t10
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1

    ; CHECK-LABEL: name: t10
    ; CHECK: liveins: $x1
    ; CHECK: renamable $x3 = LI8 24
    ; CHECK: STD killed renamable $x3, 16, $x1
    ; CHECK: renamable $r3 = LI 0
    ; CHECK: STW killed renamable $r3, 26, $x1
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    renamable $x3 = LI8 24
    STD killed renamable $x3, 16, $x1
    renamable $r3 = LI 0
    STW killed renamable $r3, 26, $x1
    BLR8 implicit $lr8, implicit $rm

...
---
name:            LIS8
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1

    ; CHECK-LABEL: name: LIS8
    ; CHECK: liveins: $x1
    ; CHECK: renamable $x3 = LIS8 0
    ; CHECK: STD renamable $x3, 16, $x1
    ; CHECK: STD killed renamable $x3, 8, $x1
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    renamable $x3 = LIS8 0
    STD killed renamable $x3, 16, $x1
    renamable $x3 = LIS8 0
    STD killed renamable $x3, 8, $x1
    BLR8 implicit $lr8, implicit $rm

...
---
name:            LIS
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1

    ; CHECK-LABEL: name: LIS
    ; CHECK: liveins: $x1
    ; CHECK: renamable $r3 = LIS 0
    ; CHECK: STW renamable $r3, 16, $x1
    ; CHECK: STW killed renamable $r3, 12, $x1
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    renamable $r3 = LIS 0
    STW killed renamable $r3, 16, $x1
    renamable $r3 = LIS 0
    STW killed renamable $r3, 12, $x1
    BLR8 implicit $lr8, implicit $rm

...
---
name:            modify_and_kill_the_reg_in_the_same_inst
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:

    ; CHECK-LABEL: name: modify_and_kill_the_reg_in_the_same_inst
    ; CHECK: renamable $x6 = LI8 1
    ; CHECK: renamable $x6 = RLDICR killed renamable $x6, 44, 19
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    renamable $x6 = LI8 1
    renamable $x6 = RLDICR killed renamable $x6, 44, 19
    BLR8 implicit $lr8, implicit $rm

...
---
name:            dead_load_immediate_followed_by_a_redundancy
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1

    ; CHECK-LABEL: name: dead_load_immediate_followed_by_a_redundancy
    ; CHECK: liveins: $x1
    ; CHECK: renamable $r3 = LI 128
    ; CHECK: renamable $x4 = ADDI8 $x1, -128
    ; CHECK: renamable $x5 = ADDI8 $x1, -128
    ; CHECK: STW killed renamable $r3, 16, $x4
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    dead renamable $r3 = LI 128
    renamable $x4 = ADDI8 $x1, -128
    dead renamable $r3 = LI 128
    renamable $x5 = ADDI8 $x1, -128
    renamable $r3 = LI 128
    STW killed renamable $r3, 16, $x4
    BLR8 implicit $lr8, implicit $rm

...
---
name:            overwrite_reg_before_killed
alignment:       16
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x1

    ; CHECK-LABEL: name: overwrite_reg_before_killed
    ; CHECK: liveins: $x1
    ; CHECK: renamable $x3 = LI8 0
    ; CHECK: STD renamable $x3, 16, $x1
    ; CHECK: STD killed renamable $x3, 8, $x1
    ; CHECK: BLR8 implicit $lr8, implicit $rm
    renamable $x3 = LI8 0
    STD renamable $x3, 16, $x1
    renamable $x3 = LI8 0
    STD killed renamable $x3, 8, $x1
    BLR8 implicit $lr8, implicit $rm

...