llvm/test/CodeGen/PowerPC/optimize-vector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN:   FileCheck %s

define dso_local <16 x i8> @x2(<16 x i8> noundef %x) {
; CHECK-LABEL: x2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vaddubm v2, v2, v2
; CHECK-NEXT:    blr
entry:
  %add = shl <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
  ret <16 x i8> %add
}

define dso_local <8 x i16> @x2h(<8 x i16> noundef %x) {
; CHECK-LABEL: x2h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vadduhm v2, v2, v2
; CHECK-NEXT:    blr
entry:
  %add = shl <8 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
  ret <8 x i16> %add
}

define dso_local <4 x i32> @x2w(<4 x i32> noundef %x) {
; CHECK-LABEL: x2w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vadduwm v2, v2, v2
; CHECK-NEXT:    blr
entry:
  %add = shl <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
  ret <4 x i32> %add
}

define dso_local <2 x i64> @x2d(<2 x i64> noundef %x) {
; CHECK-LABEL: x2d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
; CHECK-NEXT:    addi r3, r3, .LCPI3_0@toc@l
; CHECK-NEXT:    lxvd2x v3, 0, r3
; CHECK-NEXT:    vsld v2, v2, v3
; CHECK-NEXT:    blr
entry:
  %add = shl <2 x i64> %x, <i64 1, i64 1>
  ret <2 x i64> %add
}