llvm/test/Transforms/SLPVectorizer/X86/reduce-or-bitpack-split.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=x86_64-- | FileCheck %s

; The reduction is split into two vector parts and both are modeled as a
; bitfield pack, so no vector value is left for the final reduction combine.

define i64 @test(i8 %x, <4 x i8> %v) {
; CHECK-LABEL: define i64 @test(
; CHECK-SAME: i8 [[X:%.*]], <4 x i8> [[V:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0
; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> poison, <4 x i32> zeroinitializer
; CHECK-NEXT:    [[TMP2:%.*]] = or <4 x i8> [[TMP1]], splat (i8 1)
; CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <4 x i8> [[V]], <4 x i8> zeroinitializer, <8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT:    [[TMP6:%.*]] = bitcast <8 x i8> [[TMP5]] to i64
; CHECK-NEXT:    [[OP_RDX:%.*]] = or disjoint i64 [[TMP4]], [[TMP6]]
; CHECK-NEXT:    ret i64 [[OP_RDX]]
;
entry:
  %a4 = or i8 %x, 1
  %v2 = extractelement <4 x i8> %v, i64 2
  %a6 = or i8 %x, 1
  %e6 = zext i8 %a6 to i64
  %s6 = shl nuw nsw i64 %e6, 8
  %v1 = extractelement <4 x i8> %v, i64 1
  %e1 = zext i8 %v1 to i64
  %s1 = shl nuw nsw i64 %e1, 48
  %v0 = extractelement <4 x i8> %v, i64 0
  %e0 = zext i8 %v0 to i64
  %s0 = shl nuw i64 %e0, 56
  %a7 = or i8 %x, 1
  %e7 = zext i8 %a7 to i64
  %v3 = extractelement <4 x i8> %v, i64 3
  %a5 = or i8 %x, 1
  %e5 = zext i8 %a5 to i64
  %s5 = shl nuw nsw i64 %e5, 16
  %e2 = zext i8 %v2 to i64
  %s2 = shl nuw nsw i64 %e2, 40
  %r0 = or disjoint i64 %s5, %s2
  %r1 = or disjoint i64 %s6, %s1
  %r2 = or disjoint i64 %s0, %e7
  %r3 = or disjoint i64 %r1, %r2
  %r4 = or disjoint i64 %r0, %r3
  %e4 = zext i8 %a4 to i64
  %s4 = shl nuw nsw i64 %e4, 24
  %r5 = or disjoint i64 %r4, %s4
  %e3 = zext i8 %v3 to i64
  %s3 = shl nuw nsw i64 %e3, 32
  %r6 = or disjoint i64 %r5, %s3
  ret i64 %r6
}