llvm/test/Transforms/LoopVectorize/RISCV/live-out.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt < %s -S -p loop-vectorize -mtriple riscv64 -mattr=+v -vplan-verify-each | FileCheck %s --check-prefix=RV64
; RUN: opt < %s -S -p loop-vectorize -mtriple riscv32 -mattr=+v -vplan-verify-each | FileCheck %s --check-prefix=RV32
; RUN: opt < %s -S -p loop-vectorize -mtriple riscv32 -mattr=+zve32x,+zvl128b -vplan-verify-each | FileCheck %s --check-prefix=ZVE32X

; Make sure that we generate a VPInstruction::LastActiveLane that matches the
; targets index type, i.e. i64 on RV64 and i32 on RV32.  Otherwise on rv32 with
; zve32x we return an invalid cost for cttz.elts with scalable VFs.

define i32 @live_out(ptr %p, i64 %n) {
; RV64-LABEL: define i32 @live_out(
; RV64-SAME: ptr [[P:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
; RV64-NEXT:  [[ENTRY:.*:]]
; RV64-NEXT:    br label %[[VECTOR_PH:.*]]
; RV64:       [[VECTOR_PH]]:
; RV64-NEXT:    br label %[[VECTOR_BODY:.*]]
; RV64:       [[VECTOR_BODY]]:
; RV64-NEXT:    [[CURRENT_ITERATION_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV64-NEXT:    [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV64-NEXT:    [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; RV64-NEXT:    [[TMP1:%.*]] = getelementptr i32, ptr [[P]], i64 [[CURRENT_ITERATION_IV]]
; RV64-NEXT:    [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP1]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP0]])
; RV64-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP0]] to i64
; RV64-NEXT:    [[CURRENT_ITERATION_NEXT]] = add i64 [[TMP2]], [[CURRENT_ITERATION_IV]]
; RV64-NEXT:    [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP2]]
; RV64-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
; RV64-NEXT:    br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; RV64:       [[MIDDLE_BLOCK]]:
; RV64-NEXT:    [[TMP4:%.*]] = sub i64 [[TMP2]], 1
; RV64-NEXT:    [[TMP5:%.*]] = extractelement <vscale x 4 x i32> [[VP_OP_LOAD]], i64 [[TMP4]]
; RV64-NEXT:    br label %[[EXIT:.*]]
; RV64:       [[EXIT]]:
; RV64-NEXT:    ret i32 [[TMP5]]
;
; RV32-LABEL: define i32 @live_out(
; RV32-SAME: ptr [[P:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
; RV32-NEXT:  [[ENTRY:.*:]]
; RV32-NEXT:    br label %[[VECTOR_PH:.*]]
; RV32:       [[VECTOR_PH]]:
; RV32-NEXT:    br label %[[VECTOR_BODY:.*]]
; RV32:       [[VECTOR_BODY]]:
; RV32-NEXT:    [[CURRENT_ITERATION_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV32-NEXT:    [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV32-NEXT:    [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; RV32-NEXT:    [[TMP1:%.*]] = getelementptr i32, ptr [[P]], i64 [[CURRENT_ITERATION_IV]]
; RV32-NEXT:    [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP1]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP0]])
; RV32-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP0]] to i64
; RV32-NEXT:    [[CURRENT_ITERATION_NEXT]] = add i64 [[TMP2]], [[CURRENT_ITERATION_IV]]
; RV32-NEXT:    [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP2]]
; RV32-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
; RV32-NEXT:    br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; RV32:       [[MIDDLE_BLOCK]]:
; RV32-NEXT:    [[TMP4:%.*]] = sub i32 [[TMP0]], 1
; RV32-NEXT:    [[TMP5:%.*]] = extractelement <vscale x 4 x i32> [[VP_OP_LOAD]], i32 [[TMP4]]
; RV32-NEXT:    br label %[[EXIT:.*]]
; RV32:       [[EXIT]]:
; RV32-NEXT:    ret i32 [[TMP5]]
;
; ZVE32X-LABEL: define i32 @live_out(
; ZVE32X-SAME: ptr [[P:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
; ZVE32X-NEXT:  [[ENTRY:.*:]]
; ZVE32X-NEXT:    br label %[[VECTOR_PH:.*]]
; ZVE32X:       [[VECTOR_PH]]:
; ZVE32X-NEXT:    br label %[[VECTOR_BODY:.*]]
; ZVE32X:       [[VECTOR_BODY]]:
; ZVE32X-NEXT:    [[CURRENT_ITERATION_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
; ZVE32X-NEXT:    [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; ZVE32X-NEXT:    [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; ZVE32X-NEXT:    [[TMP1:%.*]] = getelementptr i32, ptr [[P]], i64 [[CURRENT_ITERATION_IV]]
; ZVE32X-NEXT:    [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP1]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP0]])
; ZVE32X-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP0]] to i64
; ZVE32X-NEXT:    [[CURRENT_ITERATION_NEXT]] = add i64 [[TMP2]], [[CURRENT_ITERATION_IV]]
; ZVE32X-NEXT:    [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP2]]
; ZVE32X-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
; ZVE32X-NEXT:    br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; ZVE32X:       [[MIDDLE_BLOCK]]:
; ZVE32X-NEXT:    [[TMP4:%.*]] = sub i32 [[TMP0]], 1
; ZVE32X-NEXT:    [[TMP5:%.*]] = extractelement <vscale x 4 x i32> [[VP_OP_LOAD]], i32 [[TMP4]]
; ZVE32X-NEXT:    br label %[[EXIT:.*]]
; ZVE32X:       [[EXIT]]:
; ZVE32X-NEXT:    ret i32 [[TMP5]]
;
entry:
  br label %loop

loop:
  %iv = phi i64 [0, %entry], [%iv.next, %loop]
  %gep = getelementptr i32, ptr %p, i64 %iv
  %ld = load i32, ptr %gep
  %iv.next = add i64 %iv, 1
  %ec = icmp eq i64 %iv.next, %n
  br i1 %ec, label %exit, label %loop

exit:
  %ret = phi i32 [ %ld, %loop ]
  ret i32 %ret
}