llvm/test/Transforms/LoopInterchange/pr43326.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -passes=loop-interchange -cache-line-size=64 -loop-interchange-profitabilities=ignore -S | FileCheck %s

@a = global i32 0
@b = global i8 0
@c = global i32 0
@d = global i32 0
@e = global [1 x [1 x i32]] zeroinitializer

define void @pr43326() {
; CHECK-LABEL: define void @pr43326() {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr @a, align 4
; CHECK-NEXT:    [[TOBOOL_NOT2:%.*]] = icmp eq i32 [[TMP0]], 0
; CHECK-NEXT:    br i1 [[TOBOOL_NOT2]], label %[[FOR_END14:.*]], label %[[OUTER_PREHEADER:.*]]
; CHECK:       [[OUTER_PREHEADER]]:
; CHECK-NEXT:    [[D_PROMOTED:%.*]] = load i32, ptr @d, align 4
; CHECK-NEXT:    [[A_PROMOTED:%.*]] = load i32, ptr @a, align 4
; CHECK-NEXT:    br label %[[OUTER_HEADER:.*]]
; CHECK:       [[OUTER_HEADER]]:
; CHECK-NEXT:    [[INC1312:%.*]] = phi i32 [ [[A_PROMOTED]], %[[OUTER_PREHEADER]] ], [ [[INC13:%.*]], %[[FOR_INC12:.*]] ]
; CHECK-NEXT:    [[XOR_LCSSA_LCSSA11:%.*]] = phi i32 [ [[D_PROMOTED]], %[[OUTER_PREHEADER]] ], [ [[XOR_LCSSA_LCSSA:%.*]], %[[FOR_INC12]] ]
; CHECK-NEXT:    br label %[[INNER1_HEADER_PREHEADER:.*]]
; CHECK:       [[INNER1_HEADER_PREHEADER]]:
; CHECK-NEXT:    br label %[[INNER1_HEADER:.*]]
; CHECK:       [[INNER1_HEADER]]:
; CHECK-NEXT:    [[J:%.*]] = phi i8 [ [[TMP5:%.*]], %[[FOR_INC10_SPLIT:.*]] ], [ 0, %[[INNER1_HEADER_PREHEADER]] ]
; CHECK-NEXT:    [[XOR_LCSSA9:%.*]] = phi i32 [ [[XOR_LCSSA:%.*]], %[[FOR_INC10_SPLIT]] ], [ [[XOR_LCSSA_LCSSA11]], %[[INNER1_HEADER_PREHEADER]] ]
; CHECK-NEXT:    br label %[[INNER2_HEADER_PREHEADER:.*]]
; CHECK:       [[INNER1_HEADER_SPLIT:.*]]:
; CHECK-NEXT:    [[IDXPROM8:%.*]] = sext i8 [[J]] to i64
; CHECK-NEXT:    br label %[[INNER2_HEADER_SPLIT:.*]]
; CHECK:       [[INNER2_HEADER_PREHEADER]]:
; CHECK-NEXT:    br label %[[INNER2_HEADER:.*]]
; CHECK:       [[INNER2_HEADER]]:
; CHECK-NEXT:    [[K:%.*]] = phi i32 [ [[TMP2:%.*]], %[[FOR_INC_SPLIT:.*]] ], [ 0, %[[INNER2_HEADER_PREHEADER]] ]
; CHECK-NEXT:    [[XOR5:%.*]] = phi i32 [ [[XOR:%.*]], %[[FOR_INC_SPLIT]] ], [ [[XOR_LCSSA9]], %[[INNER2_HEADER_PREHEADER]] ]
; CHECK-NEXT:    br label %[[INNER1_HEADER_SPLIT]]
; CHECK:       [[INNER2_HEADER_SPLIT]]:
; CHECK-NEXT:    [[IDXPROM:%.*]] = sext i32 [[K]] to i64
; CHECK-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds [1 x [1 x i32]], ptr @e, i64 0, i64 [[IDXPROM]], i64 [[IDXPROM8]]
; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX9]], align 4
; CHECK-NEXT:    [[XOR]] = xor i32 [[XOR5]], [[TMP1]]
; CHECK-NEXT:    br label %[[FOR_INC:.*]]
; CHECK:       [[FOR_INC]]:
; CHECK-NEXT:    [[K_NEXT:%.*]] = add nsw i32 [[K]], 1
; CHECK-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[K_NEXT]], 42
; CHECK-NEXT:    br label %[[FOR_END:.*]]
; CHECK:       [[FOR_INC_SPLIT]]:
; CHECK-NEXT:    [[TMP2]] = add nsw i32 [[K]], 1
; CHECK-NEXT:    [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 42
; CHECK-NEXT:    br i1 [[TMP3]], label %[[INNER2_HEADER]], label %[[FOR_INC10_SPLIT]]
; CHECK:       [[FOR_END]]:
; CHECK-NEXT:    br label %[[FOR_INC10:.*]]
; CHECK:       [[FOR_INC10]]:
; CHECK-NEXT:    [[J_NEXT:%.*]] = add i8 [[J]], -1
; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i8 [[J_NEXT]], -10
; CHECK-NEXT:    br label %[[FOR_INC_SPLIT]]
; CHECK:       [[FOR_INC10_SPLIT]]:
; CHECK-NEXT:    [[XOR_LCSSA]] = phi i32 [ [[XOR]], %[[FOR_INC_SPLIT]] ]
; CHECK-NEXT:    [[TMP4:%.*]] = phi i32 [ [[TMP2]], %[[FOR_INC_SPLIT]] ]
; CHECK-NEXT:    [[TMP5]] = add i8 [[J]], -1
; CHECK-NEXT:    [[TMP6:%.*]] = icmp sgt i8 [[TMP5]], -10
; CHECK-NEXT:    br i1 [[TMP6]], label %[[INNER1_HEADER]], label %[[FOR_END11:.*]]
; CHECK:       [[FOR_END11]]:
; CHECK-NEXT:    [[XOR_LCSSA_LCSSA]] = phi i32 [ [[XOR_LCSSA]], %[[FOR_INC10_SPLIT]] ]
; CHECK-NEXT:    [[DEC_LCSSA:%.*]] = phi i8 [ [[TMP5]], %[[FOR_INC10_SPLIT]] ]
; CHECK-NEXT:    [[INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[TMP4]], %[[FOR_INC10_SPLIT]] ]
; CHECK-NEXT:    br label %[[FOR_INC12]]
; CHECK:       [[FOR_INC12]]:
; CHECK-NEXT:    [[INC13]] = add nsw i32 [[INC1312]], 1
; CHECK-NEXT:    [[TOBOOL_NOT:%.*]] = icmp slt i32 [[INC13]], 42
; CHECK-NEXT:    br i1 [[TOBOOL_NOT]], label %[[OUTER_HEADER]], label %[[FOR_COND_FOR_END14_CRIT_EDGE:.*]]
; CHECK:       [[FOR_COND_FOR_END14_CRIT_EDGE]]:
; CHECK-NEXT:    [[INC13_LCSSA:%.*]] = phi i32 [ [[INC13]], %[[FOR_INC12]] ]
; CHECK-NEXT:    [[INC_LCSSA_LCSSA_LCSSA:%.*]] = phi i32 [ [[INC_LCSSA_LCSSA]], %[[FOR_INC12]] ]
; CHECK-NEXT:    [[XOR_LCSSA_LCSSA_LCSSA:%.*]] = phi i32 [ [[XOR_LCSSA_LCSSA]], %[[FOR_INC12]] ]
; CHECK-NEXT:    [[DEC_LCSSA_LCSSA:%.*]] = phi i8 [ [[DEC_LCSSA]], %[[FOR_INC12]] ]
; CHECK-NEXT:    store i8 [[DEC_LCSSA_LCSSA]], ptr @b, align 1
; CHECK-NEXT:    store i32 [[XOR_LCSSA_LCSSA_LCSSA]], ptr @d, align 4
; CHECK-NEXT:    store i32 [[INC_LCSSA_LCSSA_LCSSA]], ptr @c, align 4
; CHECK-NEXT:    store i32 [[INC13_LCSSA]], ptr @a, align 4
; CHECK-NEXT:    br label %[[FOR_END14]]
; CHECK:       [[FOR_END14]]:
; CHECK-NEXT:    ret void
;
entry:
  %0 = load i32, ptr @a
  %tobool.not2 = icmp eq i32 %0, 0
  br i1 %tobool.not2, label %for.end14, label %outer.preheader

outer.preheader:                                   ; preds = %entry
  %d.promoted = load i32, ptr @d
  %a.promoted = load i32, ptr @a
  br label %outer.header

outer.header:                                         ; preds = %outer.preheader, %for.inc12
  %inc1312 = phi i32 [ %a.promoted, %outer.preheader ], [ %inc13, %for.inc12 ]
  %xor.lcssa.lcssa11 = phi i32 [ %d.promoted, %outer.preheader ], [ %xor.lcssa.lcssa, %for.inc12 ]
  br label %inner1.header

inner1.header:                                        ; preds = %outer.header, %for.inc10
  %xor.lcssa9 = phi i32 [ %xor.lcssa.lcssa11, %outer.header ], [ %xor.lcssa, %for.inc10 ]
  %j = phi i8 [ 0, %outer.header ], [ %j.next, %for.inc10 ]
  %idxprom8 = sext i8 %j to i64
  br label %inner2.header

inner2.header:                                        ; preds = %inner1.header, %for.inc
  %xor5 = phi i32 [ %xor.lcssa9, %inner1.header ], [ %xor, %for.inc ]
  %k = phi i32 [ 0, %inner1.header ], [ %k.next, %for.inc ]
  %idxprom = sext i32 %k to i64
  %arrayidx9 = getelementptr inbounds [1 x [1 x i32]], ptr @e, i64 0, i64 %idxprom, i64 %idxprom8
  %1 = load i32, ptr %arrayidx9
  %xor = xor i32 %xor5, %1
  br label %for.inc

for.inc:                                          ; preds = %inner2.header
  %k.next = add nsw i32 %k, 1
  %cmp5 = icmp slt i32 %k.next, 42
  br i1 %cmp5, label %inner2.header, label %for.end

for.end:                                          ; preds = %for.inc
  %xor.lcssa = phi i32 [ %xor, %for.inc ]
  %inc.lcssa = phi i32 [ %k.next, %for.inc ]
  br label %for.inc10

for.inc10:                                        ; preds = %for.end
  %j.next = add i8 %j, -1
  %cmp = icmp sgt i8 %j.next, -10
  br i1 %cmp, label %inner1.header, label %for.end11

for.end11:                                        ; preds = %for.inc10
  %xor.lcssa.lcssa = phi i32 [ %xor.lcssa, %for.inc10 ]
  %dec.lcssa = phi i8 [ %j.next, %for.inc10 ]
  %inc.lcssa.lcssa = phi i32 [ %inc.lcssa, %for.inc10 ]
  br label %for.inc12

for.inc12:                                        ; preds = %for.end11
  %inc13 = add nsw i32 %inc1312, 1
  %tobool.not = icmp slt i32 %inc13, 42
  br i1 %tobool.not, label %outer.header, label %for.cond.for.end14_crit_edge

for.cond.for.end14_crit_edge:                     ; preds = %for.inc12
  %inc13.lcssa = phi i32 [ %inc13, %for.inc12 ]
  %inc.lcssa.lcssa.lcssa = phi i32 [ %inc.lcssa.lcssa, %for.inc12 ]
  %xor.lcssa.lcssa.lcssa = phi i32 [ %xor.lcssa.lcssa, %for.inc12 ]
  %dec.lcssa.lcssa = phi i8 [ %dec.lcssa, %for.inc12 ]
  store i8 %dec.lcssa.lcssa, ptr @b
  store i32 %xor.lcssa.lcssa.lcssa, ptr @d
  store i32 %inc.lcssa.lcssa.lcssa, ptr @c
  store i32 %inc13.lcssa, ptr @a
  br label %for.end14

for.end14:                                        ; preds = %for.cond.for.end14_crit_edge, %entry
  ret void
}