| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ |
| ; RUN: | FileCheck %s -check-prefixes=I,RV32I |
| ; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \ |
| ; RUN: | FileCheck %s -check-prefixes=ZBB,RV32ZBB |
| ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ |
| ; RUN: | FileCheck %s -check-prefixes=I,RV64I |
| ; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \ |
| ; RUN: | FileCheck %s -check-prefixes=ZBB,RV64ZBB |
| |
| define i32 @orc_b_i32_mul255(i32 %x) nounwind { |
| ; RV32I-LABEL: orc_b_i32_mul255: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a1, 4112 |
| ; RV32I-NEXT: addi a1, a1, 257 |
| ; RV32I-NEXT: and a0, a0, a1 |
| ; RV32I-NEXT: slli a1, a0, 8 |
| ; RV32I-NEXT: sub a0, a1, a0 |
| ; RV32I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i32_mul255: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: lui a1, 4112 |
| ; ZBB-NEXT: addi a1, a1, 257 |
| ; ZBB-NEXT: and a0, a0, a1 |
| ; ZBB-NEXT: orc.b a0, a0 |
| ; ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_mul255: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a1, 4112 |
| ; RV64I-NEXT: addi a1, a1, 257 |
| ; RV64I-NEXT: and a0, a0, a1 |
| ; RV64I-NEXT: slli a1, a0, 8 |
| ; RV64I-NEXT: subw a0, a1, a0 |
| ; RV64I-NEXT: ret |
| entry: |
| %and = and i32 %x, 16843009 |
| %mul = mul i32 %and, 255 |
| ret i32 %mul |
| } |
| |
| |
| define i32 @orc_b_i32_sub_shl8x_x_lsb(i32 %x) { |
| ; RV32I-LABEL: orc_b_i32_sub_shl8x_x_lsb: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a1, 4112 |
| ; RV32I-NEXT: addi a1, a1, 257 |
| ; RV32I-NEXT: and a0, a0, a1 |
| ; RV32I-NEXT: slli a1, a0, 8 |
| ; RV32I-NEXT: sub a0, a1, a0 |
| ; RV32I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i32_sub_shl8x_x_lsb: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: lui a1, 4112 |
| ; ZBB-NEXT: addi a1, a1, 257 |
| ; ZBB-NEXT: and a0, a0, a1 |
| ; ZBB-NEXT: orc.b a0, a0 |
| ; ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_shl8x_x_lsb: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a1, 4112 |
| ; RV64I-NEXT: addi a1, a1, 257 |
| ; RV64I-NEXT: and a0, a0, a1 |
| ; RV64I-NEXT: slli a1, a0, 8 |
| ; RV64I-NEXT: subw a0, a1, a0 |
| ; RV64I-NEXT: ret |
| entry: |
| %and = and i32 %x, 16843009 |
| %sub = mul i32 %and, 255 |
| ret i32 %sub |
| } |
| |
| define i32 @orc_b_i32_sub_shl8x_x_lsb_preshifted(i32 %x){ |
| ; I-LABEL: orc_b_i32_sub_shl8x_x_lsb_preshifted: |
| ; I: # %bb.0: # %entry |
| ; I-NEXT: lui a1, 16 |
| ; I-NEXT: srli a0, a0, 11 |
| ; I-NEXT: addi a1, a1, 257 |
| ; I-NEXT: and a0, a0, a1 |
| ; I-NEXT: slli a1, a0, 8 |
| ; I-NEXT: sub a0, a1, a0 |
| ; I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i32_sub_shl8x_x_lsb_preshifted: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: lui a1, 16 |
| ; ZBB-NEXT: srli a0, a0, 11 |
| ; ZBB-NEXT: addi a1, a1, 257 |
| ; ZBB-NEXT: and a0, a0, a1 |
| ; ZBB-NEXT: orc.b a0, a0 |
| ; ZBB-NEXT: ret |
| entry: |
| %shr = lshr i32 %x, 11 |
| %and = and i32 %shr, 16843009 |
| %sub = mul i32 %and, 255 |
| ret i32 %sub |
| } |
| |
| |
| define i32 @orc_b_i32_sub_shl8x_x_b1(i32 %x) { |
| ; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a1, 8224 |
| ; RV32I-NEXT: addi a1, a1, 514 |
| ; RV32I-NEXT: and a0, a0, a1 |
| ; RV32I-NEXT: slli a1, a0, 7 |
| ; RV32I-NEXT: srli a0, a0, 1 |
| ; RV32I-NEXT: sub a0, a1, a0 |
| ; RV32I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: lui a1, 8224 |
| ; ZBB-NEXT: addi a1, a1, 514 |
| ; ZBB-NEXT: and a0, a0, a1 |
| ; ZBB-NEXT: orc.b a0, a0 |
| ; ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b1: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a1, 8224 |
| ; RV64I-NEXT: addi a1, a1, 514 |
| ; RV64I-NEXT: and a0, a0, a1 |
| ; RV64I-NEXT: slli a1, a0, 7 |
| ; RV64I-NEXT: srli a0, a0, 1 |
| ; RV64I-NEXT: subw a0, a1, a0 |
| ; RV64I-NEXT: ret |
| entry: |
| %and = and i32 %x, 33686018 |
| %shl = shl i32 %and, 7 |
| %shr = lshr i32 %and, 1 |
| %sub = sub i32 %shl, %shr |
| ret i32 %sub |
| } |
| |
| |
| define i32 @orc_b_i32_sub_shl8x_x_b2(i32 %x) { |
| ; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b2: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a1, 16448 |
| ; RV32I-NEXT: addi a1, a1, 1028 |
| ; RV32I-NEXT: and a0, a0, a1 |
| ; RV32I-NEXT: slli a1, a0, 6 |
| ; RV32I-NEXT: srli a0, a0, 2 |
| ; RV32I-NEXT: sub a0, a1, a0 |
| ; RV32I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b2: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: lui a1, 16448 |
| ; ZBB-NEXT: addi a1, a1, 1028 |
| ; ZBB-NEXT: and a0, a0, a1 |
| ; ZBB-NEXT: orc.b a0, a0 |
| ; ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b2: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a1, 16448 |
| ; RV64I-NEXT: addi a1, a1, 1028 |
| ; RV64I-NEXT: and a0, a0, a1 |
| ; RV64I-NEXT: slli a1, a0, 6 |
| ; RV64I-NEXT: srli a0, a0, 2 |
| ; RV64I-NEXT: subw a0, a1, a0 |
| ; RV64I-NEXT: ret |
| entry: |
| %and = and i32 %x, 67372036 |
| %shl = shl i32 %and, 6 |
| %shr = lshr i32 %and, 2 |
| %sub = sub i32 %shl, %shr |
| ret i32 %sub |
| } |
| |
| |
| define i32 @orc_b_i32_sub_shl8x_x_b3(i32 %x) { |
| ; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b3: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a1, 32897 |
| ; RV32I-NEXT: addi a1, a1, -2040 |
| ; RV32I-NEXT: and a0, a0, a1 |
| ; RV32I-NEXT: slli a1, a0, 5 |
| ; RV32I-NEXT: srli a0, a0, 3 |
| ; RV32I-NEXT: sub a0, a1, a0 |
| ; RV32I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b3: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: lui a1, 32897 |
| ; ZBB-NEXT: addi a1, a1, -2040 |
| ; ZBB-NEXT: and a0, a0, a1 |
| ; ZBB-NEXT: orc.b a0, a0 |
| ; ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b3: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a1, 32897 |
| ; RV64I-NEXT: addi a1, a1, -2040 |
| ; RV64I-NEXT: and a0, a0, a1 |
| ; RV64I-NEXT: slli a1, a0, 5 |
| ; RV64I-NEXT: srli a0, a0, 3 |
| ; RV64I-NEXT: subw a0, a1, a0 |
| ; RV64I-NEXT: ret |
| entry: |
| %and = and i32 %x, 134744072 |
| %shl = shl i32 %and, 5 |
| %shr = lshr i32 %and, 3 |
| %sub = sub i32 %shl, %shr |
| ret i32 %sub |
| } |
| |
| |
| define i32 @orc_b_i32_sub_shl8x_x_b4(i32 %x) { |
| ; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b4: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a1, 65793 |
| ; RV32I-NEXT: addi a1, a1, 16 |
| ; RV32I-NEXT: and a0, a0, a1 |
| ; RV32I-NEXT: slli a1, a0, 4 |
| ; RV32I-NEXT: srli a0, a0, 4 |
| ; RV32I-NEXT: sub a0, a1, a0 |
| ; RV32I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b4: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: lui a1, 65793 |
| ; ZBB-NEXT: addi a1, a1, 16 |
| ; ZBB-NEXT: and a0, a0, a1 |
| ; ZBB-NEXT: orc.b a0, a0 |
| ; ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b4: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a1, 65793 |
| ; RV64I-NEXT: addi a1, a1, 16 |
| ; RV64I-NEXT: and a0, a0, a1 |
| ; RV64I-NEXT: slli a1, a0, 4 |
| ; RV64I-NEXT: srli a0, a0, 4 |
| ; RV64I-NEXT: subw a0, a1, a0 |
| ; RV64I-NEXT: ret |
| entry: |
| %and = and i32 %x, 269488144 |
| %shl = shl i32 %and, 4 |
| %shr = lshr i32 %and, 4 |
| %sub = sub i32 %shl, %shr |
| ret i32 %sub |
| } |
| |
| |
| define i32 @orc_b_i32_sub_shl8x_x_b5(i32 %x) { |
| ; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b5: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a1, 131586 |
| ; RV32I-NEXT: addi a1, a1, 32 |
| ; RV32I-NEXT: and a0, a0, a1 |
| ; RV32I-NEXT: slli a1, a0, 3 |
| ; RV32I-NEXT: srli a0, a0, 5 |
| ; RV32I-NEXT: sub a0, a1, a0 |
| ; RV32I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b5: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: lui a1, 131586 |
| ; ZBB-NEXT: addi a1, a1, 32 |
| ; ZBB-NEXT: and a0, a0, a1 |
| ; ZBB-NEXT: orc.b a0, a0 |
| ; ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b5: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a1, 131586 |
| ; RV64I-NEXT: addi a1, a1, 32 |
| ; RV64I-NEXT: and a0, a0, a1 |
| ; RV64I-NEXT: slli a1, a0, 3 |
| ; RV64I-NEXT: srli a0, a0, 5 |
| ; RV64I-NEXT: subw a0, a1, a0 |
| ; RV64I-NEXT: ret |
| entry: |
| %and = and i32 %x, 538976288 |
| %shl = shl i32 %and, 3 |
| %shr = lshr i32 %and, 5 |
| %sub = sub i32 %shl, %shr |
| ret i32 %sub |
| } |
| |
| |
| define i32 @orc_b_i32_sub_shl8x_x_b6(i32 %x) { |
| ; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b6: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a1, 263172 |
| ; RV32I-NEXT: addi a1, a1, 64 |
| ; RV32I-NEXT: and a0, a0, a1 |
| ; RV32I-NEXT: slli a1, a0, 2 |
| ; RV32I-NEXT: srli a0, a0, 6 |
| ; RV32I-NEXT: sub a0, a1, a0 |
| ; RV32I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b6: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: lui a1, 263172 |
| ; ZBB-NEXT: addi a1, a1, 64 |
| ; ZBB-NEXT: and a0, a0, a1 |
| ; ZBB-NEXT: orc.b a0, a0 |
| ; ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b6: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a1, 263172 |
| ; RV64I-NEXT: addi a1, a1, 64 |
| ; RV64I-NEXT: and a0, a0, a1 |
| ; RV64I-NEXT: slli a1, a0, 2 |
| ; RV64I-NEXT: srli a0, a0, 6 |
| ; RV64I-NEXT: subw a0, a1, a0 |
| ; RV64I-NEXT: ret |
| entry: |
| %and = and i32 %x, 1077952576 |
| %shl = shl i32 %and, 2 |
| %shr = lshr i32 %and, 6 |
| %sub = sub i32 %shl, %shr |
| ret i32 %sub |
| } |
| |
| |
| define i32 @orc_b_i32_sub_shl8x_x_b7(i32 %x) { |
| ; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b7: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a1, 526344 |
| ; RV32I-NEXT: addi a1, a1, 128 |
| ; RV32I-NEXT: and a0, a0, a1 |
| ; RV32I-NEXT: slli a1, a0, 1 |
| ; RV32I-NEXT: srli a0, a0, 7 |
| ; RV32I-NEXT: sub a0, a1, a0 |
| ; RV32I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b7: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: lui a1, 526344 |
| ; ZBB-NEXT: addi a1, a1, 128 |
| ; ZBB-NEXT: and a0, a0, a1 |
| ; ZBB-NEXT: orc.b a0, a0 |
| ; ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b7: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a1, 65793 |
| ; RV64I-NEXT: slli a1, a1, 3 |
| ; RV64I-NEXT: lui a2, 2056 |
| ; RV64I-NEXT: addi a1, a1, 128 |
| ; RV64I-NEXT: addi a2, a2, 128 |
| ; RV64I-NEXT: and a1, a0, a1 |
| ; RV64I-NEXT: and a0, a0, a2 |
| ; RV64I-NEXT: slli a0, a0, 1 |
| ; RV64I-NEXT: srli a1, a1, 7 |
| ; RV64I-NEXT: sub a0, a0, a1 |
| ; RV64I-NEXT: ret |
| entry: |
| %and = and i32 %x, 2155905152 |
| %shl = shl i32 %and, 1 |
| %shr = lshr i32 %and, 7 |
| %sub = sub i32 %shl, %shr |
| ret i32 %sub |
| } |
| |
| define i32 @orc_b_i32_sub_shl8x_x_b1_shl_used(i32 %x, ptr %arr) { |
| ; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_shl_used: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a2, 8224 |
| ; RV32I-NEXT: addi a2, a2, 514 |
| ; RV32I-NEXT: and a0, a0, a2 |
| ; RV32I-NEXT: slli a2, a0, 7 |
| ; RV32I-NEXT: srli a3, a0, 1 |
| ; RV32I-NEXT: sub a0, a2, a3 |
| ; RV32I-NEXT: sw a3, 0(a1) |
| ; RV32I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_shl_used: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: lui a2, 8224 |
| ; ZBB-NEXT: addi a2, a2, 514 |
| ; ZBB-NEXT: and a2, a0, a2 |
| ; ZBB-NEXT: orc.b a0, a2 |
| ; ZBB-NEXT: srli a2, a2, 1 |
| ; ZBB-NEXT: sw a2, 0(a1) |
| ; ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b1_shl_used: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a2, 8224 |
| ; RV64I-NEXT: addi a2, a2, 514 |
| ; RV64I-NEXT: and a0, a0, a2 |
| ; RV64I-NEXT: slli a2, a0, 7 |
| ; RV64I-NEXT: srli a3, a0, 1 |
| ; RV64I-NEXT: subw a0, a2, a3 |
| ; RV64I-NEXT: sw a3, 0(a1) |
| ; RV64I-NEXT: ret |
| entry: |
| %and = and i32 %x, 33686018 |
| %shl = shl i32 %and, 7 |
| %shr = lshr i32 %and, 1 |
| store i32 %shr, ptr %arr, align 4 |
| %sub = sub i32 %shl, %shr |
| ret i32 %sub |
| } |
| |
| define i32 @orc_b_i32_sub_shl8x_x_b1_srl_used(i32 %x, ptr %arr) { |
| ; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_srl_used: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a2, 8224 |
| ; RV32I-NEXT: addi a2, a2, 514 |
| ; RV32I-NEXT: and a0, a0, a2 |
| ; RV32I-NEXT: slli a2, a0, 7 |
| ; RV32I-NEXT: srli a0, a0, 1 |
| ; RV32I-NEXT: sub a0, a2, a0 |
| ; RV32I-NEXT: sw a2, 0(a1) |
| ; RV32I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_srl_used: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: lui a2, 8224 |
| ; ZBB-NEXT: addi a2, a2, 514 |
| ; ZBB-NEXT: and a2, a0, a2 |
| ; ZBB-NEXT: orc.b a0, a2 |
| ; ZBB-NEXT: slli a2, a2, 7 |
| ; ZBB-NEXT: sw a2, 0(a1) |
| ; ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b1_srl_used: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a2, 8224 |
| ; RV64I-NEXT: addi a2, a2, 514 |
| ; RV64I-NEXT: lui a3, 4112 |
| ; RV64I-NEXT: and a2, a0, a2 |
| ; RV64I-NEXT: slli a0, a0, 7 |
| ; RV64I-NEXT: addi a3, a3, 256 |
| ; RV64I-NEXT: and a3, a0, a3 |
| ; RV64I-NEXT: srli a2, a2, 1 |
| ; RV64I-NEXT: sub a0, a3, a2 |
| ; RV64I-NEXT: sw a3, 0(a1) |
| ; RV64I-NEXT: ret |
| entry: |
| %and = and i32 %x, 33686018 |
| %shl = shl i32 %and, 7 |
| %shr = lshr i32 %and, 1 |
| store i32 %shl, ptr %arr, align 4 |
| %sub = sub i32 %shl, %shr |
| ret i32 %sub |
| } |
| |
| |
| define i32 @orc_b_i32_sub_shl8x_x_b1_not_used(i32 %x, ptr %arr) { |
| ; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_not_used: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a1, 8224 |
| ; RV32I-NEXT: addi a1, a1, 514 |
| ; RV32I-NEXT: and a0, a0, a1 |
| ; RV32I-NEXT: slli a1, a0, 7 |
| ; RV32I-NEXT: srli a0, a0, 1 |
| ; RV32I-NEXT: sub a0, a1, a0 |
| ; RV32I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_not_used: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: lui a1, 8224 |
| ; ZBB-NEXT: addi a1, a1, 514 |
| ; ZBB-NEXT: and a0, a0, a1 |
| ; ZBB-NEXT: orc.b a0, a0 |
| ; ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b1_not_used: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a1, 8224 |
| ; RV64I-NEXT: addi a1, a1, 514 |
| ; RV64I-NEXT: and a0, a0, a1 |
| ; RV64I-NEXT: slli a1, a0, 7 |
| ; RV64I-NEXT: srli a0, a0, 1 |
| ; RV64I-NEXT: subw a0, a1, a0 |
| ; RV64I-NEXT: ret |
| entry: |
| %and = and i32 %x, 33686018 |
| %shl = shl i32 %and, 7 |
| %shr = lshr i32 %and, 1 |
| %sub = sub i32 %shl, %shr |
| ret i32 %sub |
| } |
| |
| define i32 @orc_b_i32_sub_shl8x_x_shl_used(i32 %x, ptr %arr){ |
| ; RV32I-LABEL: orc_b_i32_sub_shl8x_x_shl_used: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a2, 4112 |
| ; RV32I-NEXT: addi a2, a2, 257 |
| ; RV32I-NEXT: and a0, a0, a2 |
| ; RV32I-NEXT: slli a2, a0, 8 |
| ; RV32I-NEXT: sub a0, a2, a0 |
| ; RV32I-NEXT: sw a2, 0(a1) |
| ; RV32I-NEXT: ret |
| ; |
| ; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_shl_used: |
| ; RV32ZBB: # %bb.0: # %entry |
| ; RV32ZBB-NEXT: lui a2, 4112 |
| ; RV32ZBB-NEXT: addi a2, a2, 257 |
| ; RV32ZBB-NEXT: and a0, a0, a2 |
| ; RV32ZBB-NEXT: slli a2, a0, 8 |
| ; RV32ZBB-NEXT: sub a0, a2, a0 |
| ; RV32ZBB-NEXT: sw a2, 0(a1) |
| ; RV32ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_shl8x_x_shl_used: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a2, 4112 |
| ; RV64I-NEXT: addi a3, a2, 257 |
| ; RV64I-NEXT: slli a4, a0, 8 |
| ; RV64I-NEXT: addi a2, a2, 256 |
| ; RV64I-NEXT: and a0, a0, a3 |
| ; RV64I-NEXT: and a2, a4, a2 |
| ; RV64I-NEXT: sub a0, a2, a0 |
| ; RV64I-NEXT: sw a2, 0(a1) |
| ; RV64I-NEXT: ret |
| ; |
| ; RV64ZBB-LABEL: orc_b_i32_sub_shl8x_x_shl_used: |
| ; RV64ZBB: # %bb.0: # %entry |
| ; RV64ZBB-NEXT: lui a2, 4112 |
| ; RV64ZBB-NEXT: addi a3, a2, 257 |
| ; RV64ZBB-NEXT: slli a4, a0, 8 |
| ; RV64ZBB-NEXT: addi a2, a2, 256 |
| ; RV64ZBB-NEXT: and a0, a0, a3 |
| ; RV64ZBB-NEXT: and a2, a4, a2 |
| ; RV64ZBB-NEXT: sub a0, a2, a0 |
| ; RV64ZBB-NEXT: sw a2, 0(a1) |
| ; RV64ZBB-NEXT: ret |
| entry: |
| %and = and i32 %x, 16843009 |
| %shl = shl i32 %and, 8 |
| store i32 %shl, ptr %arr, align 4 |
| %sub = mul i32 %and, 255 |
| ret i32 %sub |
| } |
| |
| define i32 @orc_b_i32_sub_shl8x_x_b1_both_used(i32 %x, ptr %arr) { |
| ; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_both_used: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a2, 8224 |
| ; RV32I-NEXT: addi a2, a2, 514 |
| ; RV32I-NEXT: and a0, a0, a2 |
| ; RV32I-NEXT: slli a2, a0, 7 |
| ; RV32I-NEXT: srli a3, a0, 1 |
| ; RV32I-NEXT: sub a0, a2, a3 |
| ; RV32I-NEXT: sw a2, 0(a1) |
| ; RV32I-NEXT: sw a3, 4(a1) |
| ; RV32I-NEXT: ret |
| ; |
| ; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_both_used: |
| ; RV32ZBB: # %bb.0: # %entry |
| ; RV32ZBB-NEXT: lui a2, 8224 |
| ; RV32ZBB-NEXT: addi a2, a2, 514 |
| ; RV32ZBB-NEXT: and a0, a0, a2 |
| ; RV32ZBB-NEXT: slli a2, a0, 7 |
| ; RV32ZBB-NEXT: srli a3, a0, 1 |
| ; RV32ZBB-NEXT: sub a0, a2, a3 |
| ; RV32ZBB-NEXT: sw a2, 0(a1) |
| ; RV32ZBB-NEXT: sw a3, 4(a1) |
| ; RV32ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_shl8x_x_b1_both_used: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a2, 4112 |
| ; RV64I-NEXT: slli a3, a0, 7 |
| ; RV64I-NEXT: addi a4, a2, 256 |
| ; RV64I-NEXT: srli a0, a0, 1 |
| ; RV64I-NEXT: addi a2, a2, 257 |
| ; RV64I-NEXT: and a3, a3, a4 |
| ; RV64I-NEXT: and a2, a0, a2 |
| ; RV64I-NEXT: sub a0, a3, a2 |
| ; RV64I-NEXT: sw a3, 0(a1) |
| ; RV64I-NEXT: sw a2, 4(a1) |
| ; RV64I-NEXT: ret |
| ; |
| ; RV64ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_both_used: |
| ; RV64ZBB: # %bb.0: # %entry |
| ; RV64ZBB-NEXT: lui a2, 4112 |
| ; RV64ZBB-NEXT: slli a3, a0, 7 |
| ; RV64ZBB-NEXT: addi a4, a2, 256 |
| ; RV64ZBB-NEXT: srli a0, a0, 1 |
| ; RV64ZBB-NEXT: addi a2, a2, 257 |
| ; RV64ZBB-NEXT: and a3, a3, a4 |
| ; RV64ZBB-NEXT: and a2, a0, a2 |
| ; RV64ZBB-NEXT: sub a0, a3, a2 |
| ; RV64ZBB-NEXT: sw a3, 0(a1) |
| ; RV64ZBB-NEXT: sw a2, 4(a1) |
| ; RV64ZBB-NEXT: ret |
| entry: |
| %and = and i32 %x, 33686018 |
| %shl = shl i32 %and, 7 |
| %shr = lshr i32 %and, 1 |
| store i32 %shl, ptr %arr, align 4 |
| %arrayidx1 = getelementptr inbounds i8, ptr %arr, i32 4 |
| store i32 %shr, ptr %arrayidx1, align 4 |
| %sub = sub i32 %shl, %shr |
| ret i32 %sub |
| } |
| |
| |
| define i32 @orc_b_i32_sub_x_shr8x(i32 %x) { |
| ; RV32I-LABEL: orc_b_i32_sub_x_shr8x: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a1, 4112 |
| ; RV32I-NEXT: addi a1, a1, 257 |
| ; RV32I-NEXT: and a0, a0, a1 |
| ; RV32I-NEXT: srli a1, a0, 8 |
| ; RV32I-NEXT: sub a0, a0, a1 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV32ZBB-LABEL: orc_b_i32_sub_x_shr8x: |
| ; RV32ZBB: # %bb.0: # %entry |
| ; RV32ZBB-NEXT: lui a1, 4112 |
| ; RV32ZBB-NEXT: addi a1, a1, 257 |
| ; RV32ZBB-NEXT: and a0, a0, a1 |
| ; RV32ZBB-NEXT: srli a1, a0, 8 |
| ; RV32ZBB-NEXT: sub a0, a0, a1 |
| ; RV32ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i32_sub_x_shr8x: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a1, 4112 |
| ; RV64I-NEXT: addi a2, a1, 256 |
| ; RV64I-NEXT: addi a1, a1, 257 |
| ; RV64I-NEXT: and a2, a0, a2 |
| ; RV64I-NEXT: and a0, a0, a1 |
| ; RV64I-NEXT: srli a2, a2, 8 |
| ; RV64I-NEXT: sub a0, a0, a2 |
| ; RV64I-NEXT: ret |
| ; |
| ; RV64ZBB-LABEL: orc_b_i32_sub_x_shr8x: |
| ; RV64ZBB: # %bb.0: # %entry |
| ; RV64ZBB-NEXT: lui a1, 4112 |
| ; RV64ZBB-NEXT: addi a2, a1, 256 |
| ; RV64ZBB-NEXT: addi a1, a1, 257 |
| ; RV64ZBB-NEXT: and a2, a0, a2 |
| ; RV64ZBB-NEXT: and a0, a0, a1 |
| ; RV64ZBB-NEXT: srli a2, a2, 8 |
| ; RV64ZBB-NEXT: sub a0, a0, a2 |
| ; RV64ZBB-NEXT: ret |
| entry: |
| %and = and i32 %x, 16843009 |
| %shr = lshr i32 %and, 8 |
| %sub = sub i32 %and, %shr |
| ret i32 %sub |
| } |
| |
| define i16 @orc_b_i16_sub_shl8x_x_b1(i16 %x) { |
| ; I-LABEL: orc_b_i16_sub_shl8x_x_b1: |
| ; I: # %bb.0: # %entry |
| ; I-NEXT: andi a0, a0, 514 |
| ; I-NEXT: slli a1, a0, 7 |
| ; I-NEXT: srli a0, a0, 1 |
| ; I-NEXT: sub a0, a1, a0 |
| ; I-NEXT: ret |
| ; |
| ; ZBB-LABEL: orc_b_i16_sub_shl8x_x_b1: |
| ; ZBB: # %bb.0: # %entry |
| ; ZBB-NEXT: andi a0, a0, 514 |
| ; ZBB-NEXT: orc.b a0, a0 |
| ; ZBB-NEXT: ret |
| entry: |
| %and = and i16 %x, u0x0202 |
| %shl = shl i16 %and, 7 |
| %shr = lshr i16 %and, 1 |
| %sub = sub i16 %shl, %shr |
| ret i16 %sub |
| } |
| |
| define i64 @orc_b_i64_sub_shl8x_x_b2(i64 %x) { |
| ; RV32I-LABEL: orc_b_i64_sub_shl8x_x_b2: |
| ; RV32I: # %bb.0: # %entry |
| ; RV32I-NEXT: lui a2, 16448 |
| ; RV32I-NEXT: addi a2, a2, 1028 |
| ; RV32I-NEXT: and a1, a1, a2 |
| ; RV32I-NEXT: and a0, a0, a2 |
| ; RV32I-NEXT: srli a2, a0, 26 |
| ; RV32I-NEXT: slli a3, a1, 6 |
| ; RV32I-NEXT: slli a4, a0, 6 |
| ; RV32I-NEXT: or a2, a3, a2 |
| ; RV32I-NEXT: srli a1, a1, 2 |
| ; RV32I-NEXT: srli a0, a0, 2 |
| ; RV32I-NEXT: sltu a3, a4, a0 |
| ; RV32I-NEXT: sub a1, a2, a1 |
| ; RV32I-NEXT: sub a1, a1, a3 |
| ; RV32I-NEXT: sub a0, a4, a0 |
| ; RV32I-NEXT: ret |
| ; |
| ; RV32ZBB-LABEL: orc_b_i64_sub_shl8x_x_b2: |
| ; RV32ZBB: # %bb.0: # %entry |
| ; RV32ZBB-NEXT: lui a2, 16448 |
| ; RV32ZBB-NEXT: addi a2, a2, 1028 |
| ; RV32ZBB-NEXT: and a1, a1, a2 |
| ; RV32ZBB-NEXT: and a0, a0, a2 |
| ; RV32ZBB-NEXT: srli a2, a0, 26 |
| ; RV32ZBB-NEXT: slli a3, a1, 6 |
| ; RV32ZBB-NEXT: slli a4, a0, 6 |
| ; RV32ZBB-NEXT: or a2, a3, a2 |
| ; RV32ZBB-NEXT: srli a1, a1, 2 |
| ; RV32ZBB-NEXT: srli a0, a0, 2 |
| ; RV32ZBB-NEXT: sltu a3, a4, a0 |
| ; RV32ZBB-NEXT: sub a1, a2, a1 |
| ; RV32ZBB-NEXT: sub a1, a1, a3 |
| ; RV32ZBB-NEXT: sub a0, a4, a0 |
| ; RV32ZBB-NEXT: ret |
| ; |
| ; RV64I-LABEL: orc_b_i64_sub_shl8x_x_b2: |
| ; RV64I: # %bb.0: # %entry |
| ; RV64I-NEXT: lui a1, 16448 |
| ; RV64I-NEXT: addi a1, a1, 1028 |
| ; RV64I-NEXT: slli a2, a1, 32 |
| ; RV64I-NEXT: add a1, a1, a2 |
| ; RV64I-NEXT: and a0, a0, a1 |
| ; RV64I-NEXT: slli a1, a0, 6 |
| ; RV64I-NEXT: srli a0, a0, 2 |
| ; RV64I-NEXT: sub a0, a1, a0 |
| ; RV64I-NEXT: ret |
| ; |
| ; RV64ZBB-LABEL: orc_b_i64_sub_shl8x_x_b2: |
| ; RV64ZBB: # %bb.0: # %entry |
| ; RV64ZBB-NEXT: lui a1, 16448 |
| ; RV64ZBB-NEXT: addi a1, a1, 1028 |
| ; RV64ZBB-NEXT: slli a2, a1, 32 |
| ; RV64ZBB-NEXT: add a1, a1, a2 |
| ; RV64ZBB-NEXT: and a0, a0, a1 |
| ; RV64ZBB-NEXT: orc.b a0, a0 |
| ; RV64ZBB-NEXT: ret |
| entry: |
| %and = and i64 %x, u0x0404040404040404 |
| %shl = shl i64 %and, 6 |
| %shr = lshr exact i64 %and, 2 |
| %sub = sub nsw i64 %shl, %shr |
| ret i64 %sub |
| } |
