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llvm/llvm-project/56ee698b48ab31be816dbdfd4bea8c3761663dbe/./llvm/test/CodeGen/RISCV/bitinsert-bitextract-fp.ll
blob: 353d5d6b8c420889002680d46f539ec85760c51c [file]
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefix=RV32
; RUN: llc -mtriple=riscv32 -mattr=+zbb < %s | FileCheck %s --check-prefix=RV32ZBB
; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefix=RV64
; RUN: llc -mtriple=riscv64 -mattr=+zbb < %s | FileCheck %s --check-prefix=RV64ZBB
define half @test_bitextract_half_full(b16 %src) {
; RV32-LABEL: test_bitextract_half_full:
; RV32: # %bb.0:
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitextract_half_full:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitextract_half_full:
; RV64: # %bb.0:
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitextract_half_full:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ret
%result = bitextract half, b16 %src, i32 0
ret half %result
}
define float @test_bitextract_float_full(b32 %src) {
; RV32-LABEL: test_bitextract_float_full:
; RV32: # %bb.0:
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitextract_float_full:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitextract_float_full:
; RV64: # %bb.0:
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitextract_float_full:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ret
%result = bitextract float, b32 %src, i32 0
ret float %result
}
define float @test_bitextract_float_const(b64 %src) {
; RV32-LABEL: test_bitextract_float_const:
; RV32: # %bb.0:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitextract_float_const:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a0, a1
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitextract_float_const:
; RV64: # %bb.0:
; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitextract_float_const:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: srli a0, a0, 32
; RV64ZBB-NEXT: ret
%result = bitextract float, b64 %src, i32 32
ret float %result
}
define float @test_bitextract_float_var(b64 %src, i32 %off) {
; RV32-LABEL: test_bitextract_float_var:
; RV32: # %bb.0:
; RV32-NEXT: addi a3, a2, -32
; RV32-NEXT: bltz a3, .LBB3_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: srl a0, a1, a2
; RV32-NEXT: ret
; RV32-NEXT: .LBB3_2:
; RV32-NEXT: not a3, a2
; RV32-NEXT: slli a1, a1, 1
; RV32-NEXT: srl a0, a0, a2
; RV32-NEXT: sll a1, a1, a3
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitextract_float_var:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: addi a3, a2, -32
; RV32ZBB-NEXT: bltz a3, .LBB3_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: srl a0, a1, a2
; RV32ZBB-NEXT: ret
; RV32ZBB-NEXT: .LBB3_2:
; RV32ZBB-NEXT: not a3, a2
; RV32ZBB-NEXT: slli a1, a1, 1
; RV32ZBB-NEXT: srl a0, a0, a2
; RV32ZBB-NEXT: sll a1, a1, a3
; RV32ZBB-NEXT: or a0, a0, a1
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitextract_float_var:
; RV64: # %bb.0:
; RV64-NEXT: srl a0, a0, a1
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitextract_float_var:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: srl a0, a0, a1
; RV64ZBB-NEXT: ret
%result = bitextract float, b64 %src, i32 %off
ret float %result
}
define float @test_bitextract_float_b87_var(b87 %src, i32 %off) {
; RV32-LABEL: test_bitextract_float_b87_var:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -32
; RV32-NEXT: .cfi_def_cfa_offset 32
; RV32-NEXT: lw a2, 0(a0)
; RV32-NEXT: lw a3, 4(a0)
; RV32-NEXT: lw a0, 8(a0)
; RV32-NEXT: srli a4, a1, 3
; RV32-NEXT: sw zero, 16(sp)
; RV32-NEXT: sw zero, 20(sp)
; RV32-NEXT: sw zero, 24(sp)
; RV32-NEXT: sw zero, 28(sp)
; RV32-NEXT: andi a4, a4, 12
; RV32-NEXT: slli a0, a0, 9
; RV32-NEXT: mv a5, sp
; RV32-NEXT: srli a0, a0, 9
; RV32-NEXT: sw a2, 0(sp)
; RV32-NEXT: sw a3, 4(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: lw a0, 4(a4)
; RV32-NEXT: lw a2, 0(a4)
; RV32-NEXT: andi a3, a1, 31
; RV32-NEXT: slli a0, a0, 1
; RV32-NEXT: xori a3, a3, 31
; RV32-NEXT: srl a1, a2, a1
; RV32-NEXT: sll a0, a0, a3
; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitextract_float_b87_var:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: addi sp, sp, -32
; RV32ZBB-NEXT: .cfi_def_cfa_offset 32
; RV32ZBB-NEXT: lw a2, 0(a0)
; RV32ZBB-NEXT: lw a3, 4(a0)
; RV32ZBB-NEXT: lw a0, 8(a0)
; RV32ZBB-NEXT: srli a4, a1, 3
; RV32ZBB-NEXT: sw zero, 16(sp)
; RV32ZBB-NEXT: sw zero, 20(sp)
; RV32ZBB-NEXT: sw zero, 24(sp)
; RV32ZBB-NEXT: sw zero, 28(sp)
; RV32ZBB-NEXT: andi a4, a4, 12
; RV32ZBB-NEXT: slli a0, a0, 9
; RV32ZBB-NEXT: mv a5, sp
; RV32ZBB-NEXT: srli a0, a0, 9
; RV32ZBB-NEXT: sw a2, 0(sp)
; RV32ZBB-NEXT: sw a3, 4(sp)
; RV32ZBB-NEXT: sw a0, 8(sp)
; RV32ZBB-NEXT: sw zero, 12(sp)
; RV32ZBB-NEXT: add a4, a5, a4
; RV32ZBB-NEXT: lw a0, 4(a4)
; RV32ZBB-NEXT: lw a2, 0(a4)
; RV32ZBB-NEXT: andi a3, a1, 31
; RV32ZBB-NEXT: slli a0, a0, 1
; RV32ZBB-NEXT: xori a3, a3, 31
; RV32ZBB-NEXT: srl a1, a2, a1
; RV32ZBB-NEXT: sll a0, a0, a3
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: addi sp, sp, 32
; RV32ZBB-NEXT: .cfi_def_cfa_offset 0
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitextract_float_b87_var:
; RV64: # %bb.0:
; RV64-NEXT: slli a3, a2, 32
; RV64-NEXT: srli a3, a3, 32
; RV64-NEXT: slli a1, a1, 41
; RV64-NEXT: addi a4, a3, -64
; RV64-NEXT: srli a1, a1, 41
; RV64-NEXT: bltz a4, .LBB4_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: srl a0, a1, a3
; RV64-NEXT: ret
; RV64-NEXT: .LBB4_2:
; RV64-NEXT: not a3, a3
; RV64-NEXT: slli a1, a1, 1
; RV64-NEXT: srl a0, a0, a2
; RV64-NEXT: sll a1, a1, a3
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitextract_float_b87_var:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: slli a3, a2, 32
; RV64ZBB-NEXT: srli a3, a3, 32
; RV64ZBB-NEXT: slli a1, a1, 41
; RV64ZBB-NEXT: addi a4, a3, -64
; RV64ZBB-NEXT: srli a1, a1, 41
; RV64ZBB-NEXT: bltz a4, .LBB4_2
; RV64ZBB-NEXT: # %bb.1:
; RV64ZBB-NEXT: srl a0, a1, a3
; RV64ZBB-NEXT: ret
; RV64ZBB-NEXT: .LBB4_2:
; RV64ZBB-NEXT: not a3, a3
; RV64ZBB-NEXT: slli a1, a1, 1
; RV64ZBB-NEXT: srl a0, a0, a2
; RV64ZBB-NEXT: sll a1, a1, a3
; RV64ZBB-NEXT: or a0, a0, a1
; RV64ZBB-NEXT: ret
%result = bitextract float, b87 %src, i32 %off
ret float %result
}
define float @test_bitextract_float_b87_crossword(b87 %src) {
; RV32-LABEL: test_bitextract_float_b87_crossword:
; RV32: # %bb.0:
; RV32-NEXT: lw a1, 4(a0)
; RV32-NEXT: lw a0, 8(a0)
; RV32-NEXT: slli a0, a0, 9
; RV32-NEXT: srli a1, a1, 23
; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitextract_float_b87_crossword:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: lw a1, 4(a0)
; RV32ZBB-NEXT: lw a0, 8(a0)
; RV32ZBB-NEXT: slli a0, a0, 9
; RV32ZBB-NEXT: srli a1, a1, 23
; RV32ZBB-NEXT: or a0, a1, a0
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitextract_float_b87_crossword:
; RV64: # %bb.0:
; RV64-NEXT: slli a1, a1, 41
; RV64-NEXT: srli a0, a0, 55
; RV64-NEXT: srli a1, a1, 32
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitextract_float_b87_crossword:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: slli a1, a1, 41
; RV64ZBB-NEXT: srli a0, a0, 55
; RV64ZBB-NEXT: srli a1, a1, 32
; RV64ZBB-NEXT: or a0, a0, a1
; RV64ZBB-NEXT: ret
%result = bitextract float, b87 %src, i32 55
ret float %result
}
define double @test_bitextract_double_full(b64 %src) {
; RV32-LABEL: test_bitextract_double_full:
; RV32: # %bb.0:
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitextract_double_full:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitextract_double_full:
; RV64: # %bb.0:
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitextract_double_full:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: ret
%result = bitextract double, b64 %src, i32 0
ret double %result
}
define double @test_bitextract_double_const(b128 %src) {
; RV32-LABEL: test_bitextract_double_const:
; RV32: # %bb.0:
; RV32-NEXT: lw a2, 8(a0)
; RV32-NEXT: lw a1, 12(a0)
; RV32-NEXT: mv a0, a2
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitextract_double_const:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: lw a2, 8(a0)
; RV32ZBB-NEXT: lw a1, 12(a0)
; RV32ZBB-NEXT: mv a0, a2
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitextract_double_const:
; RV64: # %bb.0:
; RV64-NEXT: mv a0, a1
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitextract_double_const:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a0, a1
; RV64ZBB-NEXT: ret
%result = bitextract double, b128 %src, i32 64
ret double %result
}
define double @test_bitextract_double_var(b128 %src, i32 %off) {
; RV32-LABEL: test_bitextract_double_var:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -32
; RV32-NEXT: .cfi_def_cfa_offset 32
; RV32-NEXT: lw a2, 0(a0)
; RV32-NEXT: lw a3, 4(a0)
; RV32-NEXT: lw a4, 8(a0)
; RV32-NEXT: lw a0, 12(a0)
; RV32-NEXT: srli a5, a1, 3
; RV32-NEXT: sw zero, 16(sp)
; RV32-NEXT: sw zero, 20(sp)
; RV32-NEXT: sw zero, 24(sp)
; RV32-NEXT: sw zero, 28(sp)
; RV32-NEXT: andi a5, a5, 12
; RV32-NEXT: mv a6, sp
; RV32-NEXT: sw a2, 0(sp)
; RV32-NEXT: sw a3, 4(sp)
; RV32-NEXT: sw a4, 8(sp)
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: add a5, a6, a5
; RV32-NEXT: lw a0, 0(a5)
; RV32-NEXT: lw a2, 4(a5)
; RV32-NEXT: lw a3, 8(a5)
; RV32-NEXT: srl a0, a0, a1
; RV32-NEXT: andi a4, a1, 31
; RV32-NEXT: slli a5, a2, 1
; RV32-NEXT: xori a4, a4, 31
; RV32-NEXT: sll a5, a5, a4
; RV32-NEXT: slli a3, a3, 1
; RV32-NEXT: srl a1, a2, a1
; RV32-NEXT: sll a2, a3, a4
; RV32-NEXT: or a0, a0, a5
; RV32-NEXT: or a1, a1, a2
; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitextract_double_var:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: addi sp, sp, -32
; RV32ZBB-NEXT: .cfi_def_cfa_offset 32
; RV32ZBB-NEXT: lw a2, 0(a0)
; RV32ZBB-NEXT: lw a3, 4(a0)
; RV32ZBB-NEXT: lw a4, 8(a0)
; RV32ZBB-NEXT: lw a0, 12(a0)
; RV32ZBB-NEXT: srli a5, a1, 3
; RV32ZBB-NEXT: sw zero, 16(sp)
; RV32ZBB-NEXT: sw zero, 20(sp)
; RV32ZBB-NEXT: sw zero, 24(sp)
; RV32ZBB-NEXT: sw zero, 28(sp)
; RV32ZBB-NEXT: andi a5, a5, 12
; RV32ZBB-NEXT: mv a6, sp
; RV32ZBB-NEXT: sw a2, 0(sp)
; RV32ZBB-NEXT: sw a3, 4(sp)
; RV32ZBB-NEXT: sw a4, 8(sp)
; RV32ZBB-NEXT: sw a0, 12(sp)
; RV32ZBB-NEXT: add a5, a6, a5
; RV32ZBB-NEXT: lw a0, 0(a5)
; RV32ZBB-NEXT: lw a2, 4(a5)
; RV32ZBB-NEXT: lw a3, 8(a5)
; RV32ZBB-NEXT: srl a0, a0, a1
; RV32ZBB-NEXT: andi a4, a1, 31
; RV32ZBB-NEXT: slli a5, a2, 1
; RV32ZBB-NEXT: xori a4, a4, 31
; RV32ZBB-NEXT: sll a5, a5, a4
; RV32ZBB-NEXT: slli a3, a3, 1
; RV32ZBB-NEXT: srl a1, a2, a1
; RV32ZBB-NEXT: sll a2, a3, a4
; RV32ZBB-NEXT: or a0, a0, a5
; RV32ZBB-NEXT: or a1, a1, a2
; RV32ZBB-NEXT: addi sp, sp, 32
; RV32ZBB-NEXT: .cfi_def_cfa_offset 0
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitextract_double_var:
; RV64: # %bb.0:
; RV64-NEXT: slli a3, a2, 32
; RV64-NEXT: srli a3, a3, 32
; RV64-NEXT: addi a4, a3, -64
; RV64-NEXT: bltz a4, .LBB8_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: srl a0, a1, a3
; RV64-NEXT: ret
; RV64-NEXT: .LBB8_2:
; RV64-NEXT: slli a1, a1, 1
; RV64-NEXT: not a3, a3
; RV64-NEXT: srl a0, a0, a2
; RV64-NEXT: sll a1, a1, a3
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitextract_double_var:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: slli a3, a2, 32
; RV64ZBB-NEXT: srli a3, a3, 32
; RV64ZBB-NEXT: addi a4, a3, -64
; RV64ZBB-NEXT: bltz a4, .LBB8_2
; RV64ZBB-NEXT: # %bb.1:
; RV64ZBB-NEXT: srl a0, a1, a3
; RV64ZBB-NEXT: ret
; RV64ZBB-NEXT: .LBB8_2:
; RV64ZBB-NEXT: slli a1, a1, 1
; RV64ZBB-NEXT: not a3, a3
; RV64ZBB-NEXT: srl a0, a0, a2
; RV64ZBB-NEXT: sll a1, a1, a3
; RV64ZBB-NEXT: or a0, a0, a1
; RV64ZBB-NEXT: ret
%result = bitextract double, b128 %src, i32 %off
ret double %result
}
define double @test_bitextract_double_b231_var(b231 %src, i32 %off) {
; RV32-LABEL: test_bitextract_double_b231_var:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -64
; RV32-NEXT: .cfi_def_cfa_offset 64
; RV32-NEXT: lw a2, 28(a0)
; RV32-NEXT: lw a3, 16(a0)
; RV32-NEXT: lw a4, 20(a0)
; RV32-NEXT: lw a5, 24(a0)
; RV32-NEXT: lw a6, 0(a0)
; RV32-NEXT: lw a7, 4(a0)
; RV32-NEXT: lw t0, 8(a0)
; RV32-NEXT: lw a0, 12(a0)
; RV32-NEXT: andi a2, a2, 127
; RV32-NEXT: sw zero, 48(sp)
; RV32-NEXT: sw zero, 52(sp)
; RV32-NEXT: sw zero, 56(sp)
; RV32-NEXT: sw zero, 60(sp)
; RV32-NEXT: sw zero, 32(sp)
; RV32-NEXT: sw zero, 36(sp)
; RV32-NEXT: sw zero, 40(sp)
; RV32-NEXT: sw zero, 44(sp)
; RV32-NEXT: srli t1, a1, 3
; RV32-NEXT: sw a6, 0(sp)
; RV32-NEXT: sw a7, 4(sp)
; RV32-NEXT: sw t0, 8(sp)
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: andi a0, t1, 28
; RV32-NEXT: mv a6, sp
; RV32-NEXT: sw a3, 16(sp)
; RV32-NEXT: sw a4, 20(sp)
; RV32-NEXT: sw a5, 24(sp)
; RV32-NEXT: sw a2, 28(sp)
; RV32-NEXT: add a0, a6, a0
; RV32-NEXT: lw a2, 0(a0)
; RV32-NEXT: lw a3, 4(a0)
; RV32-NEXT: lw a0, 8(a0)
; RV32-NEXT: srl a2, a2, a1
; RV32-NEXT: andi a4, a1, 31
; RV32-NEXT: slli a5, a3, 1
; RV32-NEXT: xori a4, a4, 31
; RV32-NEXT: sll a5, a5, a4
; RV32-NEXT: slli a0, a0, 1
; RV32-NEXT: srl a1, a3, a1
; RV32-NEXT: sll a3, a0, a4
; RV32-NEXT: or a0, a2, a5
; RV32-NEXT: or a1, a1, a3
; RV32-NEXT: addi sp, sp, 64
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitextract_double_b231_var:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: addi sp, sp, -64
; RV32ZBB-NEXT: .cfi_def_cfa_offset 64
; RV32ZBB-NEXT: lw a2, 28(a0)
; RV32ZBB-NEXT: lw a3, 16(a0)
; RV32ZBB-NEXT: lw a4, 20(a0)
; RV32ZBB-NEXT: lw a5, 24(a0)
; RV32ZBB-NEXT: lw a6, 0(a0)
; RV32ZBB-NEXT: lw a7, 4(a0)
; RV32ZBB-NEXT: lw t0, 8(a0)
; RV32ZBB-NEXT: lw a0, 12(a0)
; RV32ZBB-NEXT: andi a2, a2, 127
; RV32ZBB-NEXT: sw zero, 48(sp)
; RV32ZBB-NEXT: sw zero, 52(sp)
; RV32ZBB-NEXT: sw zero, 56(sp)
; RV32ZBB-NEXT: sw zero, 60(sp)
; RV32ZBB-NEXT: sw zero, 32(sp)
; RV32ZBB-NEXT: sw zero, 36(sp)
; RV32ZBB-NEXT: sw zero, 40(sp)
; RV32ZBB-NEXT: sw zero, 44(sp)
; RV32ZBB-NEXT: srli t1, a1, 3
; RV32ZBB-NEXT: sw a6, 0(sp)
; RV32ZBB-NEXT: sw a7, 4(sp)
; RV32ZBB-NEXT: sw t0, 8(sp)
; RV32ZBB-NEXT: sw a0, 12(sp)
; RV32ZBB-NEXT: andi a0, t1, 28
; RV32ZBB-NEXT: mv a6, sp
; RV32ZBB-NEXT: sw a3, 16(sp)
; RV32ZBB-NEXT: sw a4, 20(sp)
; RV32ZBB-NEXT: sw a5, 24(sp)
; RV32ZBB-NEXT: sw a2, 28(sp)
; RV32ZBB-NEXT: add a0, a6, a0
; RV32ZBB-NEXT: lw a2, 0(a0)
; RV32ZBB-NEXT: lw a3, 4(a0)
; RV32ZBB-NEXT: lw a0, 8(a0)
; RV32ZBB-NEXT: srl a2, a2, a1
; RV32ZBB-NEXT: andi a4, a1, 31
; RV32ZBB-NEXT: slli a5, a3, 1
; RV32ZBB-NEXT: xori a4, a4, 31
; RV32ZBB-NEXT: sll a5, a5, a4
; RV32ZBB-NEXT: slli a0, a0, 1
; RV32ZBB-NEXT: srl a1, a3, a1
; RV32ZBB-NEXT: sll a3, a0, a4
; RV32ZBB-NEXT: or a0, a2, a5
; RV32ZBB-NEXT: or a1, a1, a3
; RV32ZBB-NEXT: addi sp, sp, 64
; RV32ZBB-NEXT: .cfi_def_cfa_offset 0
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitextract_double_b231_var:
; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -64
; RV64-NEXT: .cfi_def_cfa_offset 64
; RV64-NEXT: ld a2, 24(a0)
; RV64-NEXT: ld a3, 0(a0)
; RV64-NEXT: ld a4, 8(a0)
; RV64-NEXT: ld a0, 16(a0)
; RV64-NEXT: sd zero, 32(sp)
; RV64-NEXT: sd zero, 40(sp)
; RV64-NEXT: sd zero, 48(sp)
; RV64-NEXT: sd zero, 56(sp)
; RV64-NEXT: srli a5, a1, 3
; RV64-NEXT: slli a2, a2, 25
; RV64-NEXT: andi a5, a5, 24
; RV64-NEXT: srli a2, a2, 25
; RV64-NEXT: mv a6, sp
; RV64-NEXT: sd a3, 0(sp)
; RV64-NEXT: sd a4, 8(sp)
; RV64-NEXT: sd a0, 16(sp)
; RV64-NEXT: sd a2, 24(sp)
; RV64-NEXT: add a5, a6, a5
; RV64-NEXT: ld a0, 8(a5)
; RV64-NEXT: ld a2, 0(a5)
; RV64-NEXT: andi a3, a1, 63
; RV64-NEXT: slli a0, a0, 1
; RV64-NEXT: xori a3, a3, 63
; RV64-NEXT: srl a1, a2, a1
; RV64-NEXT: sll a0, a0, a3
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: addi sp, sp, 64
; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitextract_double_b231_var:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addi sp, sp, -64
; RV64ZBB-NEXT: .cfi_def_cfa_offset 64
; RV64ZBB-NEXT: ld a2, 24(a0)
; RV64ZBB-NEXT: ld a3, 0(a0)
; RV64ZBB-NEXT: ld a4, 8(a0)
; RV64ZBB-NEXT: ld a0, 16(a0)
; RV64ZBB-NEXT: sd zero, 32(sp)
; RV64ZBB-NEXT: sd zero, 40(sp)
; RV64ZBB-NEXT: sd zero, 48(sp)
; RV64ZBB-NEXT: sd zero, 56(sp)
; RV64ZBB-NEXT: srli a5, a1, 3
; RV64ZBB-NEXT: slli a2, a2, 25
; RV64ZBB-NEXT: andi a5, a5, 24
; RV64ZBB-NEXT: srli a2, a2, 25
; RV64ZBB-NEXT: mv a6, sp
; RV64ZBB-NEXT: sd a3, 0(sp)
; RV64ZBB-NEXT: sd a4, 8(sp)
; RV64ZBB-NEXT: sd a0, 16(sp)
; RV64ZBB-NEXT: sd a2, 24(sp)
; RV64ZBB-NEXT: add a5, a6, a5
; RV64ZBB-NEXT: ld a0, 8(a5)
; RV64ZBB-NEXT: ld a2, 0(a5)
; RV64ZBB-NEXT: andi a3, a1, 63
; RV64ZBB-NEXT: slli a0, a0, 1
; RV64ZBB-NEXT: xori a3, a3, 63
; RV64ZBB-NEXT: srl a1, a2, a1
; RV64ZBB-NEXT: sll a0, a0, a3
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: addi sp, sp, 64
; RV64ZBB-NEXT: .cfi_def_cfa_offset 0
; RV64ZBB-NEXT: ret
%result = bitextract double, b231 %src, i32 %off
ret double %result
}
define b16 @test_bitinsert_half_full(b16 %base, half %val) {
; RV32-LABEL: test_bitinsert_half_full:
; RV32: # %bb.0:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitinsert_half_full:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a0, a1
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitinsert_half_full:
; RV64: # %bb.0:
; RV64-NEXT: mv a0, a1
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitinsert_half_full:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a0, a1
; RV64ZBB-NEXT: ret
%result = bitinsert b16 %base, half %val, i32 0
ret b16 %result
}
define b32 @test_bitinsert_half_var(b32 %base, half %val, i32 %off) {
; RV32-LABEL: test_bitinsert_half_var:
; RV32: # %bb.0:
; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -1
; RV32-NEXT: sll a4, a3, a2
; RV32-NEXT: and a1, a1, a3
; RV32-NEXT: not a3, a4
; RV32-NEXT: sll a1, a1, a2
; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitinsert_half_var:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: lui a3, 16
; RV32ZBB-NEXT: addi a3, a3, -1
; RV32ZBB-NEXT: zext.h a1, a1
; RV32ZBB-NEXT: sll a3, a3, a2
; RV32ZBB-NEXT: sll a1, a1, a2
; RV32ZBB-NEXT: andn a0, a0, a3
; RV32ZBB-NEXT: or a0, a0, a1
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitinsert_half_var:
; RV64: # %bb.0:
; RV64-NEXT: lui a3, 16
; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: sllw a4, a3, a2
; RV64-NEXT: and a1, a1, a3
; RV64-NEXT: not a3, a4
; RV64-NEXT: sllw a1, a1, a2
; RV64-NEXT: and a0, a0, a3
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitinsert_half_var:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: lui a3, 16
; RV64ZBB-NEXT: addi a3, a3, -1
; RV64ZBB-NEXT: zext.h a1, a1
; RV64ZBB-NEXT: sllw a3, a3, a2
; RV64ZBB-NEXT: sllw a1, a1, a2
; RV64ZBB-NEXT: andn a0, a0, a3
; RV64ZBB-NEXT: or a0, a0, a1
; RV64ZBB-NEXT: ret
%result = bitinsert b32 %base, half %val, i32 %off
ret b32 %result
}
define b32 @test_bitinsert_float_full(b32 %base, float %val) {
; RV32-LABEL: test_bitinsert_float_full:
; RV32: # %bb.0:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitinsert_float_full:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a0, a1
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitinsert_float_full:
; RV64: # %bb.0:
; RV64-NEXT: mv a0, a1
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitinsert_float_full:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a0, a1
; RV64ZBB-NEXT: ret
%result = bitinsert b32 %base, float %val, i32 0
ret b32 %result
}
define b64 @test_bitinsert_float_const(b64 %base, float %val) {
; RV32-LABEL: test_bitinsert_float_const:
; RV32: # %bb.0:
; RV32-NEXT: mv a1, a2
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitinsert_float_const:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a1, a2
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitinsert_float_const:
; RV64: # %bb.0:
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: slli a1, a1, 32
; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitinsert_float_const:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: slli a0, a0, 32
; RV64ZBB-NEXT: slli a1, a1, 32
; RV64ZBB-NEXT: srli a0, a0, 32
; RV64ZBB-NEXT: or a0, a0, a1
; RV64ZBB-NEXT: ret
%result = bitinsert b64 %base, float %val, i32 32
ret b64 %result
}
define b64 @test_bitinsert_float_var(b64 %base, float %val, i32 %off) {
; RV32-LABEL: test_bitinsert_float_var:
; RV32: # %bb.0:
; RV32-NEXT: addi a5, a3, -32
; RV32-NEXT: li a6, -1
; RV32-NEXT: sll a4, a2, a3
; RV32-NEXT: sll a6, a6, a3
; RV32-NEXT: bltz a5, .LBB14_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a2, a4
; RV32-NEXT: mv a3, a6
; RV32-NEXT: j .LBB14_3
; RV32-NEXT: .LBB14_2:
; RV32-NEXT: not a3, a3
; RV32-NEXT: lui a7, 524288
; RV32-NEXT: srli a2, a2, 1
; RV32-NEXT: addi a7, a7, -1
; RV32-NEXT: srl a2, a2, a3
; RV32-NEXT: srl a3, a7, a3
; RV32-NEXT: .LBB14_3:
; RV32-NEXT: srai a5, a5, 31
; RV32-NEXT: not a3, a3
; RV32-NEXT: and a6, a5, a6
; RV32-NEXT: and a1, a1, a3
; RV32-NEXT: not a3, a6
; RV32-NEXT: and a4, a5, a4
; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: or a1, a1, a2
; RV32-NEXT: or a0, a0, a4
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitinsert_float_var:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: addi a5, a3, -32
; RV32ZBB-NEXT: li a6, -1
; RV32ZBB-NEXT: sll a4, a2, a3
; RV32ZBB-NEXT: sll a6, a6, a3
; RV32ZBB-NEXT: bltz a5, .LBB14_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: mv a2, a4
; RV32ZBB-NEXT: mv a3, a6
; RV32ZBB-NEXT: j .LBB14_3
; RV32ZBB-NEXT: .LBB14_2:
; RV32ZBB-NEXT: not a3, a3
; RV32ZBB-NEXT: lui a7, 524288
; RV32ZBB-NEXT: srli a2, a2, 1
; RV32ZBB-NEXT: addi a7, a7, -1
; RV32ZBB-NEXT: srl a2, a2, a3
; RV32ZBB-NEXT: srl a3, a7, a3
; RV32ZBB-NEXT: .LBB14_3:
; RV32ZBB-NEXT: srai a5, a5, 31
; RV32ZBB-NEXT: andn a1, a1, a3
; RV32ZBB-NEXT: and a3, a5, a6
; RV32ZBB-NEXT: and a4, a5, a4
; RV32ZBB-NEXT: andn a0, a0, a3
; RV32ZBB-NEXT: or a1, a1, a2
; RV32ZBB-NEXT: or a0, a0, a4
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitinsert_float_var:
; RV64: # %bb.0:
; RV64-NEXT: li a3, -1
; RV64-NEXT: srli a3, a3, 32
; RV64-NEXT: slli a1, a1, 32
; RV64-NEXT: sll a3, a3, a2
; RV64-NEXT: srli a1, a1, 32
; RV64-NEXT: not a3, a3
; RV64-NEXT: sll a1, a1, a2
; RV64-NEXT: and a0, a0, a3
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitinsert_float_var:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: li a3, -1
; RV64ZBB-NEXT: slli a1, a1, 32
; RV64ZBB-NEXT: srli a3, a3, 32
; RV64ZBB-NEXT: srli a1, a1, 32
; RV64ZBB-NEXT: sll a3, a3, a2
; RV64ZBB-NEXT: sll a1, a1, a2
; RV64ZBB-NEXT: andn a0, a0, a3
; RV64ZBB-NEXT: or a0, a0, a1
; RV64ZBB-NEXT: ret
%result = bitinsert b64 %base, float %val, i32 %off
ret b64 %result
}
define b87 @test_bitinsert_float_b87_var(b87 %base, float %val, i32 %off) {
; RV32-LABEL: test_bitinsert_float_b87_var:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -64
; RV32-NEXT: .cfi_def_cfa_offset 64
; RV32-NEXT: lw a4, 0(a1)
; RV32-NEXT: lw a5, 4(a1)
; RV32-NEXT: lw a1, 8(a1)
; RV32-NEXT: sw a2, 16(sp)
; RV32-NEXT: sw zero, 20(sp)
; RV32-NEXT: sw zero, 24(sp)
; RV32-NEXT: sw zero, 28(sp)
; RV32-NEXT: li a2, -1
; RV32-NEXT: sw zero, 0(sp)
; RV32-NEXT: sw zero, 4(sp)
; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: sw a2, 48(sp)
; RV32-NEXT: sw zero, 52(sp)
; RV32-NEXT: sw zero, 56(sp)
; RV32-NEXT: sw zero, 60(sp)
; RV32-NEXT: sw zero, 32(sp)
; RV32-NEXT: sw zero, 36(sp)
; RV32-NEXT: sw zero, 40(sp)
; RV32-NEXT: sw zero, 44(sp)
; RV32-NEXT: srli a2, a3, 3
; RV32-NEXT: andi a2, a2, 12
; RV32-NEXT: addi a6, sp, 16
; RV32-NEXT: sub a6, a6, a2
; RV32-NEXT: addi a7, sp, 48
; RV32-NEXT: lw t0, 4(a6)
; RV32-NEXT: sub a2, a7, a2
; RV32-NEXT: lw a7, 0(a2)
; RV32-NEXT: andi t1, a3, 31
; RV32-NEXT: lw t2, 4(a2)
; RV32-NEXT: lw t3, 0(a6)
; RV32-NEXT: lw a6, 8(a6)
; RV32-NEXT: sll t4, t0, a3
; RV32-NEXT: xori t1, t1, 31
; RV32-NEXT: lw a2, 8(a2)
; RV32-NEXT: srli t5, a7, 1
; RV32-NEXT: sll t6, t2, a3
; RV32-NEXT: srl t5, t5, t1
; RV32-NEXT: or t5, t6, t5
; RV32-NEXT: srli t6, t3, 1
; RV32-NEXT: srl t6, t6, t1
; RV32-NEXT: not t5, t5
; RV32-NEXT: or t4, t4, t6
; RV32-NEXT: and a5, a5, t5
; RV32-NEXT: or a5, a5, t4
; RV32-NEXT: sll a6, a6, a3
; RV32-NEXT: srli t2, t2, 1
; RV32-NEXT: sll a2, a2, a3
; RV32-NEXT: srl t2, t2, t1
; RV32-NEXT: srli t0, t0, 1
; RV32-NEXT: or a2, a2, t2
; RV32-NEXT: srl t0, t0, t1
; RV32-NEXT: not a2, a2
; RV32-NEXT: or a6, a6, t0
; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: or a1, a1, a6
; RV32-NEXT: sll a2, a7, a3
; RV32-NEXT: sll a3, t3, a3
; RV32-NEXT: not a2, a2
; RV32-NEXT: and a2, a4, a2
; RV32-NEXT: slli a4, a1, 9
; RV32-NEXT: or a2, a2, a3
; RV32-NEXT: srli a4, a4, 25
; RV32-NEXT: sw a2, 0(a0)
; RV32-NEXT: sw a5, 4(a0)
; RV32-NEXT: sh a1, 8(a0)
; RV32-NEXT: sb a4, 10(a0)
; RV32-NEXT: addi sp, sp, 64
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitinsert_float_b87_var:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: addi sp, sp, -80
; RV32ZBB-NEXT: .cfi_def_cfa_offset 80
; RV32ZBB-NEXT: sw s0, 76(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: .cfi_offset s0, -4
; RV32ZBB-NEXT: lw a4, 0(a1)
; RV32ZBB-NEXT: lw a5, 4(a1)
; RV32ZBB-NEXT: lw a1, 8(a1)
; RV32ZBB-NEXT: sw a2, 24(sp)
; RV32ZBB-NEXT: sw zero, 28(sp)
; RV32ZBB-NEXT: sw zero, 32(sp)
; RV32ZBB-NEXT: sw zero, 36(sp)
; RV32ZBB-NEXT: sw zero, 8(sp)
; RV32ZBB-NEXT: sw zero, 12(sp)
; RV32ZBB-NEXT: sw zero, 16(sp)
; RV32ZBB-NEXT: sw zero, 20(sp)
; RV32ZBB-NEXT: li a2, -1
; RV32ZBB-NEXT: srli a6, a3, 3
; RV32ZBB-NEXT: sw a2, 56(sp)
; RV32ZBB-NEXT: sw zero, 60(sp)
; RV32ZBB-NEXT: sw zero, 64(sp)
; RV32ZBB-NEXT: sw zero, 68(sp)
; RV32ZBB-NEXT: andi a2, a6, 12
; RV32ZBB-NEXT: addi a6, sp, 24
; RV32ZBB-NEXT: sw zero, 40(sp)
; RV32ZBB-NEXT: sw zero, 44(sp)
; RV32ZBB-NEXT: sw zero, 48(sp)
; RV32ZBB-NEXT: sw zero, 52(sp)
; RV32ZBB-NEXT: sub a6, a6, a2
; RV32ZBB-NEXT: addi a7, sp, 56
; RV32ZBB-NEXT: lw t0, 0(a6)
; RV32ZBB-NEXT: lw t1, 4(a6)
; RV32ZBB-NEXT: sub a2, a7, a2
; RV32ZBB-NEXT: andi a7, a3, 31
; RV32ZBB-NEXT: lw t2, 0(a2)
; RV32ZBB-NEXT: lw t3, 4(a2)
; RV32ZBB-NEXT: lw a6, 8(a6)
; RV32ZBB-NEXT: srli t4, t0, 1
; RV32ZBB-NEXT: xori a7, a7, 31
; RV32ZBB-NEXT: sll t5, t1, a3
; RV32ZBB-NEXT: srl t4, t4, a7
; RV32ZBB-NEXT: lw a2, 8(a2)
; RV32ZBB-NEXT: srli t6, t2, 1
; RV32ZBB-NEXT: sll s0, t3, a3
; RV32ZBB-NEXT: srl t6, t6, a7
; RV32ZBB-NEXT: or t4, t5, t4
; RV32ZBB-NEXT: or t5, s0, t6
; RV32ZBB-NEXT: andn a5, a5, t5
; RV32ZBB-NEXT: sll a6, a6, a3
; RV32ZBB-NEXT: srli t1, t1, 1
; RV32ZBB-NEXT: srli t3, t3, 1
; RV32ZBB-NEXT: sll a2, a2, a3
; RV32ZBB-NEXT: srl t3, t3, a7
; RV32ZBB-NEXT: srl a7, t1, a7
; RV32ZBB-NEXT: or a2, a2, t3
; RV32ZBB-NEXT: or a6, a6, a7
; RV32ZBB-NEXT: andn a1, a1, a2
; RV32ZBB-NEXT: or a2, a5, t4
; RV32ZBB-NEXT: or a1, a1, a6
; RV32ZBB-NEXT: sll a5, t0, a3
; RV32ZBB-NEXT: sll a3, t2, a3
; RV32ZBB-NEXT: andn a3, a4, a3
; RV32ZBB-NEXT: slli a4, a1, 9
; RV32ZBB-NEXT: or a3, a3, a5
; RV32ZBB-NEXT: srli a4, a4, 25
; RV32ZBB-NEXT: sw a3, 0(a0)
; RV32ZBB-NEXT: sw a2, 4(a0)
; RV32ZBB-NEXT: sh a1, 8(a0)
; RV32ZBB-NEXT: sb a4, 10(a0)
; RV32ZBB-NEXT: lw s0, 76(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: .cfi_restore s0
; RV32ZBB-NEXT: addi sp, sp, 80
; RV32ZBB-NEXT: .cfi_def_cfa_offset 0
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitinsert_float_b87_var:
; RV64: # %bb.0:
; RV64-NEXT: slli a4, a3, 32
; RV64-NEXT: srli a7, a4, 32
; RV64-NEXT: slli a5, a2, 32
; RV64-NEXT: addi a4, a7, -64
; RV64-NEXT: li t0, -1
; RV64-NEXT: srli a6, a5, 32
; RV64-NEXT: srli a5, t0, 32
; RV64-NEXT: bltz a4, .LBB15_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: sll a2, a6, a7
; RV64-NEXT: sll a7, a5, a7
; RV64-NEXT: j .LBB15_3
; RV64-NEXT: .LBB15_2:
; RV64-NEXT: srliw a2, a2, 1
; RV64-NEXT: lui t0, 524288
; RV64-NEXT: not a7, a7
; RV64-NEXT: addiw t0, t0, -1
; RV64-NEXT: srl a2, a2, a7
; RV64-NEXT: srl a7, t0, a7
; RV64-NEXT: .LBB15_3:
; RV64-NEXT: lui t0, 2048
; RV64-NEXT: sll a6, a6, a3
; RV64-NEXT: srai a4, a4, 63
; RV64-NEXT: addi t0, t0, -1
; RV64-NEXT: sll a3, a5, a3
; RV64-NEXT: xor a5, a7, t0
; RV64-NEXT: and a3, a4, a3
; RV64-NEXT: and a1, a1, a5
; RV64-NEXT: not a3, a3
; RV64-NEXT: and a4, a4, a6
; RV64-NEXT: and a0, a0, a3
; RV64-NEXT: or a1, a1, a2
; RV64-NEXT: or a0, a0, a4
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitinsert_float_b87_var:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: slli a4, a3, 32
; RV64ZBB-NEXT: srli a7, a4, 32
; RV64ZBB-NEXT: slli a5, a2, 32
; RV64ZBB-NEXT: addi a4, a7, -64
; RV64ZBB-NEXT: li t0, -1
; RV64ZBB-NEXT: srli a6, a5, 32
; RV64ZBB-NEXT: srli a5, t0, 32
; RV64ZBB-NEXT: bltz a4, .LBB15_2
; RV64ZBB-NEXT: # %bb.1:
; RV64ZBB-NEXT: sll a2, a6, a7
; RV64ZBB-NEXT: sll a7, a5, a7
; RV64ZBB-NEXT: j .LBB15_3
; RV64ZBB-NEXT: .LBB15_2:
; RV64ZBB-NEXT: srliw a2, a2, 1
; RV64ZBB-NEXT: lui t0, 524288
; RV64ZBB-NEXT: not a7, a7
; RV64ZBB-NEXT: addiw t0, t0, -1
; RV64ZBB-NEXT: srl a2, a2, a7
; RV64ZBB-NEXT: srl a7, t0, a7
; RV64ZBB-NEXT: .LBB15_3:
; RV64ZBB-NEXT: lui t0, 1046528
; RV64ZBB-NEXT: sll a6, a6, a3
; RV64ZBB-NEXT: srai a4, a4, 63
; RV64ZBB-NEXT: xnor a7, a7, t0
; RV64ZBB-NEXT: sll a3, a5, a3
; RV64ZBB-NEXT: and a1, a1, a7
; RV64ZBB-NEXT: and a3, a4, a3
; RV64ZBB-NEXT: and a4, a4, a6
; RV64ZBB-NEXT: andn a0, a0, a3
; RV64ZBB-NEXT: or a1, a1, a2
; RV64ZBB-NEXT: or a0, a0, a4
; RV64ZBB-NEXT: ret
%result = bitinsert b87 %base, float %val, i32 %off
ret b87 %result
}
define b64 @test_bitinsert_double_full(b64 %base, double %val) {
; RV32-LABEL: test_bitinsert_double_full:
; RV32: # %bb.0:
; RV32-NEXT: mv a1, a3
; RV32-NEXT: mv a0, a2
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitinsert_double_full:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: mv a1, a3
; RV32ZBB-NEXT: mv a0, a2
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitinsert_double_full:
; RV64: # %bb.0:
; RV64-NEXT: mv a0, a1
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitinsert_double_full:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a0, a1
; RV64ZBB-NEXT: ret
%result = bitinsert b64 %base, double %val, i32 0
ret b64 %result
}
define b128 @test_bitinsert_double_const(b128 %base, double %val) {
; RV32-LABEL: test_bitinsert_double_const:
; RV32: # %bb.0:
; RV32-NEXT: lw a4, 0(a1)
; RV32-NEXT: lw a1, 4(a1)
; RV32-NEXT: sw a4, 0(a0)
; RV32-NEXT: sw a1, 4(a0)
; RV32-NEXT: sw a2, 8(a0)
; RV32-NEXT: sw a3, 12(a0)
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitinsert_double_const:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: lw a4, 0(a1)
; RV32ZBB-NEXT: lw a1, 4(a1)
; RV32ZBB-NEXT: sw a4, 0(a0)
; RV32ZBB-NEXT: sw a1, 4(a0)
; RV32ZBB-NEXT: sw a2, 8(a0)
; RV32ZBB-NEXT: sw a3, 12(a0)
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitinsert_double_const:
; RV64: # %bb.0:
; RV64-NEXT: mv a1, a2
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitinsert_double_const:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a1, a2
; RV64ZBB-NEXT: ret
%result = bitinsert b128 %base, double %val, i32 64
ret b128 %result
}
define b128 @test_bitinsert_double_var(b128 %base, double %val, i32 %off) {
; RV32-LABEL: test_bitinsert_double_var:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -80
; RV32-NEXT: .cfi_def_cfa_offset 80
; RV32-NEXT: sw s0, 76(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s1, 72(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s2, 68(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s3, 64(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset s0, -4
; RV32-NEXT: .cfi_offset s1, -8
; RV32-NEXT: .cfi_offset s2, -12
; RV32-NEXT: .cfi_offset s3, -16
; RV32-NEXT: lw a5, 0(a1)
; RV32-NEXT: lw a7, 4(a1)
; RV32-NEXT: lw a6, 8(a1)
; RV32-NEXT: lw a1, 12(a1)
; RV32-NEXT: sw a2, 16(sp)
; RV32-NEXT: sw a3, 20(sp)
; RV32-NEXT: sw zero, 24(sp)
; RV32-NEXT: sw zero, 28(sp)
; RV32-NEXT: sw zero, 0(sp)
; RV32-NEXT: sw zero, 4(sp)
; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: li a2, -1
; RV32-NEXT: srli a3, a4, 3
; RV32-NEXT: sw a2, 48(sp)
; RV32-NEXT: sw a2, 52(sp)
; RV32-NEXT: sw zero, 56(sp)
; RV32-NEXT: sw zero, 60(sp)
; RV32-NEXT: andi a2, a3, 12
; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: sw zero, 32(sp)
; RV32-NEXT: sw zero, 36(sp)
; RV32-NEXT: sw zero, 40(sp)
; RV32-NEXT: sw zero, 44(sp)
; RV32-NEXT: sub t0, a3, a2
; RV32-NEXT: lw a3, 4(t0)
; RV32-NEXT: addi t1, sp, 48
; RV32-NEXT: sub t1, t1, a2
; RV32-NEXT: lw a2, 0(t0)
; RV32-NEXT: lw t2, 8(t0)
; RV32-NEXT: lw t0, 12(t0)
; RV32-NEXT: sll t3, a3, a4
; RV32-NEXT: lw t4, 0(t1)
; RV32-NEXT: andi t5, a4, 31
; RV32-NEXT: lw t6, 4(t1)
; RV32-NEXT: srli s0, a2, 1
; RV32-NEXT: xori t5, t5, 31
; RV32-NEXT: srl s0, s0, t5
; RV32-NEXT: lw s1, 8(t1)
; RV32-NEXT: lw t1, 12(t1)
; RV32-NEXT: srli s2, t4, 1
; RV32-NEXT: sll s3, t6, a4
; RV32-NEXT: srl s2, s2, t5
; RV32-NEXT: or t3, t3, s0
; RV32-NEXT: or s0, s3, s2
; RV32-NEXT: not s0, s0
; RV32-NEXT: srli t6, t6, 1
; RV32-NEXT: sll s2, s1, a4
; RV32-NEXT: srl t6, t6, t5
; RV32-NEXT: and a7, a7, s0
; RV32-NEXT: or t6, s2, t6
; RV32-NEXT: sll s0, t2, a4
; RV32-NEXT: srli a3, a3, 1
; RV32-NEXT: srl a3, a3, t5
; RV32-NEXT: not t6, t6
; RV32-NEXT: or a3, s0, a3
; RV32-NEXT: and a6, a6, t6
; RV32-NEXT: or a7, a7, t3
; RV32-NEXT: or a3, a6, a3
; RV32-NEXT: sll a6, t0, a4
; RV32-NEXT: srli t0, t2, 1
; RV32-NEXT: srl t0, t0, t5
; RV32-NEXT: srli s1, s1, 1
; RV32-NEXT: sll t1, t1, a4
; RV32-NEXT: srl t2, s1, t5
; RV32-NEXT: or a6, a6, t0
; RV32-NEXT: or t0, t1, t2
; RV32-NEXT: not t0, t0
; RV32-NEXT: sll t1, t4, a4
; RV32-NEXT: and a1, a1, t0
; RV32-NEXT: not t0, t1
; RV32-NEXT: sll a2, a2, a4
; RV32-NEXT: and a4, a5, t0
; RV32-NEXT: or a1, a1, a6
; RV32-NEXT: or a2, a4, a2
; RV32-NEXT: sw a2, 0(a0)
; RV32-NEXT: sw a7, 4(a0)
; RV32-NEXT: sw a3, 8(a0)
; RV32-NEXT: sw a1, 12(a0)
; RV32-NEXT: lw s0, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 72(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s2, 68(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s3, 64(sp) # 4-byte Folded Reload
; RV32-NEXT: .cfi_restore s0
; RV32-NEXT: .cfi_restore s1
; RV32-NEXT: .cfi_restore s2
; RV32-NEXT: .cfi_restore s3
; RV32-NEXT: addi sp, sp, 80
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitinsert_double_var:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: addi sp, sp, -80
; RV32ZBB-NEXT: .cfi_def_cfa_offset 80
; RV32ZBB-NEXT: sw s0, 76(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s1, 72(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s2, 68(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s3, 64(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: .cfi_offset s0, -4
; RV32ZBB-NEXT: .cfi_offset s1, -8
; RV32ZBB-NEXT: .cfi_offset s2, -12
; RV32ZBB-NEXT: .cfi_offset s3, -16
; RV32ZBB-NEXT: lw a5, 0(a1)
; RV32ZBB-NEXT: lw a7, 4(a1)
; RV32ZBB-NEXT: lw a6, 8(a1)
; RV32ZBB-NEXT: lw a1, 12(a1)
; RV32ZBB-NEXT: sw a2, 16(sp)
; RV32ZBB-NEXT: sw a3, 20(sp)
; RV32ZBB-NEXT: sw zero, 24(sp)
; RV32ZBB-NEXT: sw zero, 28(sp)
; RV32ZBB-NEXT: sw zero, 0(sp)
; RV32ZBB-NEXT: sw zero, 4(sp)
; RV32ZBB-NEXT: sw zero, 8(sp)
; RV32ZBB-NEXT: sw zero, 12(sp)
; RV32ZBB-NEXT: li a2, -1
; RV32ZBB-NEXT: srli a3, a4, 3
; RV32ZBB-NEXT: sw a2, 48(sp)
; RV32ZBB-NEXT: sw a2, 52(sp)
; RV32ZBB-NEXT: sw zero, 56(sp)
; RV32ZBB-NEXT: sw zero, 60(sp)
; RV32ZBB-NEXT: andi a3, a3, 12
; RV32ZBB-NEXT: addi a2, sp, 16
; RV32ZBB-NEXT: sw zero, 32(sp)
; RV32ZBB-NEXT: sw zero, 36(sp)
; RV32ZBB-NEXT: sw zero, 40(sp)
; RV32ZBB-NEXT: sw zero, 44(sp)
; RV32ZBB-NEXT: sub t0, a2, a3
; RV32ZBB-NEXT: lw t1, 4(t0)
; RV32ZBB-NEXT: addi a2, sp, 48
; RV32ZBB-NEXT: sub a3, a2, a3
; RV32ZBB-NEXT: lw a2, 0(t0)
; RV32ZBB-NEXT: lw t2, 8(t0)
; RV32ZBB-NEXT: lw t0, 12(t0)
; RV32ZBB-NEXT: sll t3, t1, a4
; RV32ZBB-NEXT: lw t4, 0(a3)
; RV32ZBB-NEXT: andi t5, a4, 31
; RV32ZBB-NEXT: lw t6, 4(a3)
; RV32ZBB-NEXT: srli s0, a2, 1
; RV32ZBB-NEXT: xori t5, t5, 31
; RV32ZBB-NEXT: srl s0, s0, t5
; RV32ZBB-NEXT: lw s1, 8(a3)
; RV32ZBB-NEXT: lw a3, 12(a3)
; RV32ZBB-NEXT: srli s2, t4, 1
; RV32ZBB-NEXT: sll s3, t6, a4
; RV32ZBB-NEXT: srl s2, s2, t5
; RV32ZBB-NEXT: or t3, t3, s0
; RV32ZBB-NEXT: or s0, s3, s2
; RV32ZBB-NEXT: andn a7, a7, s0
; RV32ZBB-NEXT: srli t6, t6, 1
; RV32ZBB-NEXT: sll s0, s1, a4
; RV32ZBB-NEXT: srl t6, t6, t5
; RV32ZBB-NEXT: srli t1, t1, 1
; RV32ZBB-NEXT: or t6, s0, t6
; RV32ZBB-NEXT: sll s0, t2, a4
; RV32ZBB-NEXT: srl t1, t1, t5
; RV32ZBB-NEXT: or t1, s0, t1
; RV32ZBB-NEXT: andn a6, a6, t6
; RV32ZBB-NEXT: or a7, a7, t3
; RV32ZBB-NEXT: or a6, a6, t1
; RV32ZBB-NEXT: sll t0, t0, a4
; RV32ZBB-NEXT: srli t1, t2, 1
; RV32ZBB-NEXT: srl t1, t1, t5
; RV32ZBB-NEXT: srli s1, s1, 1
; RV32ZBB-NEXT: sll a3, a3, a4
; RV32ZBB-NEXT: srl t2, s1, t5
; RV32ZBB-NEXT: or t0, t0, t1
; RV32ZBB-NEXT: or a3, a3, t2
; RV32ZBB-NEXT: andn a1, a1, a3
; RV32ZBB-NEXT: sll a3, t4, a4
; RV32ZBB-NEXT: sll a2, a2, a4
; RV32ZBB-NEXT: andn a3, a5, a3
; RV32ZBB-NEXT: or a1, a1, t0
; RV32ZBB-NEXT: or a2, a3, a2
; RV32ZBB-NEXT: sw a2, 0(a0)
; RV32ZBB-NEXT: sw a7, 4(a0)
; RV32ZBB-NEXT: sw a6, 8(a0)
; RV32ZBB-NEXT: sw a1, 12(a0)
; RV32ZBB-NEXT: lw s0, 76(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s1, 72(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s2, 68(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s3, 64(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: .cfi_restore s0
; RV32ZBB-NEXT: .cfi_restore s1
; RV32ZBB-NEXT: .cfi_restore s2
; RV32ZBB-NEXT: .cfi_restore s3
; RV32ZBB-NEXT: addi sp, sp, 80
; RV32ZBB-NEXT: .cfi_def_cfa_offset 0
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitinsert_double_var:
; RV64: # %bb.0:
; RV64-NEXT: slli a4, a3, 32
; RV64-NEXT: srli a7, a4, 32
; RV64-NEXT: addi a5, a7, -64
; RV64-NEXT: li a4, -1
; RV64-NEXT: bltz a5, .LBB18_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: sll a6, a2, a7
; RV64-NEXT: sll a7, a4, a7
; RV64-NEXT: j .LBB18_3
; RV64-NEXT: .LBB18_2:
; RV64-NEXT: srli a6, a2, 1
; RV64-NEXT: not a7, a7
; RV64-NEXT: srli t0, a4, 1
; RV64-NEXT: srl a6, a6, a7
; RV64-NEXT: srl a7, t0, a7
; RV64-NEXT: .LBB18_3:
; RV64-NEXT: not a7, a7
; RV64-NEXT: srai a5, a5, 63
; RV64-NEXT: sll a4, a4, a3
; RV64-NEXT: and a1, a1, a7
; RV64-NEXT: and a4, a5, a4
; RV64-NEXT: sll a2, a2, a3
; RV64-NEXT: not a3, a4
; RV64-NEXT: and a2, a5, a2
; RV64-NEXT: and a0, a0, a3
; RV64-NEXT: or a1, a1, a6
; RV64-NEXT: or a0, a0, a2
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitinsert_double_var:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: slli a4, a3, 32
; RV64ZBB-NEXT: srli a7, a4, 32
; RV64ZBB-NEXT: addi a5, a7, -64
; RV64ZBB-NEXT: li a4, -1
; RV64ZBB-NEXT: bltz a5, .LBB18_2
; RV64ZBB-NEXT: # %bb.1:
; RV64ZBB-NEXT: sll a6, a2, a7
; RV64ZBB-NEXT: sll a7, a4, a7
; RV64ZBB-NEXT: j .LBB18_3
; RV64ZBB-NEXT: .LBB18_2:
; RV64ZBB-NEXT: srli a6, a2, 1
; RV64ZBB-NEXT: not a7, a7
; RV64ZBB-NEXT: srli t0, a4, 1
; RV64ZBB-NEXT: srl a6, a6, a7
; RV64ZBB-NEXT: srl a7, t0, a7
; RV64ZBB-NEXT: .LBB18_3:
; RV64ZBB-NEXT: andn a1, a1, a7
; RV64ZBB-NEXT: srai a5, a5, 63
; RV64ZBB-NEXT: sll a4, a4, a3
; RV64ZBB-NEXT: sll a2, a2, a3
; RV64ZBB-NEXT: and a4, a5, a4
; RV64ZBB-NEXT: and a2, a5, a2
; RV64ZBB-NEXT: andn a0, a0, a4
; RV64ZBB-NEXT: or a1, a1, a6
; RV64ZBB-NEXT: or a0, a0, a2
; RV64ZBB-NEXT: ret
%result = bitinsert b128 %base, double %val, i32 %off
ret b128 %result
}
define b231 @test_bitinsert_double_b231_var(b231 %base, double %val, i32 %off) {
; RV32-LABEL: test_bitinsert_double_b231_var:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -192
; RV32-NEXT: .cfi_def_cfa_offset 192
; RV32-NEXT: sw ra, 188(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s0, 184(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s1, 180(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s2, 176(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s3, 172(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s4, 168(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s5, 164(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s6, 160(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s7, 156(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s8, 152(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s9, 148(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s10, 144(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s11, 140(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: .cfi_offset s0, -8
; RV32-NEXT: .cfi_offset s1, -12
; RV32-NEXT: .cfi_offset s2, -16
; RV32-NEXT: .cfi_offset s3, -20
; RV32-NEXT: .cfi_offset s4, -24
; RV32-NEXT: .cfi_offset s5, -28
; RV32-NEXT: .cfi_offset s6, -32
; RV32-NEXT: .cfi_offset s7, -36
; RV32-NEXT: .cfi_offset s8, -40
; RV32-NEXT: .cfi_offset s9, -44
; RV32-NEXT: .cfi_offset s10, -48
; RV32-NEXT: .cfi_offset s11, -52
; RV32-NEXT: lw a5, 0(a1)
; RV32-NEXT: lw t3, 4(a1)
; RV32-NEXT: lw t2, 8(a1)
; RV32-NEXT: lw t1, 12(a1)
; RV32-NEXT: lw t0, 16(a1)
; RV32-NEXT: lw a7, 20(a1)
; RV32-NEXT: lw a6, 24(a1)
; RV32-NEXT: lw a1, 28(a1)
; RV32-NEXT: sw zero, 56(sp)
; RV32-NEXT: sw zero, 60(sp)
; RV32-NEXT: sw zero, 64(sp)
; RV32-NEXT: sw zero, 68(sp)
; RV32-NEXT: sw a2, 40(sp)
; RV32-NEXT: sw a3, 44(sp)
; RV32-NEXT: sw zero, 48(sp)
; RV32-NEXT: sw zero, 52(sp)
; RV32-NEXT: sw zero, 24(sp)
; RV32-NEXT: sw zero, 28(sp)
; RV32-NEXT: sw zero, 32(sp)
; RV32-NEXT: sw zero, 36(sp)
; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: sw zero, 16(sp)
; RV32-NEXT: sw zero, 20(sp)
; RV32-NEXT: li a2, -1
; RV32-NEXT: sw zero, 120(sp)
; RV32-NEXT: sw zero, 124(sp)
; RV32-NEXT: sw zero, 128(sp)
; RV32-NEXT: sw zero, 132(sp)
; RV32-NEXT: sw a2, 104(sp)
; RV32-NEXT: sw a2, 108(sp)
; RV32-NEXT: sw zero, 112(sp)
; RV32-NEXT: sw zero, 116(sp)
; RV32-NEXT: sw zero, 88(sp)
; RV32-NEXT: sw zero, 92(sp)
; RV32-NEXT: sw zero, 96(sp)
; RV32-NEXT: sw zero, 100(sp)
; RV32-NEXT: sw zero, 72(sp)
; RV32-NEXT: sw zero, 76(sp)
; RV32-NEXT: sw zero, 80(sp)
; RV32-NEXT: sw zero, 84(sp)
; RV32-NEXT: srli a2, a4, 3
; RV32-NEXT: andi a2, a2, 28
; RV32-NEXT: addi a3, sp, 40
; RV32-NEXT: sub t5, a3, a2
; RV32-NEXT: addi a3, sp, 104
; RV32-NEXT: sub t4, a3, a2
; RV32-NEXT: lw a3, 24(t5)
; RV32-NEXT: lw t6, 28(t5)
; RV32-NEXT: lw a2, 24(t4)
; RV32-NEXT: lw s3, 28(t4)
; RV32-NEXT: lw s0, 16(t5)
; RV32-NEXT: lw s2, 20(t5)
; RV32-NEXT: andi s1, a4, 31
; RV32-NEXT: srli s4, a3, 1
; RV32-NEXT: xori s1, s1, 31
; RV32-NEXT: sll s5, t6, a4
; RV32-NEXT: srl s4, s4, s1
; RV32-NEXT: sll s3, s3, a4
; RV32-NEXT: srli t6, a2, 1
; RV32-NEXT: srl s6, t6, s1
; RV32-NEXT: lw t6, 0(t5)
; RV32-NEXT: or s4, s5, s4
; RV32-NEXT: or s3, s3, s6
; RV32-NEXT: not s3, s3
; RV32-NEXT: lw s5, 4(t5)
; RV32-NEXT: and a1, a1, s3
; RV32-NEXT: lw s3, 8(t5)
; RV32-NEXT: lw s6, 12(t5)
; RV32-NEXT: srli s7, t6, 1
; RV32-NEXT: lw t5, 0(t4)
; RV32-NEXT: lw s8, 4(t4)
; RV32-NEXT: sll s9, s5, a4
; RV32-NEXT: srl s7, s7, s1
; RV32-NEXT: or a1, a1, s4
; RV32-NEXT: or s4, s9, s7
; RV32-NEXT: lw s7, 8(t4)
; RV32-NEXT: lw s9, 12(t4)
; RV32-NEXT: sll s10, s8, a4
; RV32-NEXT: srli s11, t5, 1
; RV32-NEXT: srl s11, s11, s1
; RV32-NEXT: lw ra, 16(t4)
; RV32-NEXT: lw t4, 20(t4)
; RV32-NEXT: or s10, s10, s11
; RV32-NEXT: not s10, s10
; RV32-NEXT: srli s8, s8, 1
; RV32-NEXT: sll s11, s7, a4
; RV32-NEXT: srl s8, s8, s1
; RV32-NEXT: and t3, t3, s10
; RV32-NEXT: or s8, s11, s8
; RV32-NEXT: sll s10, s3, a4
; RV32-NEXT: srli s5, s5, 1
; RV32-NEXT: srl s5, s5, s1
; RV32-NEXT: not s8, s8
; RV32-NEXT: or s5, s10, s5
; RV32-NEXT: and s8, t2, s8
; RV32-NEXT: or t2, t3, s4
; RV32-NEXT: or t3, s8, s5
; RV32-NEXT: sll s4, s6, a4
; RV32-NEXT: srli s3, s3, 1
; RV32-NEXT: srl s3, s3, s1
; RV32-NEXT: srli s5, s7, 1
; RV32-NEXT: sll s7, s9, a4
; RV32-NEXT: srl s5, s5, s1
; RV32-NEXT: or s3, s4, s3
; RV32-NEXT: or s4, s7, s5
; RV32-NEXT: not s4, s4
; RV32-NEXT: srli s5, s9, 1
; RV32-NEXT: sll s7, ra, a4
; RV32-NEXT: srl s5, s5, s1
; RV32-NEXT: and t1, t1, s4
; RV32-NEXT: or s4, s7, s5
; RV32-NEXT: sll s5, s0, a4
; RV32-NEXT: srli s6, s6, 1
; RV32-NEXT: srl s6, s6, s1
; RV32-NEXT: not s4, s4
; RV32-NEXT: or s5, s5, s6
; RV32-NEXT: and t0, t0, s4
; RV32-NEXT: or t1, t1, s3
; RV32-NEXT: or t0, t0, s5
; RV32-NEXT: sll s3, s2, a4
; RV32-NEXT: srli s4, ra, 1
; RV32-NEXT: sll s5, t4, a4
; RV32-NEXT: srl s4, s4, s1
; RV32-NEXT: srli s0, s0, 1
; RV32-NEXT: or s4, s5, s4
; RV32-NEXT: srl s0, s0, s1
; RV32-NEXT: not s4, s4
; RV32-NEXT: or s0, s3, s0
; RV32-NEXT: and a7, a7, s4
; RV32-NEXT: or a7, a7, s0
; RV32-NEXT: srli s0, s2, 1
; RV32-NEXT: sll a3, a3, a4
; RV32-NEXT: srl s0, s0, s1
; RV32-NEXT: or a3, a3, s0
; RV32-NEXT: srli t4, t4, 1
; RV32-NEXT: sll a2, a2, a4
; RV32-NEXT: srl t4, t4, s1
; RV32-NEXT: or a2, a2, t4
; RV32-NEXT: sll t4, t5, a4
; RV32-NEXT: not a2, a2
; RV32-NEXT: not t4, t4
; RV32-NEXT: sll a4, t6, a4
; RV32-NEXT: and a5, a5, t4
; RV32-NEXT: and a2, a6, a2
; RV32-NEXT: or a4, a5, a4
; RV32-NEXT: or a2, a2, a3
; RV32-NEXT: sw a4, 0(a0)
; RV32-NEXT: sw t2, 4(a0)
; RV32-NEXT: sw t3, 8(a0)
; RV32-NEXT: sw t1, 12(a0)
; RV32-NEXT: andi a1, a1, 127
; RV32-NEXT: sw t0, 16(a0)
; RV32-NEXT: sw a7, 20(a0)
; RV32-NEXT: sw a2, 24(a0)
; RV32-NEXT: sb a1, 28(a0)
; RV32-NEXT: lw ra, 188(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 184(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 180(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s2, 176(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s3, 172(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s4, 168(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s5, 164(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s6, 160(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s7, 156(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s8, 152(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s9, 148(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s10, 144(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s11, 140(sp) # 4-byte Folded Reload
; RV32-NEXT: .cfi_restore ra
; RV32-NEXT: .cfi_restore s0
; RV32-NEXT: .cfi_restore s1
; RV32-NEXT: .cfi_restore s2
; RV32-NEXT: .cfi_restore s3
; RV32-NEXT: .cfi_restore s4
; RV32-NEXT: .cfi_restore s5
; RV32-NEXT: .cfi_restore s6
; RV32-NEXT: .cfi_restore s7
; RV32-NEXT: .cfi_restore s8
; RV32-NEXT: .cfi_restore s9
; RV32-NEXT: .cfi_restore s10
; RV32-NEXT: .cfi_restore s11
; RV32-NEXT: addi sp, sp, 192
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV32ZBB-LABEL: test_bitinsert_double_b231_var:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: addi sp, sp, -192
; RV32ZBB-NEXT: .cfi_def_cfa_offset 192
; RV32ZBB-NEXT: sw ra, 188(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s0, 184(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s1, 180(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s2, 176(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s3, 172(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s4, 168(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s5, 164(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s6, 160(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s7, 156(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s8, 152(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s9, 148(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s10, 144(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: sw s11, 140(sp) # 4-byte Folded Spill
; RV32ZBB-NEXT: .cfi_offset ra, -4
; RV32ZBB-NEXT: .cfi_offset s0, -8
; RV32ZBB-NEXT: .cfi_offset s1, -12
; RV32ZBB-NEXT: .cfi_offset s2, -16
; RV32ZBB-NEXT: .cfi_offset s3, -20
; RV32ZBB-NEXT: .cfi_offset s4, -24
; RV32ZBB-NEXT: .cfi_offset s5, -28
; RV32ZBB-NEXT: .cfi_offset s6, -32
; RV32ZBB-NEXT: .cfi_offset s7, -36
; RV32ZBB-NEXT: .cfi_offset s8, -40
; RV32ZBB-NEXT: .cfi_offset s9, -44
; RV32ZBB-NEXT: .cfi_offset s10, -48
; RV32ZBB-NEXT: .cfi_offset s11, -52
; RV32ZBB-NEXT: lw a5, 0(a1)
; RV32ZBB-NEXT: lw t3, 4(a1)
; RV32ZBB-NEXT: lw t2, 8(a1)
; RV32ZBB-NEXT: lw t1, 12(a1)
; RV32ZBB-NEXT: lw t0, 16(a1)
; RV32ZBB-NEXT: lw a7, 20(a1)
; RV32ZBB-NEXT: lw a6, 24(a1)
; RV32ZBB-NEXT: lw a1, 28(a1)
; RV32ZBB-NEXT: sw zero, 56(sp)
; RV32ZBB-NEXT: sw zero, 60(sp)
; RV32ZBB-NEXT: sw zero, 64(sp)
; RV32ZBB-NEXT: sw zero, 68(sp)
; RV32ZBB-NEXT: sw a2, 40(sp)
; RV32ZBB-NEXT: sw a3, 44(sp)
; RV32ZBB-NEXT: sw zero, 48(sp)
; RV32ZBB-NEXT: sw zero, 52(sp)
; RV32ZBB-NEXT: sw zero, 24(sp)
; RV32ZBB-NEXT: sw zero, 28(sp)
; RV32ZBB-NEXT: sw zero, 32(sp)
; RV32ZBB-NEXT: sw zero, 36(sp)
; RV32ZBB-NEXT: sw zero, 8(sp)
; RV32ZBB-NEXT: sw zero, 12(sp)
; RV32ZBB-NEXT: sw zero, 16(sp)
; RV32ZBB-NEXT: sw zero, 20(sp)
; RV32ZBB-NEXT: sw zero, 120(sp)
; RV32ZBB-NEXT: sw zero, 124(sp)
; RV32ZBB-NEXT: sw zero, 128(sp)
; RV32ZBB-NEXT: sw zero, 132(sp)
; RV32ZBB-NEXT: li a2, -1
; RV32ZBB-NEXT: sw a2, 104(sp)
; RV32ZBB-NEXT: sw a2, 108(sp)
; RV32ZBB-NEXT: sw zero, 112(sp)
; RV32ZBB-NEXT: sw zero, 116(sp)
; RV32ZBB-NEXT: srli a2, a4, 3
; RV32ZBB-NEXT: sw zero, 88(sp)
; RV32ZBB-NEXT: sw zero, 92(sp)
; RV32ZBB-NEXT: sw zero, 96(sp)
; RV32ZBB-NEXT: sw zero, 100(sp)
; RV32ZBB-NEXT: andi t5, a2, 28
; RV32ZBB-NEXT: addi a2, sp, 40
; RV32ZBB-NEXT: sw zero, 72(sp)
; RV32ZBB-NEXT: sw zero, 76(sp)
; RV32ZBB-NEXT: sw zero, 80(sp)
; RV32ZBB-NEXT: sw zero, 84(sp)
; RV32ZBB-NEXT: sub a2, a2, t5
; RV32ZBB-NEXT: lw a3, 16(a2)
; RV32ZBB-NEXT: lw t6, 20(a2)
; RV32ZBB-NEXT: lw t4, 24(a2)
; RV32ZBB-NEXT: lw s2, 28(a2)
; RV32ZBB-NEXT: addi s0, sp, 104
; RV32ZBB-NEXT: andi s1, a4, 31
; RV32ZBB-NEXT: sub s5, s0, t5
; RV32ZBB-NEXT: lw t5, 24(s5)
; RV32ZBB-NEXT: lw s4, 16(s5)
; RV32ZBB-NEXT: lw s0, 20(s5)
; RV32ZBB-NEXT: lw s3, 28(s5)
; RV32ZBB-NEXT: srli s6, t4, 1
; RV32ZBB-NEXT: xori s1, s1, 31
; RV32ZBB-NEXT: sll s2, s2, a4
; RV32ZBB-NEXT: srl s6, s6, s1
; RV32ZBB-NEXT: or s6, s2, s6
; RV32ZBB-NEXT: srli s2, t5, 1
; RV32ZBB-NEXT: sll s3, s3, a4
; RV32ZBB-NEXT: srl s2, s2, s1
; RV32ZBB-NEXT: or s3, s3, s2
; RV32ZBB-NEXT: lw s2, 0(s5)
; RV32ZBB-NEXT: andn a1, a1, s3
; RV32ZBB-NEXT: lw s7, 4(s5)
; RV32ZBB-NEXT: or a1, a1, s6
; RV32ZBB-NEXT: lw s3, 0(a2)
; RV32ZBB-NEXT: lw s6, 4(a2)
; RV32ZBB-NEXT: lw s8, 8(s5)
; RV32ZBB-NEXT: lw s5, 12(s5)
; RV32ZBB-NEXT: srli s9, s2, 1
; RV32ZBB-NEXT: sll s10, s7, a4
; RV32ZBB-NEXT: srl s9, s9, s1
; RV32ZBB-NEXT: lw s11, 8(a2)
; RV32ZBB-NEXT: lw ra, 12(a2)
; RV32ZBB-NEXT: srli a2, s3, 1
; RV32ZBB-NEXT: or s9, s10, s9
; RV32ZBB-NEXT: sll s10, s6, a4
; RV32ZBB-NEXT: srl a2, a2, s1
; RV32ZBB-NEXT: or a2, s10, a2
; RV32ZBB-NEXT: andn t3, t3, s9
; RV32ZBB-NEXT: or a2, t3, a2
; RV32ZBB-NEXT: srli t3, s7, 1
; RV32ZBB-NEXT: sll s7, s8, a4
; RV32ZBB-NEXT: srl t3, t3, s1
; RV32ZBB-NEXT: srli s6, s6, 1
; RV32ZBB-NEXT: or t3, s7, t3
; RV32ZBB-NEXT: sll s7, s11, a4
; RV32ZBB-NEXT: srl s6, s6, s1
; RV32ZBB-NEXT: or s6, s7, s6
; RV32ZBB-NEXT: andn t2, t2, t3
; RV32ZBB-NEXT: or t2, t2, s6
; RV32ZBB-NEXT: srli t3, s8, 1
; RV32ZBB-NEXT: sll s6, s5, a4
; RV32ZBB-NEXT: srl t3, t3, s1
; RV32ZBB-NEXT: srli s7, s11, 1
; RV32ZBB-NEXT: or t3, s6, t3
; RV32ZBB-NEXT: sll s6, ra, a4
; RV32ZBB-NEXT: srl s7, s7, s1
; RV32ZBB-NEXT: or s6, s6, s7
; RV32ZBB-NEXT: andn t1, t1, t3
; RV32ZBB-NEXT: or t1, t1, s6
; RV32ZBB-NEXT: srli t3, s5, 1
; RV32ZBB-NEXT: sll s5, s4, a4
; RV32ZBB-NEXT: srl t3, t3, s1
; RV32ZBB-NEXT: srli s6, ra, 1
; RV32ZBB-NEXT: or t3, s5, t3
; RV32ZBB-NEXT: sll s5, a3, a4
; RV32ZBB-NEXT: srl s6, s6, s1
; RV32ZBB-NEXT: or s5, s5, s6
; RV32ZBB-NEXT: andn t0, t0, t3
; RV32ZBB-NEXT: or t0, t0, s5
; RV32ZBB-NEXT: sll t3, t6, a4
; RV32ZBB-NEXT: srli a3, a3, 1
; RV32ZBB-NEXT: srli s4, s4, 1
; RV32ZBB-NEXT: sll s5, s0, a4
; RV32ZBB-NEXT: srl s4, s4, s1
; RV32ZBB-NEXT: srl a3, a3, s1
; RV32ZBB-NEXT: or s4, s5, s4
; RV32ZBB-NEXT: or a3, t3, a3
; RV32ZBB-NEXT: andn a7, a7, s4
; RV32ZBB-NEXT: or a3, a7, a3
; RV32ZBB-NEXT: srli a7, t6, 1
; RV32ZBB-NEXT: sll t3, t4, a4
; RV32ZBB-NEXT: srl a7, a7, s1
; RV32ZBB-NEXT: or a7, t3, a7
; RV32ZBB-NEXT: srli s0, s0, 1
; RV32ZBB-NEXT: sll t3, t5, a4
; RV32ZBB-NEXT: srl t4, s0, s1
; RV32ZBB-NEXT: or t3, t3, t4
; RV32ZBB-NEXT: sll t4, s2, a4
; RV32ZBB-NEXT: sll a4, s3, a4
; RV32ZBB-NEXT: andn a5, a5, t4
; RV32ZBB-NEXT: andn a6, a6, t3
; RV32ZBB-NEXT: or a4, a5, a4
; RV32ZBB-NEXT: or a5, a6, a7
; RV32ZBB-NEXT: sw a4, 0(a0)
; RV32ZBB-NEXT: sw a2, 4(a0)
; RV32ZBB-NEXT: sw t2, 8(a0)
; RV32ZBB-NEXT: sw t1, 12(a0)
; RV32ZBB-NEXT: andi a1, a1, 127
; RV32ZBB-NEXT: sw t0, 16(a0)
; RV32ZBB-NEXT: sw a3, 20(a0)
; RV32ZBB-NEXT: sw a5, 24(a0)
; RV32ZBB-NEXT: sb a1, 28(a0)
; RV32ZBB-NEXT: lw ra, 188(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s0, 184(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s1, 180(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s2, 176(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s3, 172(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s4, 168(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s5, 164(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s6, 160(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s7, 156(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s8, 152(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s9, 148(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s10, 144(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: lw s11, 140(sp) # 4-byte Folded Reload
; RV32ZBB-NEXT: .cfi_restore ra
; RV32ZBB-NEXT: .cfi_restore s0
; RV32ZBB-NEXT: .cfi_restore s1
; RV32ZBB-NEXT: .cfi_restore s2
; RV32ZBB-NEXT: .cfi_restore s3
; RV32ZBB-NEXT: .cfi_restore s4
; RV32ZBB-NEXT: .cfi_restore s5
; RV32ZBB-NEXT: .cfi_restore s6
; RV32ZBB-NEXT: .cfi_restore s7
; RV32ZBB-NEXT: .cfi_restore s8
; RV32ZBB-NEXT: .cfi_restore s9
; RV32ZBB-NEXT: .cfi_restore s10
; RV32ZBB-NEXT: .cfi_restore s11
; RV32ZBB-NEXT: addi sp, sp, 192
; RV32ZBB-NEXT: .cfi_def_cfa_offset 0
; RV32ZBB-NEXT: ret
;
; RV64-LABEL: test_bitinsert_double_b231_var:
; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -160
; RV64-NEXT: .cfi_def_cfa_offset 160
; RV64-NEXT: sd s0, 152(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s1, 144(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s2, 136(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset s0, -8
; RV64-NEXT: .cfi_offset s1, -16
; RV64-NEXT: .cfi_offset s2, -24
; RV64-NEXT: ld a4, 0(a1)
; RV64-NEXT: ld a6, 8(a1)
; RV64-NEXT: ld a5, 16(a1)
; RV64-NEXT: ld a1, 24(a1)
; RV64-NEXT: sd a2, 96(sp)
; RV64-NEXT: sd zero, 104(sp)
; RV64-NEXT: sd zero, 112(sp)
; RV64-NEXT: sd zero, 120(sp)
; RV64-NEXT: li a2, -1
; RV64-NEXT: sd zero, 64(sp)
; RV64-NEXT: sd zero, 72(sp)
; RV64-NEXT: sd zero, 80(sp)
; RV64-NEXT: sd zero, 88(sp)
; RV64-NEXT: sd a2, 32(sp)
; RV64-NEXT: sd zero, 40(sp)
; RV64-NEXT: sd zero, 48(sp)
; RV64-NEXT: sd zero, 56(sp)
; RV64-NEXT: sd zero, 0(sp)
; RV64-NEXT: sd zero, 8(sp)
; RV64-NEXT: sd zero, 16(sp)
; RV64-NEXT: sd zero, 24(sp)
; RV64-NEXT: srli a2, a3, 3
; RV64-NEXT: andi a2, a2, 24
; RV64-NEXT: addi a7, sp, 32
; RV64-NEXT: addi t0, sp, 96
; RV64-NEXT: sub t1, a7, a2
; RV64-NEXT: sub t0, t0, a2
; RV64-NEXT: ld a7, 0(t1)
; RV64-NEXT: ld t2, 8(t1)
; RV64-NEXT: ld a2, 0(t0)
; RV64-NEXT: ld t3, 8(t0)
; RV64-NEXT: andi t4, a3, 63
; RV64-NEXT: xori t4, t4, 63
; RV64-NEXT: ld t5, 16(t1)
; RV64-NEXT: ld t1, 24(t1)
; RV64-NEXT: srli t6, a7, 1
; RV64-NEXT: sll s0, t2, a3
; RV64-NEXT: srl t6, t6, t4
; RV64-NEXT: ld s1, 16(t0)
; RV64-NEXT: ld t0, 24(t0)
; RV64-NEXT: srli s2, a2, 1
; RV64-NEXT: or t6, s0, t6
; RV64-NEXT: sll s0, t3, a3
; RV64-NEXT: srl s2, s2, t4
; RV64-NEXT: or s0, s0, s2
; RV64-NEXT: not t6, t6
; RV64-NEXT: and a6, a6, t6
; RV64-NEXT: srli t2, t2, 1
; RV64-NEXT: sll t6, t5, a3
; RV64-NEXT: srl t2, t2, t4
; RV64-NEXT: or a6, a6, s0
; RV64-NEXT: or t2, t6, t2
; RV64-NEXT: sll t6, s1, a3
; RV64-NEXT: srli t3, t3, 1
; RV64-NEXT: srl t3, t3, t4
; RV64-NEXT: not t2, t2
; RV64-NEXT: or t3, t6, t3
; RV64-NEXT: and a5, a5, t2
; RV64-NEXT: or a5, a5, t3
; RV64-NEXT: sll t0, t0, a3
; RV64-NEXT: srli s1, s1, 1
; RV64-NEXT: srli t2, t5, 1
; RV64-NEXT: sll t1, t1, a3
; RV64-NEXT: srl t2, t2, t4
; RV64-NEXT: srl t3, s1, t4
; RV64-NEXT: or t1, t1, t2
; RV64-NEXT: or t0, t0, t3
; RV64-NEXT: not t1, t1
; RV64-NEXT: and a1, a1, t1
; RV64-NEXT: sll a7, a7, a3
; RV64-NEXT: or a1, a1, t0
; RV64-NEXT: not a7, a7
; RV64-NEXT: sll a2, a2, a3
; RV64-NEXT: and a3, a4, a7
; RV64-NEXT: or a2, a3, a2
; RV64-NEXT: slli a3, a1, 25
; RV64-NEXT: srli a3, a3, 57
; RV64-NEXT: sd a2, 0(a0)
; RV64-NEXT: sd a6, 8(a0)
; RV64-NEXT: sd a5, 16(a0)
; RV64-NEXT: sw a1, 24(a0)
; RV64-NEXT: sb a3, 28(a0)
; RV64-NEXT: ld s0, 152(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s1, 144(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s2, 136(sp) # 8-byte Folded Reload
; RV64-NEXT: .cfi_restore s0
; RV64-NEXT: .cfi_restore s1
; RV64-NEXT: .cfi_restore s2
; RV64-NEXT: addi sp, sp, 160
; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
;
; RV64ZBB-LABEL: test_bitinsert_double_b231_var:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addi sp, sp, -160
; RV64ZBB-NEXT: .cfi_def_cfa_offset 160
; RV64ZBB-NEXT: sd s0, 152(sp) # 8-byte Folded Spill
; RV64ZBB-NEXT: sd s1, 144(sp) # 8-byte Folded Spill
; RV64ZBB-NEXT: sd s2, 136(sp) # 8-byte Folded Spill
; RV64ZBB-NEXT: .cfi_offset s0, -8
; RV64ZBB-NEXT: .cfi_offset s1, -16
; RV64ZBB-NEXT: .cfi_offset s2, -24
; RV64ZBB-NEXT: ld a4, 0(a1)
; RV64ZBB-NEXT: ld a6, 8(a1)
; RV64ZBB-NEXT: ld a5, 16(a1)
; RV64ZBB-NEXT: ld a1, 24(a1)
; RV64ZBB-NEXT: sd a2, 96(sp)
; RV64ZBB-NEXT: sd zero, 104(sp)
; RV64ZBB-NEXT: sd zero, 112(sp)
; RV64ZBB-NEXT: sd zero, 120(sp)
; RV64ZBB-NEXT: li a2, -1
; RV64ZBB-NEXT: sd zero, 64(sp)
; RV64ZBB-NEXT: sd zero, 72(sp)
; RV64ZBB-NEXT: sd zero, 80(sp)
; RV64ZBB-NEXT: sd zero, 88(sp)
; RV64ZBB-NEXT: sd a2, 32(sp)
; RV64ZBB-NEXT: sd zero, 40(sp)
; RV64ZBB-NEXT: sd zero, 48(sp)
; RV64ZBB-NEXT: sd zero, 56(sp)
; RV64ZBB-NEXT: sd zero, 0(sp)
; RV64ZBB-NEXT: sd zero, 8(sp)
; RV64ZBB-NEXT: sd zero, 16(sp)
; RV64ZBB-NEXT: sd zero, 24(sp)
; RV64ZBB-NEXT: srli a2, a3, 3
; RV64ZBB-NEXT: andi a2, a2, 24
; RV64ZBB-NEXT: addi a7, sp, 32
; RV64ZBB-NEXT: addi t0, sp, 96
; RV64ZBB-NEXT: sub t1, a7, a2
; RV64ZBB-NEXT: sub t0, t0, a2
; RV64ZBB-NEXT: ld a2, 0(t1)
; RV64ZBB-NEXT: ld t2, 8(t1)
; RV64ZBB-NEXT: ld a7, 0(t0)
; RV64ZBB-NEXT: ld t3, 8(t0)
; RV64ZBB-NEXT: andi t4, a3, 63
; RV64ZBB-NEXT: xori t4, t4, 63
; RV64ZBB-NEXT: ld t5, 16(t1)
; RV64ZBB-NEXT: ld t1, 24(t1)
; RV64ZBB-NEXT: srli t6, a2, 1
; RV64ZBB-NEXT: sll s0, t2, a3
; RV64ZBB-NEXT: srl t6, t6, t4
; RV64ZBB-NEXT: ld s1, 16(t0)
; RV64ZBB-NEXT: ld t0, 24(t0)
; RV64ZBB-NEXT: srli s2, a7, 1
; RV64ZBB-NEXT: or t6, s0, t6
; RV64ZBB-NEXT: sll s0, t3, a3
; RV64ZBB-NEXT: srl s2, s2, t4
; RV64ZBB-NEXT: or s0, s0, s2
; RV64ZBB-NEXT: andn a6, a6, t6
; RV64ZBB-NEXT: or a6, a6, s0
; RV64ZBB-NEXT: srli t2, t2, 1
; RV64ZBB-NEXT: sll t6, t5, a3
; RV64ZBB-NEXT: srl t2, t2, t4
; RV64ZBB-NEXT: srli t3, t3, 1
; RV64ZBB-NEXT: or t2, t6, t2
; RV64ZBB-NEXT: sll t6, s1, a3
; RV64ZBB-NEXT: srl t3, t3, t4
; RV64ZBB-NEXT: or t3, t6, t3
; RV64ZBB-NEXT: andn a5, a5, t2
; RV64ZBB-NEXT: or a5, a5, t3
; RV64ZBB-NEXT: sll t0, t0, a3
; RV64ZBB-NEXT: srli s1, s1, 1
; RV64ZBB-NEXT: srli t2, t5, 1
; RV64ZBB-NEXT: sll t1, t1, a3
; RV64ZBB-NEXT: srl t2, t2, t4
; RV64ZBB-NEXT: srl t3, s1, t4
; RV64ZBB-NEXT: or t1, t1, t2
; RV64ZBB-NEXT: or t0, t0, t3
; RV64ZBB-NEXT: andn a1, a1, t1
; RV64ZBB-NEXT: or a1, a1, t0
; RV64ZBB-NEXT: sll a2, a2, a3
; RV64ZBB-NEXT: sll a3, a7, a3
; RV64ZBB-NEXT: andn a2, a4, a2
; RV64ZBB-NEXT: or a2, a2, a3
; RV64ZBB-NEXT: slli a3, a1, 25
; RV64ZBB-NEXT: srli a3, a3, 57
; RV64ZBB-NEXT: sd a2, 0(a0)
; RV64ZBB-NEXT: sd a6, 8(a0)
; RV64ZBB-NEXT: sd a5, 16(a0)
; RV64ZBB-NEXT: sw a1, 24(a0)
; RV64ZBB-NEXT: sb a3, 28(a0)
; RV64ZBB-NEXT: ld s0, 152(sp) # 8-byte Folded Reload
; RV64ZBB-NEXT: ld s1, 144(sp) # 8-byte Folded Reload
; RV64ZBB-NEXT: ld s2, 136(sp) # 8-byte Folded Reload
; RV64ZBB-NEXT: .cfi_restore s0
; RV64ZBB-NEXT: .cfi_restore s1
; RV64ZBB-NEXT: .cfi_restore s2
; RV64ZBB-NEXT: addi sp, sp, 160
; RV64ZBB-NEXT: .cfi_def_cfa_offset 0
; RV64ZBB-NEXT: ret
%result = bitinsert b231 %base, double %val, i32 %off
ret b231 %result
}