llvm/test/CodeGen/PowerPC/splat-extend.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN:   -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN:   FileCheck %s
; RUN: llc -verify-machineinstrs  -mtriple=powerpc64-aix-xcoff \
; RUN:   -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN:   FileCheck %s
; RUN: llc -verify-machineinstrs  -mtriple=powerpc-aix-xcoff \
; RUN:   -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN:   FileCheck %s

define dso_local noundef <8 x i16> @v103s() local_unnamed_addr {
; CHECK-LABEL: v103s:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxspltib v2, 103
; CHECK-NEXT:    vupklsb v2, v2
; CHECK-NEXT:    blr
entry:
  ret <8 x i16> splat (i16 103)
}

define dso_local noundef <2 x i64> @v103l() local_unnamed_addr {
; CHECK-LABEL: v103l:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxspltib v2, 103
; CHECK-NEXT:    vextsb2d v2, v2
; CHECK-NEXT:    blr
entry:
  ret <2 x i64> splat (i64 103)
}

define dso_local noundef <4 x i32> @v103i() local_unnamed_addr {
; CHECK-LABEL: v103i:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxspltib v2, 103
; CHECK-NEXT:    vextsb2w v2, v2
; CHECK-NEXT:    blr
entry:
  ret <4 x i32> splat (i32 103)
}

define dso_local noundef <2 x i64> @v11l() local_unnamed_addr {
; CHECK-LABEL: v11l:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vspltisw v2, -11
; CHECK-NEXT:    vupklsw v2, v2
; CHECK-NEXT:    blr
entry:
  ret <2 x i64> splat (i64 -11)
}

declare <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8>)

define i32 @crash(ptr %p) {
; CHECK-LABEL: crash:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxspltib v2, 127
; CHECK-NEXT:    vextsb2w v2, v2
; CHECK-NEXT:    stxv v2, 0(r3)
; CHECK-NEXT:    li r3, 0
; CHECK-NEXT:    stxv v2, 0(0)
; CHECK-NEXT:    blr
entry:
  store <4 x i32> <i32 127, i32 127, i32 127, i32 127>, ptr %p, align 16
  %0 = call <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>)
  store <4 x i32> %0, ptr null, align 16
  ret i32 0
}