llvm/test/CodeGen/AMDGPU/loop-header-align-gfx950.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgpu9.50 -run-pass=block-placement -o - %s | FileCheck %s

# Test that loop headers are aligned to 32 bytes on GFX950 when the first
# instruction is 8 bytes, to prevent the instruction from being split by the
# 32-byte fetch window boundary.
# The second test case verifies that 4-byte instructions do NOT trigger
# alignment.
# The rotated cases verify that the decision is made for the block that block
# placement actually aligns (the backedge destination), which after rotation is
# not the LoopInfo header. The extra preheader keeps the function entry out of
# the rotated chain, and the diamond gives placement a landing pad distinct
# from the natural header.

---
name:            loop_with_8byte_first_inst
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: loop_with_8byte_first_inst
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $sgpr0_sgpr1 = S_MOV_B64 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1 (align 32):
  ; CHECK-NEXT:   successors: %bb.2(0x04000000), %bb.1(0x7c000000)
  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $vgpr0_vgpr1 = V_LSHRREV_B64_e64 1, killed $vgpr0_vgpr1, implicit $exec
  ; CHECK-NEXT:   V_CMP_EQ_U64_e32 0, $vgpr0_vgpr1, implicit-def $vcc, implicit $exec
  ; CHECK-NEXT:   renamable $sgpr0_sgpr1 = S_OR_B64 killed renamable $vcc, killed renamable $sgpr0_sgpr1, implicit-def $scc
  ; CHECK-NEXT:   $exec = S_ANDN2_B64 $exec, renamable $sgpr0_sgpr1, implicit-def $scc
  ; CHECK-NEXT:   S_CBRANCH_EXECNZ %bb.1, implicit $exec
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr0_sgpr1, implicit-def $scc
  ; CHECK-NEXT:   S_SETPC_B64_return undef $sgpr30_sgpr31
  bb.0:
    successors: %bb.1(0x80000000)
    liveins: $vgpr0_vgpr1

    renamable $sgpr0_sgpr1 = S_MOV_B64 0

  bb.1:
    successors: %bb.2(0x04000000), %bb.1(0x7c000000)
    liveins: $sgpr0_sgpr1, $vgpr0_vgpr1

    renamable $vgpr0_vgpr1 = V_LSHRREV_B64_e64 1, killed renamable $vgpr0_vgpr1, implicit $exec
    V_CMP_EQ_U64_e32 0, $vgpr0_vgpr1, implicit-def $vcc, implicit $exec
    renamable $sgpr0_sgpr1 = S_OR_B64 killed renamable $vcc, killed renamable $sgpr0_sgpr1, implicit-def $scc
    $exec = S_ANDN2_B64 $exec, renamable $sgpr0_sgpr1, implicit-def $scc
    S_CBRANCH_EXECNZ %bb.1, implicit $exec

  bb.2:
    liveins: $sgpr0_sgpr1

    $exec = S_OR_B64 $exec, killed renamable $sgpr0_sgpr1, implicit-def $scc
    S_SETPC_B64_return undef $sgpr30_sgpr31
...

---
name:            loop_with_4byte_first_inst
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: loop_with_4byte_first_inst
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $sgpr0_sgpr1 = S_MOV_B64 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x04000000), %bb.1(0x7c000000)
  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1, $vgpr0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $vgpr0 = V_ADD_U32_e32 1, killed $vgpr0, implicit $exec
  ; CHECK-NEXT:   V_CMP_LT_U32_e32 10, $vgpr0, implicit-def $vcc, implicit $exec
  ; CHECK-NEXT:   renamable $sgpr0_sgpr1 = S_OR_B64 killed renamable $vcc, killed renamable $sgpr0_sgpr1, implicit-def $scc
  ; CHECK-NEXT:   $exec = S_ANDN2_B64 $exec, renamable $sgpr0_sgpr1, implicit-def $scc
  ; CHECK-NEXT:   S_CBRANCH_EXECNZ %bb.1, implicit $exec
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr0_sgpr1, implicit-def $scc
  ; CHECK-NEXT:   S_SETPC_B64_return undef $sgpr30_sgpr31
  bb.0:
    successors: %bb.1(0x80000000)
    liveins: $vgpr0

    renamable $sgpr0_sgpr1 = S_MOV_B64 0

  bb.1:
    successors: %bb.2(0x04000000), %bb.1(0x7c000000)
    liveins: $sgpr0_sgpr1, $vgpr0

    renamable $vgpr0 = V_ADD_U32_e32 1, killed $vgpr0, implicit $exec
    V_CMP_LT_U32_e32 10, $vgpr0, implicit-def $vcc, implicit $exec
    renamable $sgpr0_sgpr1 = S_OR_B64 killed renamable $vcc, killed renamable $sgpr0_sgpr1, implicit-def $scc
    $exec = S_ANDN2_B64 $exec, renamable $sgpr0_sgpr1, implicit-def $scc
    S_CBRANCH_EXECNZ %bb.1, implicit $exec

  bb.2:
    liveins: $sgpr0_sgpr1

    $exec = S_OR_B64 $exec, killed renamable $sgpr0_sgpr1, implicit-def $scc
    S_SETPC_B64_return undef $sgpr30_sgpr31
...

---
name:            rotated_loop_with_4byte_landing_pad
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: rotated_loop_with_4byte_landing_pad
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_BRANCH %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.6:
  ; CHECK-NEXT:   successors: %bb.7(0x04000000), %bb.2(0x7c000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $vgpr0 = V_ADD_U32_e32 1, $vgpr0, implicit $exec
  ; CHECK-NEXT:   V_CMP_EQ_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.7, implicit killed $vcc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.4(0x40000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $vgpr0_vgpr1 = V_LSHRREV_B64_e64 1, killed $vgpr0_vgpr1, implicit $exec
  ; CHECK-NEXT:   V_CMP_EQ_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
  ; CHECK-NEXT:   S_CBRANCH_VCCZ %bb.4, implicit killed $vcc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $vgpr0 = V_ADD_U32_e32 1, $vgpr0, implicit $exec
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.4:
  ; CHECK-NEXT:   successors: %bb.5(0x40000000), %bb.6(0x40000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $vgpr0 = V_ADD_U32_e32 1, $vgpr0, implicit $exec
  ; CHECK-NEXT:   V_CMP_EQ_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
  ; CHECK-NEXT:   S_CBRANCH_VCCZ %bb.6, implicit killed $vcc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.5:
  ; CHECK-NEXT:   successors: %bb.6(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $vgpr0 = V_ADD_U32_e32 1, $vgpr0, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.6
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.7:
  ; CHECK-NEXT:   S_SETPC_B64_return undef $sgpr30_sgpr31
  bb.0:
    successors: %bb.1(0x80000000)
    liveins: $vgpr0_vgpr1

    S_BRANCH %bb.1

  bb.1:
    successors: %bb.2(0x80000000)
    liveins: $vgpr0_vgpr1

    S_BRANCH %bb.2

  bb.2:
    successors: %bb.3(0x40000000), %bb.4(0x40000000)
    liveins: $vgpr0_vgpr1

    renamable $vgpr0_vgpr1 = V_LSHRREV_B64_e64 1, killed renamable $vgpr0_vgpr1, implicit $exec
    V_CMP_EQ_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
    S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
    S_BRANCH %bb.4

  bb.3:
    successors: %bb.4(0x80000000)
    liveins: $vgpr0_vgpr1

    renamable $vgpr0 = V_ADD_U32_e32 1, renamable $vgpr0, implicit $exec
    S_BRANCH %bb.4

  bb.4:
    successors: %bb.5(0x40000000), %bb.6(0x40000000)
    liveins: $vgpr0_vgpr1

    renamable $vgpr0 = V_ADD_U32_e32 1, renamable $vgpr0, implicit $exec
    V_CMP_EQ_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
    S_CBRANCH_VCCNZ %bb.5, implicit killed $vcc
    S_BRANCH %bb.6

  bb.5:
    successors: %bb.6(0x80000000)
    liveins: $vgpr0_vgpr1

    renamable $vgpr0 = V_ADD_U32_e32 1, renamable $vgpr0, implicit $exec
    S_BRANCH %bb.6

  bb.6:
    successors: %bb.7(0x04000000), %bb.2(0x7c000000)
    liveins: $vgpr0_vgpr1

    renamable $vgpr0 = V_ADD_U32_e32 1, renamable $vgpr0, implicit $exec
    V_CMP_EQ_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
    S_CBRANCH_VCCNZ %bb.7, implicit killed $vcc
    S_BRANCH %bb.2

  bb.7:
    S_SETPC_B64_return undef $sgpr30_sgpr31
...

---
name:            rotated_loop_with_8byte_landing_pad
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: rotated_loop_with_8byte_landing_pad
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_BRANCH %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.6 (align 32):
  ; CHECK-NEXT:   successors: %bb.7(0x04000000), %bb.2(0x7c000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $vgpr0_vgpr1 = V_LSHRREV_B64_e64 1, $vgpr0_vgpr1, implicit $exec
  ; CHECK-NEXT:   V_CMP_EQ_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.7, implicit killed $vcc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.4(0x40000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $vgpr0_vgpr1 = V_LSHRREV_B64_e64 1, $vgpr0_vgpr1, implicit $exec
  ; CHECK-NEXT:   V_CMP_EQ_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
  ; CHECK-NEXT:   S_CBRANCH_VCCZ %bb.4, implicit killed $vcc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $vgpr0 = V_ADD_U32_e32 1, $vgpr0, implicit $exec
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.4:
  ; CHECK-NEXT:   successors: %bb.5(0x40000000), %bb.6(0x40000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $vgpr0 = V_ADD_U32_e32 1, $vgpr0, implicit $exec
  ; CHECK-NEXT:   V_CMP_EQ_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
  ; CHECK-NEXT:   S_CBRANCH_VCCZ %bb.6, implicit killed $vcc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.5:
  ; CHECK-NEXT:   successors: %bb.6(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0_vgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $vgpr0 = V_ADD_U32_e32 1, $vgpr0, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.6
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.7:
  ; CHECK-NEXT:   S_SETPC_B64_return undef $sgpr30_sgpr31
  bb.0:
    successors: %bb.1(0x80000000)
    liveins: $vgpr0_vgpr1

    S_BRANCH %bb.1

  bb.1:
    successors: %bb.2(0x80000000)
    liveins: $vgpr0_vgpr1

    S_BRANCH %bb.2

  bb.2:
    successors: %bb.3(0x40000000), %bb.4(0x40000000)
    liveins: $vgpr0_vgpr1

    renamable $vgpr0_vgpr1 = V_LSHRREV_B64_e64 1, renamable $vgpr0_vgpr1, implicit $exec
    V_CMP_EQ_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
    S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
    S_BRANCH %bb.4

  bb.3:
    successors: %bb.4(0x80000000)
    liveins: $vgpr0_vgpr1

    renamable $vgpr0 = V_ADD_U32_e32 1, renamable $vgpr0, implicit $exec
    S_BRANCH %bb.4

  bb.4:
    successors: %bb.5(0x40000000), %bb.6(0x40000000)
    liveins: $vgpr0_vgpr1

    renamable $vgpr0 = V_ADD_U32_e32 1, renamable $vgpr0, implicit $exec
    V_CMP_EQ_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
    S_CBRANCH_VCCNZ %bb.5, implicit killed $vcc
    S_BRANCH %bb.6

  bb.5:
    successors: %bb.6(0x80000000)
    liveins: $vgpr0_vgpr1

    renamable $vgpr0 = V_ADD_U32_e32 1, renamable $vgpr0, implicit $exec
    S_BRANCH %bb.6

  bb.6:
    successors: %bb.7(0x04000000), %bb.2(0x7c000000)
    liveins: $vgpr0_vgpr1

    renamable $vgpr0_vgpr1 = V_LSHRREV_B64_e64 1, renamable $vgpr0_vgpr1, implicit $exec
    V_CMP_EQ_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
    S_CBRANCH_VCCNZ %bb.7, implicit killed $vcc
    S_BRANCH %bb.2

  bb.7:
    S_SETPC_B64_return undef $sgpr30_sgpr31
...