llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GISEL %s
; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 < %s | FileCheck -check-prefixes=GFX11 %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GFX12 %s

define float @v_exp2_f32(float %src)  {
; GCN-LABEL: v_exp2_f32:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_exp_f32_e32 v0, v0
; GCN-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_exp2_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_exp_f32_e32 v0, v0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_exp2_f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_exp_f32_e32 v0, v0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %exp2 = call float @llvm.amdgcn.exp2.f32(float %src)
  ret float %exp2
}
define float @v_exp2_f32_uniform(float inreg %src)  {
; GCN-LABEL: v_exp2_f32_uniform:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_exp_f32_e32 v0, s16
; GCN-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_exp2_f32_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_exp_f32_e32 v0, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_exp2_f32_uniform:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_s_exp_f32 s0, s0
; GFX12-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT:    s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %exp2 = call float @llvm.amdgcn.exp2.f32(float %src)
  ret float %exp2
}

define float @v_fabs_exp2_f32(float %src)  {
; GCN-LABEL: v_fabs_exp2_f32:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_exp_f32_e64 v0, |v0|
; GCN-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fabs_exp2_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_exp_f32_e64 v0, |v0|
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_fabs_exp2_f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_exp_f32_e64 v0, |v0|
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %fabs.src = call float @llvm.fabs.f32(float %src)
  %exp2 = call float @llvm.amdgcn.exp2.f32(float %fabs.src)
  ret float %exp2
}

define float @v_fneg_fabs_exp2_f32(float %src)  {
; GCN-LABEL: v_fneg_fabs_exp2_f32:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_exp_f32_e64 v0, -|v0|
; GCN-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fneg_fabs_exp2_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_exp_f32_e64 v0, -|v0|
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_fneg_fabs_exp2_f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_exp_f32_e64 v0, -|v0|
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %fabs.src = call float @llvm.fabs.f32(float %src)
  %neg.fabs.src = fneg float %fabs.src
  %exp2 = call float @llvm.amdgcn.exp2.f32(float %neg.fabs.src)
  ret float %exp2
}

define half @v_exp2_f16(half %src)  {
; GCN-LABEL: v_exp2_f16:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_exp_f16_e32 v0, v0
; GCN-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_exp2_f16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_exp_f16_e32 v0.l, v0.l
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_exp2_f16:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_exp_f16_e32 v0.l, v0.l
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %exp2 = call half @llvm.amdgcn.exp2.f16(half %src)
  ret half %exp2
}

define half @v_exp2_f16_uniform(half inreg %src)  {
; GCN-LABEL: v_exp2_f16_uniform:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_exp_f16_e32 v0, s16
; GCN-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_exp2_f16_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_exp_f16_e32 v0.l, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_exp2_f16_uniform:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_s_exp_f16 s0, s0
; GFX12-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT:    s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %exp2 = call half @llvm.amdgcn.exp2.f16(half %src)
  ret half %exp2
}

define half @v_fabs_exp2_f16(half %src)  {
; GCN-LABEL: v_fabs_exp2_f16:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_exp_f16_e64 v0, |v0|
; GCN-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fabs_exp2_f16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_exp_f16_e64 v0.l, |v0.l|
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_fabs_exp2_f16:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_exp_f16_e64 v0.l, |v0.l|
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %fabs.src = call half @llvm.fabs.f16(half %src)
  %exp2 = call half @llvm.amdgcn.exp2.f16(half %fabs.src)
  ret half %exp2
}

define half @v_fneg_fabs_exp2_f16(half %src)  {
; GCN-LABEL: v_fneg_fabs_exp2_f16:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_exp_f16_e64 v0, -|v0|
; GCN-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fneg_fabs_exp2_f16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_exp_f16_e64 v0.l, -|v0.l|
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_fneg_fabs_exp2_f16:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_exp_f16_e64 v0.l, -|v0.l|
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %fabs.src = call half @llvm.fabs.f16(half %src)
  %neg.fabs.src = fneg half %fabs.src
  %exp2 = call half @llvm.amdgcn.exp2.f16(half %neg.fabs.src)
  ret half %exp2
}

declare half @llvm.amdgcn.exp2.f16(half) #0
declare float @llvm.amdgcn.exp2.f32(float) #0
declare float @llvm.fabs.f32(float) #0
declare half @llvm.fabs.f16(half) #0

attributes #0 = { nounwind readnone speculatable willreturn }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GISEL: {{.*}}
; SDAG: {{.*}}