| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | |
| ; RUN: llc -global-isel -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GFX6 %s | |
| ; RUN: llc -global-isel -mtriple=amdgpu8.03 < %s | FileCheck -check-prefix=GFX8 %s | |
| ; RUN: llc -global-isel -mtriple=amdgpu9.00 < %s | FileCheck -check-prefix=GFX9 %s | |
| ; RUN: llc -global-isel -mtriple=amdgpu10.10 < %s | FileCheck -check-prefix=GFX10 %s | |
| ; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s | |
| ; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s | |
| define float @v_pow_f32(float %x, float %y) { | |
| ; GFX6-LABEL: v_pow_f32: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2 | |
| ; GFX6-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1 | |
| ; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1 | |
| ; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v1, v1, v3 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f32: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX8-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX8-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX8-NEXT: v_ldexp_f32 v2, v2, v3 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1 | |
| ; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1 | |
| ; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f32: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX9-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX9-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX9-NEXT: v_ldexp_f32 v2, v2, v3 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1 | |
| ; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v1, -2 | |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX9-NEXT: v_and_or_b32 v1, v2, v1, v3 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f32: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| | |
| ; GFX10-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX10-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1 | |
| ; GFX10-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1 | |
| ; GFX10-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v6, v3 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v6, v3 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, v2, v4 | |
| ; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v0 | |
| ; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4 | |
| ; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v1, s4 | |
| ; GFX10-NEXT: s_xor_b32 s4, vcc_lo, exec_lo | |
| ; GFX10-NEXT: s_and_b32 s4, s6, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-LABEL: v_pow_f32: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| | |
| ; GFX11-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 24 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0 | |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX11-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX11-NEXT: v_mul_f32_e32 v3, 0.5, v1 | |
| ; GFX11-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_trunc_f32_e32 v6, v3 | |
| ; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v6, v3 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v2, v2, v4 | |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v0 | |
| ; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0 | |
| ; GFX11-NEXT: s_xor_b32 s0, vcc_lo, exec_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | |
| ; GFX11-NEXT: s_and_b32 s0, s2, s0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] | |
| %pow = call float @llvm.pow.f32(float %x, float %y) | |
| ret float %pow | |
| } | |
| define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) { | |
| ; GFX6-LABEL: v_pow_v2f32: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_mov_b32_e32 v4, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v4 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v5, 5, v5 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v5, |v0|, v5 | |
| ; GFX6-NEXT: v_log_f32_e32 v5, v5 | |
| ; GFX6-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v5, v5, v7 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v5, v2, v5 | |
| ; GFX6-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v5, v7 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v5, v5, v9 | |
| ; GFX6-NEXT: v_exp_f32_e32 v5, v5 | |
| ; GFX6-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24 | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v5, v5, v10 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v10, v2 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v10, v2 | |
| ; GFX6-NEXT: v_mul_f32_e32 v2, 0.5, v2 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v10, v2 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v2 | |
| ; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v5 | |
| ; GFX6-NEXT: v_and_b32_e32 v10, 0x80000000, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v2, v2, v10 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5] | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 5, v0 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v0, |v1|, v0 | |
| ; GFX6-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5] | |
| ; GFX6-NEXT: s_xor_b64 s[10:11], vcc, exec | |
| ; GFX6-NEXT: v_mov_b32_e32 v4, 0x7fc00000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v0, v0, v5 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v3, v0 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v7 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v0, v0, v5 | |
| ; GFX6-NEXT: v_exp_f32_e32 v5, v0 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], s[8:9], s[10:11] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v9, vcc | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v2, v5, v2 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v5, v3 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v3 | |
| ; GFX6-NEXT: v_mul_f32_e32 v3, 0.5, v3 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v5, v3 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v3 | |
| ; GFX6-NEXT: v_and_b32_e32 v3, 0x7fffffff, v2 | |
| ; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v1 | |
| ; GFX6-NEXT: v_or_b32_e32 v3, v3, v5 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[4:5] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24 | |
| ; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_v2f32: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_mov_b32_e32 v4, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v4 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v5, 5, v5 | |
| ; GFX8-NEXT: v_ldexp_f32 v5, |v0|, v5 | |
| ; GFX8-NEXT: v_log_f32_e32 v5, v5 | |
| ; GFX8-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v5, v5, v7 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v5, v2, v5 | |
| ; GFX8-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v5, v7 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v5, v5, v9 | |
| ; GFX8-NEXT: v_exp_f32_e32 v5, v5 | |
| ; GFX8-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24 | |
| ; GFX8-NEXT: v_ldexp_f32 v5, v5, v10 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v10, v2 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v10, v2 | |
| ; GFX8-NEXT: v_mul_f32_e32 v2, 0.5, v2 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v10, v2 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v2 | |
| ; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v5 | |
| ; GFX8-NEXT: v_and_b32_e32 v10, 0x80000000, v0 | |
| ; GFX8-NEXT: v_or_b32_e32 v2, v2, v10 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5] | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 5, v0 | |
| ; GFX8-NEXT: v_ldexp_f32 v0, |v1|, v0 | |
| ; GFX8-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5] | |
| ; GFX8-NEXT: s_xor_b64 s[10:11], vcc, exec | |
| ; GFX8-NEXT: v_mov_b32_e32 v4, 0x7fc00000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v0, v0, v5 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v3, v0 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v7 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v0, v0, v5 | |
| ; GFX8-NEXT: v_exp_f32_e32 v5, v0 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], s[8:9], s[10:11] | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v9, vcc | |
| ; GFX8-NEXT: v_ldexp_f32 v2, v5, v2 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v5, v3 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v3 | |
| ; GFX8-NEXT: v_mul_f32_e32 v3, 0.5, v3 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v5, v3 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v3 | |
| ; GFX8-NEXT: v_and_b32_e32 v3, 0x7fffffff, v2 | |
| ; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v1 | |
| ; GFX8-NEXT: v_or_b32_e32 v3, v3, v5 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[4:5] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24 | |
| ; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_v2f32: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_mov_b32_e32 v4, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v4 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v5, 5, v5 | |
| ; GFX9-NEXT: v_ldexp_f32 v5, |v0|, v5 | |
| ; GFX9-NEXT: v_log_f32_e32 v5, v5 | |
| ; GFX9-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v5, v5, v7 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v5, v2, v5 | |
| ; GFX9-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v5, v7 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v5, v5, v9 | |
| ; GFX9-NEXT: v_exp_f32_e32 v5, v5 | |
| ; GFX9-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24 | |
| ; GFX9-NEXT: v_ldexp_f32 v5, v5, v10 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v10, v2 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v10, v2 | |
| ; GFX9-NEXT: v_mul_f32_e32 v2, 0.5, v2 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v10, v2 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v2 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v2, -2 | |
| ; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v0 | |
| ; GFX9-NEXT: v_and_or_b32 v10, v5, v2, v10 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v10, s[4:5] | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 5, v0 | |
| ; GFX9-NEXT: v_ldexp_f32 v0, |v1|, v0 | |
| ; GFX9-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, v6, s[4:5] | |
| ; GFX9-NEXT: s_xor_b64 s[10:11], vcc, exec | |
| ; GFX9-NEXT: v_mov_b32_e32 v4, 0x7fc00000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v0, v0, v6 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v3, v0 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v7 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v0, v0, v6 | |
| ; GFX9-NEXT: v_exp_f32_e32 v6, v0 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], s[8:9], s[10:11] | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v0, v5, v4, s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc | |
| ; GFX9-NEXT: v_ldexp_f32 v5, v6, v5 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v6, v3 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v3 | |
| ; GFX9-NEXT: v_mul_f32_e32 v3, 0.5, v3 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v6, v3 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v6, v3 | |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v1 | |
| ; GFX9-NEXT: v_and_or_b32 v2, v5, v2, v3 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v1, 24 | |
| ; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_v2f32: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v1| | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s8, v0, 24 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v8, v2 | |
| ; GFX10-NEXT: v_mul_f32_e32 v9, 0.5, v3 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s5 | |
| ; GFX10-NEXT: v_and_b32_e32 v10, 0x80000000, v1 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v5, 5, v5 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s9, v1, 24 | |
| ; GFX10-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX10-NEXT: v_ldexp_f32 v5, |v1|, v5 | |
| ; GFX10-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX10-NEXT: v_log_f32_e32 v5, v5 | |
| ; GFX10-NEXT: v_sub_f32_e32 v4, v4, v6 | |
| ; GFX10-NEXT: v_sub_f32_e32 v5, v5, v7 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v2, v4 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v5, v3, v5 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, s4 | |
| ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v2 | |
| ; GFX10-NEXT: v_add_f32_e32 v4, v4, v6 | |
| ; GFX10-NEXT: v_add_f32_e32 v5, v5, v7 | |
| ; GFX10-NEXT: v_and_b32_e32 v7, 0x80000000, v0 | |
| ; GFX10-NEXT: v_mul_f32_e32 v6, 0.5, v2 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v8, v9 | |
| ; GFX10-NEXT: v_exp_f32_e32 v0, v4 | |
| ; GFX10-NEXT: v_exp_f32_e32 v5, v5 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v4, v3 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v2, v6 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v8, v9 | |
| ; GFX10-NEXT: s_xor_b32 s10, vcc_lo, exec_lo | |
| ; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v4, v3 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v2, v6 | |
| ; GFX10-NEXT: v_ldexp_f32 v0, v0, v11 | |
| ; GFX10-NEXT: v_ldexp_f32 v1, v5, v1 | |
| ; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s5 | |
| ; GFX10-NEXT: s_and_b32 s5, s8, s10 | |
| ; GFX10-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v7 | |
| ; GFX10-NEXT: v_and_or_b32 v3, 0x7fffffff, v1, v10 | |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo | |
| ; GFX10-NEXT: s_and_b32 vcc_lo, s4, s6 | |
| ; GFX10-NEXT: s_xor_b32 s4, s4, exec_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo | |
| ; GFX10-NEXT: s_and_b32 s4, s9, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-LABEL: v_pow_v2f32: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v1| | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| | |
| ; GFX11-NEXT: v_cmp_class_f32_e64 s4, v0, 24 | |
| ; GFX11-NEXT: v_trunc_f32_e32 v8, v2 | |
| ; GFX11-NEXT: v_and_b32_e32 v10, 0x80000000, v1 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, s1 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1 | |
| ; GFX11-NEXT: v_cmp_class_f32_e64 s5, v1, 24 | |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 5, v5 | |
| ; GFX11-NEXT: v_mul_f32_e32 v9, 0.5, v3 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_ldexp_f32 v5, |v1|, v5 | |
| ; GFX11-NEXT: v_log_f32_e32 v5, v5 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_dual_sub_f32 v5, v5, v7 :: v_dual_lshlrev_b32 v4, 5, v4 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v5, v3, v5 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v5 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, s0 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_sub_f32_e32 v4, v4, v6 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, s0 | |
| ; GFX11-NEXT: v_dual_add_f32 v5, v5, v7 :: v_dual_mul_dx9_zero_f32 v4, v2, v4 | |
| ; GFX11-NEXT: v_and_b32_e32 v7, 0x80000000, v0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_exp_f32_e32 v5, v5 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v4 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 0x42800000, vcc_lo | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v2 | |
| ; GFX11-NEXT: v_trunc_f32_e32 v8, v9 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v1, v5, v1 | |
| ; GFX11-NEXT: v_add_f32_e32 v4, v4, v6 | |
| ; GFX11-NEXT: v_mul_f32_e32 v6, 0.5, v2 | |
| ; GFX11-NEXT: s_xor_b32 s6, vcc_lo, exec_lo | |
| ; GFX11-NEXT: v_cmp_lg_f32_e64 s2, v8, v9 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_exp_f32_e32 v0, v4 | |
| ; GFX11-NEXT: v_trunc_f32_e32 v2, v6 | |
| ; GFX11-NEXT: v_trunc_f32_e32 v4, v3 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v2, v6 | |
| ; GFX11-NEXT: v_cmp_eq_f32_e64 s0, v4, v3 | |
| ; GFX11-NEXT: v_and_or_b32 v3, 0x7fffffff, v1, v10 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v0, v0, v11 | |
| ; GFX11-NEXT: s_and_b32 vcc_lo, vcc_lo, s1 | |
| ; GFX11-NEXT: s_and_b32 s1, s4, s6 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v7 | |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo | |
| ; GFX11-NEXT: s_and_b32 vcc_lo, s0, s2 | |
| ; GFX11-NEXT: s_xor_b32 s0, s0, exec_lo | |
| ; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo | |
| ; GFX11-NEXT: s_and_b32 s0, s5, s0 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0 | |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] | |
| %pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y) | |
| ret <2 x float> %pow | |
| } | |
| define half @v_pow_f16(half %x, half %y) { | |
| ; GFX6-LABEL: v_pow_f16: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2 | |
| ; GFX6-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1 | |
| ; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1 | |
| ; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v1, v1, v3 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f16: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX8-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX8-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX8-NEXT: v_ldexp_f32 v2, v2, v3 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1 | |
| ; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1 | |
| ; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f16: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX9-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX9-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX9-NEXT: v_ldexp_f32 v2, v2, v3 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1 | |
| ; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v1, -2 | |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX9-NEXT: v_and_or_b32 v1, v2, v1, v3 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f16: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v1 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| | |
| ; GFX10-NEXT: v_trunc_f32_e32 v5, v4 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX10-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v4, v2 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX10-NEXT: v_mov_b32_e32 v3, 0.5 | |
| ; GFX10-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX10-NEXT: v_fma_mix_f32 v1, v1, v3, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v6, v1 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, v2, v3 | |
| ; GFX10-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v6, v1 | |
| ; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v3 | |
| ; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v1, s4 | |
| ; GFX10-NEXT: s_xor_b32 s4, vcc_lo, exec_lo | |
| ; GFX10-NEXT: s_and_b32 s4, s6, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4 | |
| ; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-TRUE16-LABEL: v_pow_f16: | |
| ; GFX11-TRUE16: ; %bb.0: | |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v1.l | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v5, v4 | |
| ; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0 | |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v4, v2 | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mov_b32 v3, 0.5 | |
| ; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v3, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4 | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v1 | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, v3 | |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v6, v1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v3 | |
| ; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0 | |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, vcc_lo, exec_lo | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | |
| ; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s0 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 | |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-FAKE16-LABEL: v_pow_f16: | |
| ; GFX11-FAKE16: ; %bb.0: | |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v1 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v4 | |
| ; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s2, v0, 24 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0 | |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX11-FAKE16-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v4, v2 | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_mov_b32 v3, 0.5 | |
| ; GFX11-FAKE16-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v3, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4 | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v6, v1 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v2, v2, v3 | |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v6, v1 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v3 | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0 | |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, vcc_lo, exec_lo | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, s0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] | |
| %pow = call half @llvm.pow.f16(half %x, half %y) | |
| ret half %pow | |
| } | |
| define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) { | |
| ; GFX6-LABEL: v_pow_v2f16: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x800000 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v1 | |
| ; GFX6-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v4, |v2|, v4 | |
| ; GFX6-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0 | |
| ; GFX6-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX6-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX6-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX6-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v10 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5 | |
| ; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v5 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5 | |
| ; GFX6-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4 | |
| ; GFX6-NEXT: v_and_b32_e32 v10, 0x80000000, v2 | |
| ; GFX6-NEXT: v_or_b32_e32 v5, v5, v10 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: s_xor_b64 s[8:9], vcc, exec | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2 | |
| ; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1 | |
| ; GFX6-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v2, v2, v5 | |
| ; GFX6-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc | |
| ; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5] | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1 | |
| ; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1 | |
| ; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v1, v1, v5 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc | |
| ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4 | |
| ; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 | |
| ; GFX6-NEXT: v_bfe_u32 v1, v4, 0, 16 | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_v2f16: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x800000 | |
| ; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v1 | |
| ; GFX8-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX8-NEXT: v_ldexp_f32 v4, |v2|, v4 | |
| ; GFX8-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX8-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX8-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX8-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX8-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX8-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX8-NEXT: v_ldexp_f32 v4, v4, v10 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5 | |
| ; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v5 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5 | |
| ; GFX8-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4 | |
| ; GFX8-NEXT: v_and_b32_e32 v10, 0x80000000, v2 | |
| ; GFX8-NEXT: v_or_b32_e32 v5, v5, v10 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: s_xor_b64 s[8:9], vcc, exec | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX8-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9] | |
| ; GFX8-NEXT: v_sub_f32_e32 v2, v2, v5 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v2, v2, v5 | |
| ; GFX8-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5] | |
| ; GFX8-NEXT: v_ldexp_f32 v2, v2, v5 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1 | |
| ; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1 | |
| ; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v0 | |
| ; GFX8-NEXT: v_or_b32_e32 v1, v1, v5 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc | |
| ; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v4 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 16 | |
| ; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 | |
| ; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_v2f16: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x800000 | |
| ; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v1 | |
| ; GFX9-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX9-NEXT: v_ldexp_f32 v4, |v2|, v4 | |
| ; GFX9-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX9-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX9-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX9-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX9-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX9-NEXT: v_ldexp_f32 v4, v4, v10 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5 | |
| ; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v5 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v5, -2 | |
| ; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v2 | |
| ; GFX9-NEXT: v_and_or_b32 v10, v4, v5, v10 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: s_xor_b64 s[8:9], vcc, exec | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[4:5] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX9-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9] | |
| ; GFX9-NEXT: v_sub_f32_e32 v2, v2, v6 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v2, v2, v6 | |
| ; GFX9-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v9, vcc | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5] | |
| ; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, v2, v6 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v6, v1 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v1 | |
| ; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v6, v1 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v6, v1 | |
| ; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v0 | |
| ; GFX9-NEXT: v_and_or_b32 v1, v2, v5, v1 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc | |
| ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_pack_b32_f16 v0, v4, v0 | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_v2f16: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v1 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2| | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0| | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24 | |
| ; GFX10-NEXT: v_and_b32_e32 v14, 0x80000000, v0 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s9, v0, 24 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s5 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 5, v3 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3 | |
| ; GFX10-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX10-NEXT: v_log_f32_e32 v3, v3 | |
| ; GFX10-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX10-NEXT: v_sub_f32_e32 v3, v3, v5 | |
| ; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX10-NEXT: v_sub_f32_e32 v4, v4, v6 | |
| ; GFX10-NEXT: v_mov_b32_e32 v6, 0.5 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v7, v3 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX10-NEXT: v_fma_mix_f32 v10, v1, v6, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX10-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v6, v7 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v12, v1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 0xffffffc0, s4 | |
| ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v7 | |
| ; GFX10-NEXT: v_add_f32_e32 v3, v3, v8 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v8, v10 | |
| ; GFX10-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX10-NEXT: v_and_b32_e32 v9, 0x80000000, v2 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v2, v5 | |
| ; GFX10-NEXT: v_exp_f32_e32 v3, v3 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v8, v10 | |
| ; GFX10-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v12, v1 | |
| ; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v2, v5 | |
| ; GFX10-NEXT: s_xor_b32 s10, vcc_lo, exec_lo | |
| ; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4 | |
| ; GFX10-NEXT: s_xor_b32 s4, s5, exec_lo | |
| ; GFX10-NEXT: v_ldexp_f32 v0, v3, v11 | |
| ; GFX10-NEXT: s_and_b32 s4, s9, s4 | |
| ; GFX10-NEXT: v_ldexp_f32 v3, v4, v13 | |
| ; GFX10-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v9 | |
| ; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v14 | |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo | |
| ; GFX10-NEXT: s_and_b32 vcc_lo, s5, s6 | |
| ; GFX10-NEXT: s_and_b32 s5, s8, s10 | |
| ; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4 | |
| ; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1 | |
| ; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-TRUE16-LABEL: v_pow_v2f16: | |
| ; GFX11-TRUE16: ; %bb.0: | |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2| | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| | |
| ; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24 | |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0x80000000, v0 | |
| ; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3 | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3 | |
| ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, 0.5 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3 | |
| ; GFX11-TRUE16-NEXT: v_fma_mix_f32 v10, v1, v6, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5 | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.h | |
| ; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v7 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3 | |
| ; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v5, v4 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v1 | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4 | |
| ; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v12, v1 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 0xffffffc0, s0 | |
| ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v7 | |
| ; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v4, v4, v9 | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v10 | |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0x80000000, v2 | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v2, v5 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | |
| ; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3 | |
| ; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s0, v8, v10 | |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s6, vcc_lo, exec_lo | |
| ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v2, v5 | |
| ; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, vcc_lo, s0 | |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, s1, exec_lo | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v3, v11 | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, v13 | |
| ; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v9 | |
| ; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v3, v14 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo | |
| ; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s1, s2 | |
| ; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s1 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 | |
| ; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1 | |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-FAKE16-LABEL: v_pow_v2f16: | |
| ; GFX11-FAKE16: ; %bb.0: | |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v1 | |
| ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0.5 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2| | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0x80000000, v2 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_fma_mix_f32 v9, v1, v8, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 | |
| ; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3 | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v5 | |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1 | |
| ; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v9 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v6, v3 | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v5 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v1 | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v5, v4 | |
| ; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v12, v1 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v7 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, s0 | |
| ; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v7 | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v6 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, s0 | |
| ; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v8, v9 | |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0x80000000, v0 | |
| ; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3 | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v5 | |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s4, vcc_lo, exec_lo | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6 | |
| ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v7, v5 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v10 | |
| ; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1 | |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s1, s2, exec_lo | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_and_or_b32 v9, 0x7fffffff, v3, v11 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, v9, s0 | |
| ; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v4, v8 | |
| ; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc_lo | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, s4 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0 | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s1 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1 | |
| ; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0 | |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] | |
| %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y) | |
| ret <2 x half> %pow | |
| } | |
| define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) { | |
| ; GFX6-LABEL: v_pow_v2f16_fneg_lhs: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x800000 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v1 | |
| ; GFX6-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v4, |v2|, v4 | |
| ; GFX6-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0 | |
| ; GFX6-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX6-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX6-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX6-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v10 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5 | |
| ; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v5 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5 | |
| ; GFX6-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4 | |
| ; GFX6-NEXT: v_and_b32_e32 v10, 0x80000000, v2 | |
| ; GFX6-NEXT: v_or_b32_e32 v5, v5, v10 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: s_xor_b64 s[8:9], vcc, exec | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2 | |
| ; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1 | |
| ; GFX6-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v2, v2, v5 | |
| ; GFX6-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc | |
| ; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5] | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1 | |
| ; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1 | |
| ; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v1, v1, v5 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc | |
| ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4 | |
| ; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 | |
| ; GFX6-NEXT: v_bfe_u32 v1, v4, 0, 16 | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_v2f16_fneg_lhs: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 | |
| ; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x800000 | |
| ; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v1 | |
| ; GFX8-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX8-NEXT: v_ldexp_f32 v4, |v2|, v4 | |
| ; GFX8-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX8-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX8-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX8-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX8-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX8-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX8-NEXT: v_ldexp_f32 v4, v4, v10 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5 | |
| ; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v5 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5 | |
| ; GFX8-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4 | |
| ; GFX8-NEXT: v_and_b32_e32 v10, 0x80000000, v2 | |
| ; GFX8-NEXT: v_or_b32_e32 v5, v5, v10 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: s_xor_b64 s[8:9], vcc, exec | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX8-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9] | |
| ; GFX8-NEXT: v_sub_f32_e32 v2, v2, v5 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v2, v2, v5 | |
| ; GFX8-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5] | |
| ; GFX8-NEXT: v_ldexp_f32 v2, v2, v5 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1 | |
| ; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1 | |
| ; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v0 | |
| ; GFX8-NEXT: v_or_b32_e32 v1, v1, v5 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc | |
| ; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v4 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 16 | |
| ; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 | |
| ; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_v2f16_fneg_lhs: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 | |
| ; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x800000 | |
| ; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v1 | |
| ; GFX9-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX9-NEXT: v_ldexp_f32 v4, |v2|, v4 | |
| ; GFX9-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX9-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX9-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX9-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX9-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX9-NEXT: v_ldexp_f32 v4, v4, v10 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5 | |
| ; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v5 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v5, -2 | |
| ; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v2 | |
| ; GFX9-NEXT: v_and_or_b32 v10, v4, v5, v10 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: s_xor_b64 s[8:9], vcc, exec | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[4:5] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX9-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9] | |
| ; GFX9-NEXT: v_sub_f32_e32 v2, v2, v6 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v2, v2, v6 | |
| ; GFX9-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v9, vcc | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5] | |
| ; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, v2, v6 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v6, v1 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v1 | |
| ; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v6, v1 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v6, v1 | |
| ; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v0 | |
| ; GFX9-NEXT: v_and_or_b32 v1, v2, v5, v1 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc | |
| ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_pack_b32_f16 v0, v4, v0 | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_v2f16_fneg_lhs: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 | |
| ; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v1 | |
| ; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2| | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0| | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s9, v0, 24 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s5 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 5, v3 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3 | |
| ; GFX10-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX10-NEXT: v_log_f32_e32 v3, v3 | |
| ; GFX10-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX10-NEXT: v_sub_f32_e32 v3, v3, v5 | |
| ; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX10-NEXT: v_sub_f32_e32 v4, v4, v6 | |
| ; GFX10-NEXT: v_mov_b32_e32 v6, 0.5 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v7, v3 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX10-NEXT: v_fma_mix_f32 v10, v1, v6, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX10-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v6, v7 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v11, v1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v6, v7 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s4 | |
| ; GFX10-NEXT: v_add_f32_e32 v3, v3, v8 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v8, v10 | |
| ; GFX10-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v9, v5 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s6, v11, v1 | |
| ; GFX10-NEXT: v_exp_f32_e32 v3, v3 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v8, v10 | |
| ; GFX10-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX10-NEXT: v_and_b32_e32 v8, 0x80000000, v2 | |
| ; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v9, v5 | |
| ; GFX10-NEXT: s_xor_b32 s10, s5, exec_lo | |
| ; GFX10-NEXT: s_and_b32 vcc_lo, s5, vcc_lo | |
| ; GFX10-NEXT: s_and_b32 s5, s8, s10 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, v3, v6 | |
| ; GFX10-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX10-NEXT: v_ldexp_f32 v4, v4, v7 | |
| ; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v8 | |
| ; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v4, v3 | |
| ; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo | |
| ; GFX10-NEXT: s_and_b32 vcc_lo, s4, s6 | |
| ; GFX10-NEXT: s_xor_b32 s4, s4, exec_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo | |
| ; GFX10-NEXT: s_and_b32 s4, s9, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4 | |
| ; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1 | |
| ; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_pack_b32_f16 v0, v1, v0 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_lhs: | |
| ; GFX11-TRUE16: ; %bb.0: | |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2| | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| | |
| ; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24 | |
| ; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v6 :: v_dual_lshlrev_b32 v3, 5, v3 | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3 | |
| ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, 0.5 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3 | |
| ; GFX11-TRUE16-NEXT: v_fma_mix_f32 v10, v1, v6, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v5 | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.h | |
| ; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v6, v7 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3 | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v11, v1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, v6, v7 | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s2, v11, v1 | |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s6, s1, exec_lo | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v8 | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v8, v10 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3 | |
| ; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v8, v10 | |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0x80000000, v2 | |
| ; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s1, vcc_lo | |
| ; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6 | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v6 | |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v8 | |
| ; GFX11-TRUE16-NEXT: v_dual_mul_dx9_zero_f32 v4, v5, v4 :: v_dual_cndmask_b32 v1, v2, v1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0 | |
| ; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v5 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v9, v5 | |
| ; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s0, s2 | |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, exec_lo | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0 | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, v7 | |
| ; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x7fffffff, v4, v3 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0 | |
| ; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2 | |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_lhs: | |
| ; GFX11-FAKE16: ; %bb.0: | |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v1 | |
| ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0.5 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 | |
| ; GFX11-FAKE16-NEXT: v_fma_mix_f32 v9, v1, v8, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2| | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0 | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 | |
| ; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1 | |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3 | |
| ; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v5 | |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1 | |
| ; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v8, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v9 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v6, v3 | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v5 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v1 | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v5, v4 | |
| ; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v11, v1 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, vcc_lo | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v7 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42800000, s0 | |
| ; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v7 | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v6 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6 | |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0x80000000, v2 | |
| ; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0 | |
| ; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v8, v9 | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v5 | |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0x80000000, v0 | |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s4, vcc_lo, exec_lo | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v7 | |
| ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v8, v5 | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v10 | |
| ; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1 | |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s1, s2, exec_lo | |
| ; GFX11-FAKE16-NEXT: v_and_or_b32 v6, 0x7fffffff, v3, v6 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, v6, s0 | |
| ; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v4, v9 | |
| ; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc_lo | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, s4 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0 | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s1 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1 | |
| ; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0 | |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] | |
| %x.fneg = fneg <2 x half> %x | |
| %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y) | |
| ret <2 x half> %pow | |
| } | |
| define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) { | |
| ; GFX6-LABEL: v_pow_v2f16_fneg_rhs: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x800000 | |
| ; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v1 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v4, |v2|, v4 | |
| ; GFX6-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX6-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX6-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX6-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX6-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v10 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5 | |
| ; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v5 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5 | |
| ; GFX6-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4 | |
| ; GFX6-NEXT: v_and_b32_e32 v10, 0x80000000, v2 | |
| ; GFX6-NEXT: v_or_b32_e32 v5, v5, v10 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: s_xor_b64 s[8:9], vcc, exec | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2 | |
| ; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1 | |
| ; GFX6-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v2, v2, v5 | |
| ; GFX6-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc | |
| ; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5] | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1 | |
| ; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1 | |
| ; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v1, v1, v5 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc | |
| ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4 | |
| ; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 | |
| ; GFX6-NEXT: v_bfe_u32 v1, v4, 0, 16 | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_v2f16_fneg_rhs: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x800000 | |
| ; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 | |
| ; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v1 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX8-NEXT: v_ldexp_f32 v4, |v2|, v4 | |
| ; GFX8-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX8-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX8-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX8-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX8-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX8-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX8-NEXT: v_ldexp_f32 v4, v4, v10 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5 | |
| ; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v5 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5 | |
| ; GFX8-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4 | |
| ; GFX8-NEXT: v_and_b32_e32 v10, 0x80000000, v2 | |
| ; GFX8-NEXT: v_or_b32_e32 v5, v5, v10 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: s_xor_b64 s[8:9], vcc, exec | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX8-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v2, v2, v5 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v2, v2, v5 | |
| ; GFX8-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc | |
| ; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9] | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5] | |
| ; GFX8-NEXT: v_ldexp_f32 v2, v2, v5 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1 | |
| ; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1 | |
| ; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v0 | |
| ; GFX8-NEXT: v_or_b32_e32 v1, v1, v5 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc | |
| ; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v4 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 16 | |
| ; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 | |
| ; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_v2f16_fneg_rhs: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x800000 | |
| ; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 | |
| ; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v1 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX9-NEXT: v_ldexp_f32 v4, |v2|, v4 | |
| ; GFX9-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX9-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX9-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX9-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX9-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX9-NEXT: v_ldexp_f32 v4, v4, v10 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5 | |
| ; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v5 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v5, -2 | |
| ; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v2 | |
| ; GFX9-NEXT: v_and_or_b32 v10, v4, v5, v10 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: s_xor_b64 s[8:9], vcc, exec | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[4:5] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX9-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v2, v2, v6 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v2, v2, v6 | |
| ; GFX9-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v9, vcc | |
| ; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9] | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5] | |
| ; GFX9-NEXT: v_ldexp_f32 v2, v2, v6 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v6, v1 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v1 | |
| ; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v6, v1 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v6, v1 | |
| ; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v0 | |
| ; GFX9-NEXT: v_and_or_b32 v1, v2, v5, v1 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc | |
| ; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4 | |
| ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_pack_b32_f16 v0, v4, v0 | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_v2f16_fneg_rhs: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX10-NEXT: v_xor_b32_e32 v5, 0x80008000, v1 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2| | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0| | |
| ; GFX10-NEXT: v_cvt_f32_f16_e32 v8, v5 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s9, v0, 24 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s5 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 5, v3 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3 | |
| ; GFX10-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX10-NEXT: v_log_f32_e32 v3, v3 | |
| ; GFX10-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6 | |
| ; GFX10-NEXT: v_cvt_f32_f16_sdwa v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX10-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX10-NEXT: v_mov_b32_e32 v7, 0.5 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v8, v3 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v13, v6 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4 | |
| ; GFX10-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] | |
| ; GFX10-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3 | |
| ; GFX10-NEXT: v_and_b32_e32 v7, 0x80000000, v2 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4 | |
| ; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v13, v6 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v12, v5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, s4 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v12, v5 | |
| ; GFX10-NEXT: v_add_f32_e32 v3, v3, v9 | |
| ; GFX10-NEXT: v_and_b32_e32 v9, 0x80000000, v0 | |
| ; GFX10-NEXT: v_add_f32_e32 v4, v4, v10 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_trunc_f32_e32 v10, v8 | |
| ; GFX10-NEXT: v_exp_f32_e32 v2, v3 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX10-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v10, v8 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v3, v1 | |
| ; GFX10-NEXT: s_xor_b32 s10, s4, exec_lo | |
| ; GFX10-NEXT: v_ldexp_f32 v0, v2, v0 | |
| ; GFX10-NEXT: s_and_b32 s4, s4, s5 | |
| ; GFX10-NEXT: v_ldexp_f32 v1, v4, v11 | |
| ; GFX10-NEXT: s_and_b32 vcc_lo, s6, vcc_lo | |
| ; GFX10-NEXT: s_and_b32 s5, s8, s10 | |
| ; GFX10-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v7 | |
| ; GFX10-NEXT: v_and_or_b32 v3, 0x7fffffff, v1, v9 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s4 | |
| ; GFX10-NEXT: s_xor_b32 s4, s6, exec_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo | |
| ; GFX10-NEXT: s_and_b32 s4, s9, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s4 | |
| ; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1 | |
| ; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_rhs: | |
| ; GFX11-TRUE16: ; %bb.0: | |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h | |
| ; GFX11-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2| | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v5.l | |
| ; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24 | |
| ; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v7 :: v_dual_mov_b32 v7, 0.5 | |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3 | |
| ; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3 | |
| ; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3 | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v6 | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v5.h | |
| ; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0x80000000, v2 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v8, v3 | |
| ; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v5 | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v13, v6 | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4 | |
| ; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v12, v5 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) | |
| ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v13, v6 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 0xffffffc0, s0 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) | |
| ; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v9 :: v_dual_add_f32 v4, v4, v10 | |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0x80000000, v0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v8 | |
| ; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v3 | |
| ; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v10, v8 | |
| ; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v3, v1 | |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s6, s0, exec_lo | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v2, v0 | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v4, v11 | |
| ; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1 | |
| ; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo | |
| ; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6 | |
| ; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x7fffffff, v0, v7 | |
| ; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v1, v9 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo | |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, s2, exec_lo | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0 | |
| ; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1 | |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_rhs: | |
| ; GFX11-FAKE16: ; %bb.0: | |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 | |
| ; GFX11-FAKE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1 | |
| ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0.5 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2| | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v5 | |
| ; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v9, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0 | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v7 | |
| ; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42000000, s1 | |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_dual_sub_f32 v4, v4, v8 :: v_dual_lshlrev_b32 v3, 5, v3 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3 | |
| ; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v6 | |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5 | |
| ; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v9, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v1 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3 | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v6 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v12, v5 | |
| ; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v9, v1 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3 | |
| ; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v11, v7 | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v7, v6 | |
| ; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v8 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, s0 | |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s4, vcc_lo, exec_lo | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v7, v6 | |
| ; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v8 | |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0x80000000, v2 | |
| ; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v10 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, s0 | |
| ; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v12, v5 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_and_or_b32 v5, 0x7fffffff, v3, v8 | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v10 | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0 | |
| ; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1 | |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0x80000000, v0 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, v5, s0 | |
| ; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24 | |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s1, s2, exec_lo | |
| ; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v4, v13 | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, s4 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc_lo | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s1 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0 | |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] | |
| %y.fneg = fneg <2 x half> %y | |
| %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y.fneg) | |
| ret <2 x half> %pow | |
| } | |
| define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) { | |
| ; GFX6-LABEL: v_pow_v2f16_fneg_lhs_rhs: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x800000 | |
| ; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v5, v1 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v4, |v2|, v4 | |
| ; GFX6-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX6-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX6-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX6-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX6-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v4, v4, v10 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5 | |
| ; GFX6-NEXT: v_mul_f32_e32 v5, 0.5, v5 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5 | |
| ; GFX6-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4 | |
| ; GFX6-NEXT: v_and_b32_e32 v10, 0x80000000, v2 | |
| ; GFX6-NEXT: v_or_b32_e32 v5, v5, v10 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: s_xor_b64 s[8:9], vcc, exec | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2 | |
| ; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1 | |
| ; GFX6-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fc00000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v2, v2, v5 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v2, v2, v5 | |
| ; GFX6-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc | |
| ; GFX6-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5] | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v5 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1 | |
| ; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1 | |
| ; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX6-NEXT: v_and_b32_e32 v5, 0x80000000, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v1, v1, v5 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc | |
| ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_cvt_f16_f32_e32 v4, v4 | |
| ; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 | |
| ; GFX6-NEXT: v_bfe_u32 v1, v4, 0, 16 | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_v2f16_fneg_lhs_rhs: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 | |
| ; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x800000 | |
| ; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 | |
| ; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v1 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX8-NEXT: v_ldexp_f32 v4, |v2|, v4 | |
| ; GFX8-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX8-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX8-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX8-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX8-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX8-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX8-NEXT: v_ldexp_f32 v4, v4, v10 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5 | |
| ; GFX8-NEXT: v_mul_f32_e32 v5, 0.5, v5 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5 | |
| ; GFX8-NEXT: v_and_b32_e32 v5, 0x7fffffff, v4 | |
| ; GFX8-NEXT: v_and_b32_e32 v10, 0x80000000, v2 | |
| ; GFX8-NEXT: v_or_b32_e32 v5, v5, v10 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: s_xor_b64 s[8:9], vcc, exec | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX8-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v6, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x7fc00000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v2, v2, v5 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v2, v2, v5 | |
| ; GFX8-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc | |
| ; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9] | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5] | |
| ; GFX8-NEXT: v_ldexp_f32 v2, v2, v5 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v5, v1 | |
| ; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v1 | |
| ; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX8-NEXT: v_and_b32_e32 v5, 0x80000000, v0 | |
| ; GFX8-NEXT: v_or_b32_e32 v1, v1, v5 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc | |
| ; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v4 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 16 | |
| ; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 | |
| ; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_v2f16_fneg_lhs_rhs: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 | |
| ; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x800000 | |
| ; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 | |
| ; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v1 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX9-NEXT: v_ldexp_f32 v4, |v2|, v4 | |
| ; GFX9-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX9-NEXT: v_mov_b32_e32 v6, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v8, 0x42800000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v4, v5, v4 | |
| ; GFX9-NEXT: v_mov_b32_e32 v7, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v4, v7 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v8, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v4, v4, v9 | |
| ; GFX9-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX9-NEXT: v_not_b32_e32 v9, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v9, vcc | |
| ; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX9-NEXT: v_ldexp_f32 v4, v4, v10 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v10, v5 | |
| ; GFX9-NEXT: v_mul_f32_e32 v5, 0.5, v5 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v10, v5 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v5, -2 | |
| ; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v2 | |
| ; GFX9-NEXT: v_and_or_b32 v10, v4, v5, v10 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: s_xor_b64 s[8:9], vcc, exec | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[4:5] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v2, 24 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX9-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v2, v2, v6 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v7 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v2, v2, v6 | |
| ; GFX9-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v9, vcc | |
| ; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9] | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[4:5] | |
| ; GFX9-NEXT: v_ldexp_f32 v2, v2, v6 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v6, v1 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v1 | |
| ; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v6, v1 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v6, v1 | |
| ; GFX9-NEXT: v_and_b32_e32 v1, 0x80000000, v0 | |
| ; GFX9-NEXT: v_and_or_b32 v1, v2, v5, v1 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 24 | |
| ; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc | |
| ; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4 | |
| ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_pack_b32_f16 v0, v4, v0 | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_v2f16_fneg_lhs_rhs: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 | |
| ; GFX10-NEXT: v_xor_b32_e32 v5, 0x80008000, v1 | |
| ; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX10-NEXT: v_cvt_f32_f16_e32 v8, v5 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v2| | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0| | |
| ; GFX10-NEXT: v_and_b32_e32 v11, 0x80000000, v2 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s8, v2, 24 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s9, v0, 24 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s5 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 5, v3 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX10-NEXT: v_ldexp_f32 v3, |v2|, v3 | |
| ; GFX10-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX10-NEXT: v_log_f32_e32 v3, v3 | |
| ; GFX10-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX10-NEXT: v_sub_f32_e32 v3, v3, v6 | |
| ; GFX10-NEXT: v_cvt_f32_f16_sdwa v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 | |
| ; GFX10-NEXT: v_sub_f32_e32 v4, v4, v7 | |
| ; GFX10-NEXT: v_mov_b32_e32 v7, 0.5 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v3, v8, v3 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v12, v6 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v4, v6, v4 | |
| ; GFX10-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] | |
| ; GFX10-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3 | |
| ; GFX10-NEXT: v_cmp_eq_f32_e64 s6, v12, v6 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v4 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v7, v1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 0xffffffc0, s4 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v1 | |
| ; GFX10-NEXT: v_add_f32_e32 v3, v3, v9 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v9, v8 | |
| ; GFX10-NEXT: v_add_f32_e32 v4, v4, v10 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX10-NEXT: v_and_b32_e32 v1, 0x80000000, v0 | |
| ; GFX10-NEXT: v_exp_f32_e32 v3, v3 | |
| ; GFX10-NEXT: v_cmp_eq_f32_e64 s4, v9, v8 | |
| ; GFX10-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s5, v10, v5 | |
| ; GFX10-NEXT: s_and_b32 vcc_lo, s6, vcc_lo | |
| ; GFX10-NEXT: s_xor_b32 s10, s4, exec_lo | |
| ; GFX10-NEXT: s_and_b32 s4, s4, s5 | |
| ; GFX10-NEXT: s_and_b32 s5, s8, s10 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, v3, v2 | |
| ; GFX10-NEXT: v_ldexp_f32 v0, v4, v13 | |
| ; GFX10-NEXT: v_and_or_b32 v3, 0x7fffffff, v2, v11 | |
| ; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, v1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v3, s4 | |
| ; GFX10-NEXT: s_xor_b32 s4, s6, exec_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo | |
| ; GFX10-NEXT: s_and_b32 s4, s9, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4 | |
| ; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1 | |
| ; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_pack_b32_f16 v0, v1, v0 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_lhs_rhs: | |
| ; GFX11-TRUE16: ; %bb.0: | |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 | |
| ; GFX11-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v5.l | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2| | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| | |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0x80000000, v2 | |
| ; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s4, v2, 24 | |
| ; GFX11-TRUE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s1 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_dual_sub_f32 v4, v4, v7 :: v_dual_mov_b32 v7, 0.5 | |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 5, v3 | |
| ; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, -v1, v7, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, |v2|, v3 | |
| ; GFX11-TRUE16-NEXT: v_log_f32_e32 v3, v3 | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v6 | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v5.h | |
| ; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, v5, v7, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v7, v1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v8, v3 | |
| ; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4 | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v12, v6 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3 | |
| ; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) | |
| ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, v12, v6 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 0x42800000, vcc_lo | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 0x42800000, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 0xffffffc0, s0 | |
| ; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v7, v1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) | |
| ; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, v3, v9 :: v_dual_add_f32 v4, v4, v10 | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v9, v8 | |
| ; GFX11-TRUE16-NEXT: v_trunc_f32_e32 v10, v5 | |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x80000000, v0 | |
| ; GFX11-TRUE16-NEXT: v_exp_f32_e32 v3, v3 | |
| ; GFX11-TRUE16-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, v9, v8 | |
| ; GFX11-TRUE16-NEXT: v_cmp_lg_f32_e64 s1, v10, v5 | |
| ; GFX11-TRUE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo | |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s6, s0, exec_lo | |
| ; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1 | |
| ; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s6 | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2 | |
| ; GFX11-TRUE16-NEXT: v_ldexp_f32 v0, v4, v13 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v2, v11 | |
| ; GFX11-TRUE16-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, v1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, v3, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo | |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, s2, exec_lo | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: s_and_b32 s0, s5, s0 | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v2, 0x7fc00000, s1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, 0x7fc00000, s0 | |
| ; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1 | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2 | |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_lhs_rhs: | |
| ; GFX11-FAKE16: ; %bb.0: | |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 | |
| ; GFX11-FAKE16-NEXT: v_xor_b32_e32 v5, 0x80008000, v1 | |
| ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0.5 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0 | |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v5 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_fma_mix_f32 v1, -v1, v9, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v2| | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0x80000000, v2 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s0 | |
| ; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s5, v0, 24 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42000000, s1 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v4 | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, |v0|, v4 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_log_f32_e32 v4, v4 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_dual_sub_f32 v4, v4, v8 :: v_dual_lshlrev_b32 v3, 5, v3 | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, |v2|, v3 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_log_f32_e32 v3, v3 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_sub_f32_e32 v3, v3, v6 | |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5 | |
| ; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, v5, v9, neg(0) op_sel_hi:[1,0,0] | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v9, v7 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v3, v7, v3 | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v6 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v11, v5 | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v3 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v4, v6, v4 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, vcc_lo | |
| ; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v4 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v7 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) | |
| ; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v8 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 0x42800000, s0 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v7, 0, 0xffffffc0, s0 | |
| ; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s0, v11, v5 | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v5, v6 | |
| ; GFX11-FAKE16-NEXT: v_exp_f32_e32 v3, v3 | |
| ; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, v4, v8 | |
| ; GFX11-FAKE16-NEXT: v_trunc_f32_e32 v8, v1 | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0 | |
| ; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e64 s2, v5, v6 | |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s4, vcc_lo, exec_lo | |
| ; GFX11-FAKE16-NEXT: v_exp_f32_e32 v4, v4 | |
| ; GFX11-FAKE16-NEXT: v_cmp_lg_f32_e64 s1, v8, v1 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, v10 | |
| ; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s1 | |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s1, s2, exec_lo | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) | |
| ; GFX11-FAKE16-NEXT: v_and_or_b32 v10, 0x7fffffff, v3, v12 | |
| ; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v7 | |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0x80000000, v0 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, v10, s0 | |
| ; GFX11-FAKE16-NEXT: v_cmp_class_f32_e64 s0, v2, 24 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0x7fffffff, v4, v9 | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, s4 | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc_lo | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, 0x7fc00000, s0 | |
| ; GFX11-FAKE16-NEXT: s_and_b32 s0, s5, s1 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) | |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1 | |
| ; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0 | |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] | |
| %x.fneg = fneg <2 x half> %x | |
| %y.fneg = fneg <2 x half> %y | |
| %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y.fneg) | |
| ret <2 x half> %pow | |
| } | |
| ; FIXME | |
| ; define double @v_pow_f64(double %x, double %y) { | |
| ; %pow = call double @llvm.pow.f64(double %x, double %y) | |
| ; ret double %pow | |
| ; } | |
| define float @v_pow_f32_fabs_lhs(float %x, float %y) { | |
| ; GFX6-LABEL: v_pow_f32_fabs_lhs: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v2 | |
| ; GFX6-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX6-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_not_b32_e32 v1, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_fabs_lhs: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v2 | |
| ; GFX8-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX8-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_not_b32_e32 v1, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc | |
| ; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_fabs_lhs: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v2 | |
| ; GFX9-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX9-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_not_b32_e32 v1, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc | |
| ; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_fabs_lhs: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v2 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_fabs_lhs: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 | |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v2 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0 | |
| ; GFX11-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 | |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] | |
| %fabs.x = call float @llvm.fabs.f32(float %x) | |
| %pow = call float @llvm.pow.f32(float %fabs.x, float %y) | |
| ret float %pow | |
| } | |
| define float @v_pow_f32_fabs_rhs(float %x, float %y) { | |
| ; GFX6-LABEL: v_pow_f32_fabs_rhs: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2 | |
| ; GFX6-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24 | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_trunc_f32_e64 v3, |v1| | |
| ; GFX6-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, |v1| | |
| ; GFX6-NEXT: v_mul_f32_e64 v1, |v1|, 0.5 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1 | |
| ; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v1, v1, v3 | |
| ; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc | |
| ; GFX6-NEXT: s_xor_b64 s[4:5], s[6:7], exec | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX6-NEXT: s_and_b64 vcc, s[8:9], s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_fabs_rhs: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX8-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX8-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, v2, v3 | |
| ; GFX8-NEXT: v_trunc_f32_e64 v3, |v1| | |
| ; GFX8-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, |v1| | |
| ; GFX8-NEXT: v_mul_f32_e64 v1, |v1|, 0.5 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1 | |
| ; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 | |
| ; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc | |
| ; GFX8-NEXT: s_xor_b64 s[4:5], s[6:7], exec | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX8-NEXT: s_and_b64 vcc, s[8:9], s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_fabs_rhs: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX9-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX9-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, v2, v3 | |
| ; GFX9-NEXT: v_trunc_f32_e64 v3, |v1| | |
| ; GFX9-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, |v1| | |
| ; GFX9-NEXT: v_mul_f32_e64 v1, |v1|, 0.5 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v1, -2 | |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX9-NEXT: v_and_or_b32 v1, v2, v1, v3 | |
| ; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc | |
| ; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], exec | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX9-NEXT: s_and_b64 vcc, s[8:9], s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_fabs_rhs: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0| | |
| ; GFX10-NEXT: v_trunc_f32_e64 v5, |v1| | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s5 | |
| ; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v5, |v1| | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX10-NEXT: s_xor_b32 s4, s5, exec_lo | |
| ; GFX10-NEXT: s_and_b32 s4, s6, s4 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX10-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e64 v2, |v1|, v2 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX10-NEXT: v_mul_f32_e64 v3, |v1|, 0.5 | |
| ; GFX10-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v6, v3 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v3 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, v2, v4 | |
| ; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v0 | |
| ; GFX10-NEXT: s_and_b32 vcc_lo, s5, vcc_lo | |
| ; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4 | |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_fabs_rhs: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| | |
| ; GFX11-NEXT: v_trunc_f32_e64 v5, |v1| | |
| ; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 24 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s1 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s1 | |
| ; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v5, |v1| | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) | |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX11-NEXT: s_xor_b32 s0, s1, exec_lo | |
| ; GFX11-NEXT: s_and_b32 s0, s2, s0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX11-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v2, |v1|, v2 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX11-NEXT: v_mul_f32_e64 v3, |v1|, 0.5 | |
| ; GFX11-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_trunc_f32_e32 v6, v3 | |
| ; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v3 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v2, v2, v4 | |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v0 | |
| ; GFX11-NEXT: s_and_b32 vcc_lo, s1, vcc_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4 | |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] | |
| %fabs.y = call float @llvm.fabs.f32(float %y) | |
| %pow = call float @llvm.pow.f32(float %x, float %fabs.y) | |
| ret float %pow | |
| } | |
| define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) { | |
| ; GFX6-LABEL: v_pow_f32_fabs_lhs_rhs: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v2 | |
| ; GFX6-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX6-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_not_b32_e32 v1, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v2 | |
| ; GFX8-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX8-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_not_b32_e32 v1, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc | |
| ; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v2 | |
| ; GFX9-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX9-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_not_b32_e32 v1, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc | |
| ; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v2 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_fabs_lhs_rhs: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 | |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v2 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0 | |
| ; GFX11-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, |v1|, v0 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 | |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] | |
| %fabs.x = call float @llvm.fabs.f32(float %x) | |
| %fabs.y = call float @llvm.fabs.f32(float %y) | |
| %pow = call float @llvm.pow.f32(float %fabs.x, float %fabs.y) | |
| ret float %pow | |
| } | |
| define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) { | |
| ; GFX6-LABEL: v_pow_f32_sgpr_vgpr: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[2:3], |s0|, v1 | |
| ; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] | |
| ; GFX6-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX6-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX6-NEXT: s_lshl_b32 s2, s2, 5 | |
| ; GFX6-NEXT: v_mov_b32_e32 v1, s2 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v1, |s0|, v1 | |
| ; GFX6-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX6-NEXT: s_cselect_b32 s1, 0x42000000, 0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 | |
| ; GFX6-NEXT: v_subrev_f32_e32 v1, s1, v1 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v0, v1 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX6-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX6-NEXT: v_not_b32_e32 v2, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX6-NEXT: s_and_b32 s1, s0, 0x80000000 | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v2, v0 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v2, v0 | |
| ; GFX6-NEXT: v_mul_f32_e32 v0, 0.5, v0 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v2, v0 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[2:3], v2, v0 | |
| ; GFX6-NEXT: v_and_b32_e32 v0, 0x7fffffff, v1 | |
| ; GFX6-NEXT: v_or_b32_e32 v0, s1, v0 | |
| ; GFX6-NEXT: s_and_b64 s[2:3], vcc, s[2:3] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24 | |
| ; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[2:3] | |
| ; GFX6-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX6-NEXT: s_xor_b64 s[0:1], vcc, exec | |
| ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 | |
| ; GFX6-NEXT: s_cselect_b64 s[2:3], exec, 0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v1, 0x7fc00000 | |
| ; GFX6-NEXT: s_and_b64 vcc, s[2:3], s[0:1] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc | |
| ; GFX6-NEXT: ; return to shader part epilog | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_sgpr_vgpr: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 s[2:3], |s0|, v1 | |
| ; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0 | |
| ; GFX8-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX8-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX8-NEXT: s_lshl_b32 s2, s2, 5 | |
| ; GFX8-NEXT: v_mov_b32_e32 v1, s2 | |
| ; GFX8-NEXT: v_ldexp_f32 v1, |s0|, v1 | |
| ; GFX8-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX8-NEXT: s_cselect_b32 s1, 0x42000000, 0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 | |
| ; GFX8-NEXT: v_subrev_f32_e32 v1, s1, v1 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v0, v1 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX8-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX8-NEXT: v_not_b32_e32 v2, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX8-NEXT: s_and_b32 s1, s0, 0x80000000 | |
| ; GFX8-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v2, v0 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v2, v0 | |
| ; GFX8-NEXT: v_mul_f32_e32 v0, 0.5, v0 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v2, v0 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[2:3], v2, v0 | |
| ; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v1 | |
| ; GFX8-NEXT: v_or_b32_e32 v0, s1, v0 | |
| ; GFX8-NEXT: s_and_b64 s[2:3], vcc, s[2:3] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24 | |
| ; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[2:3] | |
| ; GFX8-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX8-NEXT: s_xor_b64 s[0:1], vcc, exec | |
| ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 | |
| ; GFX8-NEXT: s_cselect_b64 s[2:3], exec, 0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v1, 0x7fc00000 | |
| ; GFX8-NEXT: s_and_b64 vcc, s[2:3], s[0:1] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc | |
| ; GFX8-NEXT: ; return to shader part epilog | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_sgpr_vgpr: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 s[2:3], |s0|, v1 | |
| ; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0 | |
| ; GFX9-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX9-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX9-NEXT: s_lshl_b32 s2, s2, 5 | |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s2 | |
| ; GFX9-NEXT: v_ldexp_f32 v1, |s0|, v1 | |
| ; GFX9-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX9-NEXT: s_cselect_b32 s1, 0x42000000, 0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 | |
| ; GFX9-NEXT: v_subrev_f32_e32 v1, s1, v1 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v0, v1 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX9-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX9-NEXT: v_not_b32_e32 v2, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX9-NEXT: s_and_b32 s1, s0, 0x80000000 | |
| ; GFX9-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v2, v0 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v2, v0 | |
| ; GFX9-NEXT: v_mul_f32_e32 v0, 0.5, v0 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v2, v0 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[2:3], v2, v0 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v0, -2 | |
| ; GFX9-NEXT: v_and_or_b32 v0, v1, v0, s1 | |
| ; GFX9-NEXT: s_and_b64 s[2:3], vcc, s[2:3] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24 | |
| ; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[2:3] | |
| ; GFX9-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX9-NEXT: s_xor_b64 s[0:1], vcc, exec | |
| ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 | |
| ; GFX9-NEXT: s_cselect_b64 s[2:3], exec, 0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0x7fc00000 | |
| ; GFX9-NEXT: s_and_b64 vcc, s[2:3], s[0:1] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc | |
| ; GFX9-NEXT: ; return to shader part epilog | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_sgpr_vgpr: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0| | |
| ; GFX10-NEXT: v_trunc_f32_e32 v3, v0 | |
| ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX10-NEXT: s_cselect_b32 s3, 1, 0 | |
| ; GFX10-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX10-NEXT: s_lshl_b32 s3, s3, 5 | |
| ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX10-NEXT: v_ldexp_f32 v1, |s0|, s3 | |
| ; GFX10-NEXT: s_cselect_b32 s1, 0x42000000, 0 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s3, s0, 24 | |
| ; GFX10-NEXT: s_and_b32 s0, s0, 0x80000000 | |
| ; GFX10-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX10-NEXT: v_subrev_f32_e32 v1, s1, v1 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v0, v1 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v0 | |
| ; GFX10-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX10-NEXT: v_mul_f32_e32 v2, 0.5, v0 | |
| ; GFX10-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v5, v2 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s1, v5, v2 | |
| ; GFX10-NEXT: v_ldexp_f32 v0, v1, v4 | |
| ; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, s0 | |
| ; GFX10-NEXT: s_and_b32 s0, vcc_lo, s1 | |
| ; GFX10-NEXT: s_cmp_lg_u32 s3, 0 | |
| ; GFX10-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX10-NEXT: s_xor_b32 s2, vcc_lo, exec_lo | |
| ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 | |
| ; GFX10-NEXT: s_cselect_b32 s0, exec_lo, 0 | |
| ; GFX10-NEXT: s_and_b32 s0, s0, s2 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX10-NEXT: ; return to shader part epilog | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_sgpr_vgpr: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0| | |
| ; GFX11-NEXT: v_trunc_f32_e32 v3, v0 | |
| ; GFX11-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX11-NEXT: s_cselect_b32 s3, 1, 0 | |
| ; GFX11-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX11-NEXT: s_lshl_b32 s3, s3, 5 | |
| ; GFX11-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX11-NEXT: v_ldexp_f32 v1, |s0|, s3 | |
| ; GFX11-NEXT: s_cselect_b32 s1, 0x42000000, 0 | |
| ; GFX11-NEXT: v_cmp_class_f32_e64 s3, s0, 24 | |
| ; GFX11-NEXT: s_and_b32 s0, s0, 0x80000000 | |
| ; GFX11-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_subrev_f32_e32 v1, s1, v1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, v0, v1 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX11-NEXT: v_mul_f32_e32 v2, 0.5, v0 | |
| ; GFX11-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_trunc_f32_e32 v5, v2 | |
| ; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v5, v2 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v0, v1, v4 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v0, s0 | |
| ; GFX11-NEXT: s_and_b32 s0, vcc_lo, s1 | |
| ; GFX11-NEXT: s_cmp_lg_u32 s3, 0 | |
| ; GFX11-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX11-NEXT: s_xor_b32 s2, vcc_lo, exec_lo | |
| ; GFX11-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 | |
| ; GFX11-NEXT: s_cselect_b32 s0, exec_lo, 0 | |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | |
| ; GFX11-NEXT: s_and_b32 s0, s0, s2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX11-NEXT: ; return to shader part epilog | |
| %pow = call float @llvm.pow.f32(float %x, float %y) | |
| ret float %pow | |
| } | |
| define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) { | |
| ; GFX6-LABEL: v_pow_f32_vgpr_sgpr: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v1, |v0|, v1 | |
| ; GFX6-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v1, s0, v1 | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX6-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX6-NEXT: v_not_b32_e32 v2, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v2, s0 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, s0, v2 | |
| ; GFX6-NEXT: v_mul_f32_e64 v2, s0, 0.5 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v3, v2 | |
| ; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc | |
| ; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2 | |
| ; GFX6-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc | |
| ; GFX6-NEXT: s_cselect_b32 s0, 1, 0 | |
| ; GFX6-NEXT: s_and_b32 s0, s2, s0 | |
| ; GFX6-NEXT: s_cmp_lg_u32 s0, 0 | |
| ; GFX6-NEXT: s_cselect_b64 vcc, exec, 0 | |
| ; GFX6-NEXT: s_xor_b32 s2, s2, 1 | |
| ; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v1 | |
| ; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 | |
| ; GFX6-NEXT: v_or_b32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[0:1], v0, 24 | |
| ; GFX6-NEXT: s_cselect_b64 s[2:3], exec, 0 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX6-NEXT: s_and_b64 vcc, s[0:1], s[2:3] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX6-NEXT: ; return to shader part epilog | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_vgpr_sgpr: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX8-NEXT: v_ldexp_f32 v1, |v0|, v1 | |
| ; GFX8-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v1, s0, v1 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX8-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX8-NEXT: v_not_b32_e32 v2, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX8-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v2, s0 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, s0, v2 | |
| ; GFX8-NEXT: v_mul_f32_e64 v2, s0, 0.5 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v3, v2 | |
| ; GFX8-NEXT: s_cmp_lg_u64 vcc, 0 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2 | |
| ; GFX8-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX8-NEXT: s_cmp_lg_u64 vcc, 0 | |
| ; GFX8-NEXT: s_cselect_b32 s0, 1, 0 | |
| ; GFX8-NEXT: s_and_b32 s0, s2, s0 | |
| ; GFX8-NEXT: s_cmp_lg_u32 s0, 0 | |
| ; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 | |
| ; GFX8-NEXT: s_xor_b32 s2, s2, 1 | |
| ; GFX8-NEXT: v_and_b32_e32 v2, 0x7fffffff, v1 | |
| ; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 | |
| ; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[0:1], v0, 24 | |
| ; GFX8-NEXT: s_cselect_b64 s[2:3], exec, 0 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX8-NEXT: s_and_b64 vcc, s[0:1], s[2:3] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX8-NEXT: ; return to shader part epilog | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_vgpr_sgpr: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX9-NEXT: v_ldexp_f32 v1, |v0|, v1 | |
| ; GFX9-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v1, s0, v1 | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX9-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX9-NEXT: v_not_b32_e32 v2, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX9-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v2, s0 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, s0, v2 | |
| ; GFX9-NEXT: v_mul_f32_e64 v2, s0, 0.5 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v3, v2 | |
| ; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v2 | |
| ; GFX9-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 | |
| ; GFX9-NEXT: s_cselect_b32 s0, 1, 0 | |
| ; GFX9-NEXT: s_and_b32 s0, s2, s0 | |
| ; GFX9-NEXT: s_cmp_lg_u32 s0, 0 | |
| ; GFX9-NEXT: s_cselect_b64 vcc, exec, 0 | |
| ; GFX9-NEXT: s_xor_b32 s2, s2, 1 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v2, -2 | |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 | |
| ; GFX9-NEXT: v_and_or_b32 v2, v1, v2, v3 | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[0:1], v0, 24 | |
| ; GFX9-NEXT: s_cselect_b64 s[2:3], exec, 0 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX9-NEXT: s_and_b64 vcc, s[0:1], s[2:3] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX9-NEXT: ; return to shader part epilog | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_vgpr_sgpr: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| | |
| ; GFX10-NEXT: v_mul_f32_e64 v3, s0, 0.5 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s2, v0, 24 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s1 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v4, v3 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s1, v4, v3 | |
| ; GFX10-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX10-NEXT: v_ldexp_f32 v1, |v0|, v1 | |
| ; GFX10-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX10-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v1, s0, v1 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v2, s0 | |
| ; GFX10-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX10-NEXT: v_cmp_eq_f32_e64 s0, s0, v2 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: s_cmp_lg_u32 s0, 0 | |
| ; GFX10-NEXT: s_cselect_b32 s0, 1, 0 | |
| ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX10-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX10-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX10-NEXT: s_and_b32 s1, s0, s1 | |
| ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v3 | |
| ; GFX10-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 | |
| ; GFX10-NEXT: s_xor_b32 s0, s0, 1 | |
| ; GFX10-NEXT: s_cmp_lg_u32 s0, 0 | |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo | |
| ; GFX10-NEXT: s_cselect_b32 s0, exec_lo, 0 | |
| ; GFX10-NEXT: s_and_b32 s0, s2, s0 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX10-NEXT: ; return to shader part epilog | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_vgpr_sgpr: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| | |
| ; GFX11-NEXT: v_mul_f32_e64 v3, s0, 0.5 | |
| ; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 24 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s1 | |
| ; GFX11-NEXT: v_trunc_f32_e32 v4, v3 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v4, v3 | |
| ; GFX11-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_ldexp_f32 v1, |v0|, v1 | |
| ; GFX11-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, s0, v1 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX11-NEXT: v_trunc_f32_e32 v2, s0 | |
| ; GFX11-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-NEXT: v_cmp_eq_f32_e64 s0, s0, v2 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-NEXT: s_cmp_lg_u32 s0, 0 | |
| ; GFX11-NEXT: s_cselect_b32 s0, 1, 0 | |
| ; GFX11-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX11-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) | |
| ; GFX11-NEXT: s_and_b32 s1, s0, s1 | |
| ; GFX11-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) | |
| ; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v3 | |
| ; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 | |
| ; GFX11-NEXT: s_xor_b32 s0, s0, 1 | |
| ; GFX11-NEXT: s_cmp_lg_u32 s0, 0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) | |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo | |
| ; GFX11-NEXT: s_cselect_b32 s0, exec_lo, 0 | |
| ; GFX11-NEXT: s_and_b32 s0, s2, s0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX11-NEXT: ; return to shader part epilog | |
| %pow = call float @llvm.pow.f32(float %x, float %y) | |
| ret float %pow | |
| } | |
| define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) { | |
| ; GFX6-LABEL: v_pow_f32_sgpr_sgpr: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: v_mov_b32_e32 v0, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[2:3], |s0|, v0 | |
| ; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3] | |
| ; GFX6-NEXT: s_cselect_b32 s3, 1, 0 | |
| ; GFX6-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX6-NEXT: s_lshl_b32 s3, s3, 5 | |
| ; GFX6-NEXT: v_mov_b32_e32 v0, s3 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v0, |s0|, v0 | |
| ; GFX6-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 | |
| ; GFX6-NEXT: s_cselect_b32 s2, 0x42000000, 0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 | |
| ; GFX6-NEXT: v_subrev_f32_e32 v0, s2, v0 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 | |
| ; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc | |
| ; GFX6-NEXT: s_cselect_b32 s2, 0x42800000, 0 | |
| ; GFX6-NEXT: v_add_f32_e32 v0, s2, v0 | |
| ; GFX6-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX6-NEXT: s_cselect_b32 s2, 0xffffffc0, 0 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s2 | |
| ; GFX6-NEXT: v_readfirstlane_b32 s4, v0 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v0, s1 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, s1, v0 | |
| ; GFX6-NEXT: v_mul_f32_e64 v0, s1, 0.5 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v1, v0 | |
| ; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc | |
| ; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v1, v0 | |
| ; GFX6-NEXT: s_cselect_b32 s5, 1, 0 | |
| ; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc | |
| ; GFX6-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX6-NEXT: s_and_b32 s2, s4, 0x7fffffff | |
| ; GFX6-NEXT: s_and_b32 s3, s0, 0x80000000 | |
| ; GFX6-NEXT: s_and_b32 s1, s5, s1 | |
| ; GFX6-NEXT: s_or_b32 s2, s2, s3 | |
| ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24 | |
| ; GFX6-NEXT: s_cselect_b32 s2, s2, s4 | |
| ; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1] | |
| ; GFX6-NEXT: s_cselect_b32 s0, 1, 0 | |
| ; GFX6-NEXT: s_xor_b32 s1, s5, 1 | |
| ; GFX6-NEXT: s_and_b32 s0, s0, s1 | |
| ; GFX6-NEXT: s_cmp_lg_u32 s0, 0 | |
| ; GFX6-NEXT: s_cselect_b32 s0, 0x7fc00000, s2 | |
| ; GFX6-NEXT: v_mov_b32_e32 v0, s0 | |
| ; GFX6-NEXT: ; return to shader part epilog | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_sgpr_sgpr: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: v_mov_b32_e32 v0, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 s[2:3], |s0|, v0 | |
| ; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0 | |
| ; GFX8-NEXT: s_cselect_b32 s3, 1, 0 | |
| ; GFX8-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX8-NEXT: s_lshl_b32 s3, s3, 5 | |
| ; GFX8-NEXT: v_mov_b32_e32 v0, s3 | |
| ; GFX8-NEXT: v_ldexp_f32 v0, |s0|, v0 | |
| ; GFX8-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 | |
| ; GFX8-NEXT: s_cselect_b32 s2, 0x42000000, 0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 | |
| ; GFX8-NEXT: v_subrev_f32_e32 v0, s2, v0 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 | |
| ; GFX8-NEXT: s_cmp_lg_u64 vcc, 0 | |
| ; GFX8-NEXT: s_cselect_b32 s2, 0x42800000, 0 | |
| ; GFX8-NEXT: v_add_f32_e32 v0, s2, v0 | |
| ; GFX8-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX8-NEXT: s_cselect_b32 s2, 0xffffffc0, 0 | |
| ; GFX8-NEXT: v_ldexp_f32 v0, v0, s2 | |
| ; GFX8-NEXT: v_readfirstlane_b32 s2, v0 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v0, s1 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, s1, v0 | |
| ; GFX8-NEXT: v_mul_f32_e64 v0, s1, 0.5 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v1, v0 | |
| ; GFX8-NEXT: s_cmp_lg_u64 vcc, 0 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v1, v0 | |
| ; GFX8-NEXT: s_cselect_b32 s3, 1, 0 | |
| ; GFX8-NEXT: s_cmp_lg_u64 vcc, 0 | |
| ; GFX8-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX8-NEXT: s_and_b32 s4, s2, 0x7fffffff | |
| ; GFX8-NEXT: s_and_b32 s5, s0, 0x80000000 | |
| ; GFX8-NEXT: s_and_b32 s1, s3, s1 | |
| ; GFX8-NEXT: s_or_b32 s4, s4, s5 | |
| ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24 | |
| ; GFX8-NEXT: s_cselect_b32 s2, s4, s2 | |
| ; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0 | |
| ; GFX8-NEXT: s_cselect_b32 s0, 1, 0 | |
| ; GFX8-NEXT: s_xor_b32 s1, s3, 1 | |
| ; GFX8-NEXT: s_and_b32 s0, s0, s1 | |
| ; GFX8-NEXT: s_cmp_lg_u32 s0, 0 | |
| ; GFX8-NEXT: s_cselect_b32 s0, 0x7fc00000, s2 | |
| ; GFX8-NEXT: v_mov_b32_e32 v0, s0 | |
| ; GFX8-NEXT: ; return to shader part epilog | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_sgpr_sgpr: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 s[2:3], |s0|, v0 | |
| ; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0 | |
| ; GFX9-NEXT: s_cselect_b32 s3, 1, 0 | |
| ; GFX9-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX9-NEXT: s_lshl_b32 s3, s3, 5 | |
| ; GFX9-NEXT: v_mov_b32_e32 v0, s3 | |
| ; GFX9-NEXT: v_ldexp_f32 v0, |s0|, v0 | |
| ; GFX9-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 | |
| ; GFX9-NEXT: s_cselect_b32 s2, 0x42000000, 0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 | |
| ; GFX9-NEXT: v_subrev_f32_e32 v0, s2, v0 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 | |
| ; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 | |
| ; GFX9-NEXT: s_cselect_b32 s2, 0x42800000, 0 | |
| ; GFX9-NEXT: v_add_f32_e32 v0, s2, v0 | |
| ; GFX9-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX9-NEXT: s_cselect_b32 s2, 0xffffffc0, 0 | |
| ; GFX9-NEXT: v_ldexp_f32 v0, v0, s2 | |
| ; GFX9-NEXT: v_readfirstlane_b32 s2, v0 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v0, s1 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, s1, v0 | |
| ; GFX9-NEXT: v_mul_f32_e64 v0, s1, 0.5 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v1, v0 | |
| ; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v1, v0 | |
| ; GFX9-NEXT: s_cselect_b32 s3, 1, 0 | |
| ; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 | |
| ; GFX9-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX9-NEXT: s_and_b32 s4, s2, 0x7fffffff | |
| ; GFX9-NEXT: s_and_b32 s5, s0, 0x80000000 | |
| ; GFX9-NEXT: s_and_b32 s1, s3, s1 | |
| ; GFX9-NEXT: s_or_b32 s4, s4, s5 | |
| ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[0:1], s0, 24 | |
| ; GFX9-NEXT: s_cselect_b32 s2, s4, s2 | |
| ; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 | |
| ; GFX9-NEXT: s_cselect_b32 s0, 1, 0 | |
| ; GFX9-NEXT: s_xor_b32 s1, s3, 1 | |
| ; GFX9-NEXT: s_and_b32 s0, s0, s1 | |
| ; GFX9-NEXT: s_cmp_lg_u32 s0, 0 | |
| ; GFX9-NEXT: s_cselect_b32 s0, 0x7fc00000, s2 | |
| ; GFX9-NEXT: v_mov_b32_e32 v0, s0 | |
| ; GFX9-NEXT: ; return to shader part epilog | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_sgpr_sgpr: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0| | |
| ; GFX10-NEXT: v_mul_f32_e64 v1, s1, 0.5 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v2, s1 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s4, s0, 24 | |
| ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX10-NEXT: s_cselect_b32 s3, 1, 0 | |
| ; GFX10-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX10-NEXT: s_lshl_b32 s3, s3, 5 | |
| ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 | |
| ; GFX10-NEXT: v_ldexp_f32 v0, |s0|, s3 | |
| ; GFX10-NEXT: s_cselect_b32 s2, 0x42000000, 0 | |
| ; GFX10-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_subrev_f32_e32 v0, s2, v0 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 | |
| ; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0 | |
| ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, s1, v2 | |
| ; GFX10-NEXT: s_cselect_b32 s2, 0x42800000, 0 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s1, v3, v1 | |
| ; GFX10-NEXT: v_add_f32_e32 v0, s2, v0 | |
| ; GFX10-NEXT: s_cselect_b32 s2, 0xffffffc0, 0 | |
| ; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0 | |
| ; GFX10-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_ldexp_f32 v0, v0, s2 | |
| ; GFX10-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX10-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX10-NEXT: v_readfirstlane_b32 s3, v0 | |
| ; GFX10-NEXT: s_and_b32 s0, s0, 0x80000000 | |
| ; GFX10-NEXT: s_and_b32 s1, s2, s1 | |
| ; GFX10-NEXT: s_and_b32 s5, s3, 0x7fffffff | |
| ; GFX10-NEXT: s_or_b32 s5, s5, s0 | |
| ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX10-NEXT: s_cselect_b32 s0, s5, s3 | |
| ; GFX10-NEXT: s_cmp_lg_u32 s4, 0 | |
| ; GFX10-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX10-NEXT: s_xor_b32 s2, s2, 1 | |
| ; GFX10-NEXT: s_and_b32 s1, s1, s2 | |
| ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX10-NEXT: s_cselect_b32 s0, 0x7fc00000, s0 | |
| ; GFX10-NEXT: v_mov_b32_e32 v0, s0 | |
| ; GFX10-NEXT: ; return to shader part epilog | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_sgpr_sgpr: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0| | |
| ; GFX11-NEXT: v_mul_f32_e64 v1, s1, 0.5 | |
| ; GFX11-NEXT: v_trunc_f32_e32 v2, s1 | |
| ; GFX11-NEXT: v_cmp_class_f32_e64 s4, s0, 24 | |
| ; GFX11-NEXT: s_cmp_lg_u32 s2, 0 | |
| ; GFX11-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX11-NEXT: s_cselect_b32 s3, 1, 0 | |
| ; GFX11-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX11-NEXT: s_lshl_b32 s3, s3, 5 | |
| ; GFX11-NEXT: s_cmp_lg_u32 s2, 0 | |
| ; GFX11-NEXT: v_ldexp_f32 v0, |s0|, s3 | |
| ; GFX11-NEXT: s_cselect_b32 s2, 0x42000000, 0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_subrev_f32_e32 v0, s2, v0 | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s1, v0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 | |
| ; GFX11-NEXT: s_cmp_lg_u32 vcc_lo, 0 | |
| ; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, s1, v2 | |
| ; GFX11-NEXT: s_cselect_b32 s2, 0x42800000, 0 | |
| ; GFX11-NEXT: v_cmp_lg_f32_e64 s1, v3, v1 | |
| ; GFX11-NEXT: v_add_f32_e32 v0, s2, v0 | |
| ; GFX11-NEXT: s_cselect_b32 s2, 0xffffffc0, 0 | |
| ; GFX11-NEXT: s_cmp_lg_u32 vcc_lo, 0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v0, v0, s2 | |
| ; GFX11-NEXT: s_cselect_b32 s2, 1, 0 | |
| ; GFX11-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX11-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1) | |
| ; GFX11-NEXT: v_readfirstlane_b32 s3, v0 | |
| ; GFX11-NEXT: s_and_b32 s0, s0, 0x80000000 | |
| ; GFX11-NEXT: s_and_b32 s1, s2, s1 | |
| ; GFX11-NEXT: s_and_b32 s5, s3, 0x7fffffff | |
| ; GFX11-NEXT: s_or_b32 s5, s5, s0 | |
| ; GFX11-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX11-NEXT: s_cselect_b32 s0, s5, s3 | |
| ; GFX11-NEXT: s_cmp_lg_u32 s4, 0 | |
| ; GFX11-NEXT: s_cselect_b32 s1, 1, 0 | |
| ; GFX11-NEXT: s_xor_b32 s2, s2, 1 | |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) | |
| ; GFX11-NEXT: s_and_b32 s1, s1, s2 | |
| ; GFX11-NEXT: s_cmp_lg_u32 s1, 0 | |
| ; GFX11-NEXT: s_cselect_b32 s0, 0x7fc00000, s0 | |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | |
| ; GFX11-NEXT: v_mov_b32_e32 v0, s0 | |
| ; GFX11-NEXT: ; return to shader part epilog | |
| %pow = call float @llvm.pow.f32(float %x, float %y) | |
| ret float %pow | |
| } | |
| define float @v_pow_f32_fneg_lhs(float %x, float %y) { | |
| ; GFX6-LABEL: v_pow_f32_fneg_lhs: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2 | |
| ; GFX6-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_not_b32_e32 v4, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc | |
| ; GFX6-NEXT: v_xor_b32_e32 v3, 0x80000000, v0 | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v4 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v4, v1 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v4, v1 | |
| ; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v4, v1 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v4, v1 | |
| ; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v3 | |
| ; GFX6-NEXT: v_or_b32_e32 v1, v1, v3 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], -v0, 24 | |
| ; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_fneg_lhs: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX8-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX8-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_not_b32_e32 v4, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc | |
| ; GFX8-NEXT: v_xor_b32_e32 v3, 0x80000000, v0 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, v2, v4 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v4, v1 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v4, v1 | |
| ; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v4, v1 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v4, v1 | |
| ; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v3 | |
| ; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], -v0, 24 | |
| ; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_fneg_lhs: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX9-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX9-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_not_b32_e32 v4, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc | |
| ; GFX9-NEXT: v_xor_b32_e32 v3, 0x80000000, v0 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, v2, v4 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v4, v1 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v1 | |
| ; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v4, v1 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v4, v1 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v1, -2 | |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v3 | |
| ; GFX9-NEXT: v_and_or_b32 v1, v2, v1, v3 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], -v0, 24 | |
| ; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_fneg_lhs: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| | |
| ; GFX10-NEXT: v_xor_b32_e32 v5, 0x80000000, v0 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v6, v1 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s6, -v0, 24 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX10-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v1 | |
| ; GFX10-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1 | |
| ; GFX10-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v7, v3 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v7, v3 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, v2, v4 | |
| ; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v5 | |
| ; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4 | |
| ; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v1, s4 | |
| ; GFX10-NEXT: s_xor_b32 s4, vcc_lo, exec_lo | |
| ; GFX10-NEXT: s_and_b32 s4, s6, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_fneg_lhs: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| | |
| ; GFX11-NEXT: v_xor_b32_e32 v5, 0x80000000, v0 | |
| ; GFX11-NEXT: v_trunc_f32_e32 v6, v1 | |
| ; GFX11-NEXT: v_cmp_class_f32_e64 s2, -v0, 24 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0 | |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX11-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX11-NEXT: v_mul_f32_e32 v3, 0.5, v1 | |
| ; GFX11-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_trunc_f32_e32 v7, v3 | |
| ; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v7, v3 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v2, v2, v4 | |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v5 | |
| ; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0 | |
| ; GFX11-NEXT: s_xor_b32 s0, vcc_lo, exec_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | |
| ; GFX11-NEXT: s_and_b32 s0, s2, s0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] | |
| %neg.x = fneg float %x | |
| %pow = call float @llvm.pow.f32(float %neg.x, float %y) | |
| ret float %pow | |
| } | |
| define float @v_pow_f32_fneg_rhs(float %x, float %y) { | |
| ; GFX6-LABEL: v_pow_f32_fneg_rhs: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2 | |
| ; GFX6-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e64 v2, -v1, v2 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24 | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_trunc_f32_e64 v3, -v1 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, -v1 | |
| ; GFX6-NEXT: v_mul_f32_e64 v1, -v1, 0.5 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1 | |
| ; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v1, v1, v3 | |
| ; GFX6-NEXT: s_and_b64 vcc, s[6:7], vcc | |
| ; GFX6-NEXT: s_xor_b64 s[4:5], s[6:7], exec | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX6-NEXT: s_and_b64 vcc, s[8:9], s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_fneg_rhs: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX8-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e64 v2, -v1, v2 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX8-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, v2, v3 | |
| ; GFX8-NEXT: v_trunc_f32_e64 v3, -v1 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, -v1 | |
| ; GFX8-NEXT: v_mul_f32_e64 v1, -v1, 0.5 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1 | |
| ; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 | |
| ; GFX8-NEXT: s_and_b64 vcc, s[6:7], vcc | |
| ; GFX8-NEXT: s_xor_b64 s[4:5], s[6:7], exec | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX8-NEXT: s_and_b64 vcc, s[8:9], s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_fneg_rhs: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX9-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e64 v2, -v1, v2 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX9-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[8:9], v0, 24 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, v2, v3 | |
| ; GFX9-NEXT: v_trunc_f32_e64 v3, -v1 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e64 s[6:7], v3, -v1 | |
| ; GFX9-NEXT: v_mul_f32_e64 v1, -v1, 0.5 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v3, v1 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v1, -2 | |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX9-NEXT: v_and_or_b32 v1, v2, v1, v3 | |
| ; GFX9-NEXT: s_and_b64 vcc, s[6:7], vcc | |
| ; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], exec | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX9-NEXT: s_and_b64 vcc, s[8:9], s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_fneg_rhs: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, |v0| | |
| ; GFX10-NEXT: v_trunc_f32_e64 v5, -v1 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 24 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s5 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s5 | |
| ; GFX10-NEXT: v_cmp_eq_f32_e64 s5, v5, -v1 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX10-NEXT: s_xor_b32 s4, s5, exec_lo | |
| ; GFX10-NEXT: s_and_b32 s4, s6, s4 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX10-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e64 v2, -v1, v2 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX10-NEXT: v_mul_f32_e64 v3, -v1, 0.5 | |
| ; GFX10-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v6, v3 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v3 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, v2, v4 | |
| ; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v0 | |
| ; GFX10-NEXT: s_and_b32 vcc_lo, s5, vcc_lo | |
| ; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4 | |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_fneg_rhs: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |v0| | |
| ; GFX11-NEXT: v_trunc_f32_e64 v5, -v1 | |
| ; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 24 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s1 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s1 | |
| ; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v5, -v1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) | |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX11-NEXT: s_xor_b32 s0, s1, exec_lo | |
| ; GFX11-NEXT: s_and_b32 s0, s2, s0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX11-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v2, -v1, v2 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX11-NEXT: v_mul_f32_e64 v3, -v1, 0.5 | |
| ; GFX11-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_trunc_f32_e32 v6, v3 | |
| ; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v3 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v2, v2, v4 | |
| ; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v0 | |
| ; GFX11-NEXT: s_and_b32 vcc_lo, s1, vcc_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v4 | |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] | |
| %neg.y = fneg float %y | |
| %pow = call float @llvm.pow.f32(float %x, float %neg.y) | |
| ret float %pow | |
| } | |
| define float @v_pow_f32_afn(float %x, float %y) { | |
| ; GFX6-LABEL: v_pow_f32_afn: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 | |
| ; GFX6-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_afn: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 | |
| ; GFX8-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_afn: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 | |
| ; GFX9-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_afn: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 | |
| ; GFX10-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_afn: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] | |
| %pow = call afn float @llvm.pow.f32(float %x, float %y) | |
| ret float %pow | |
| } | |
| define half @v_pow_f16_afn(half %x, half %y) { | |
| ; GFX6-LABEL: v_pow_f16_afn: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 | |
| ; GFX6-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 | |
| ; GFX6-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f16_afn: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 | |
| ; GFX8-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 | |
| ; GFX8-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f16_afn: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 | |
| ; GFX9-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 | |
| ; GFX9-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f16_afn: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1 | |
| ; GFX10-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 | |
| ; GFX10-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-TRUE16-LABEL: v_pow_f16_afn: | |
| ; GFX11-TRUE16: ; %bb.0: | |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l | |
| ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l | |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) | |
| ; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0 | |
| ; GFX11-TRUE16-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 | |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-FAKE16-LABEL: v_pow_f16_afn: | |
| ; GFX11-FAKE16: ; %bb.0: | |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1 | |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) | |
| ; GFX11-FAKE16-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0 | |
| ; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0 | |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] | |
| %pow = call afn half @llvm.pow.f16(half %x, half %y) | |
| ret half %pow | |
| } | |
| define float @v_pow_f32_const_even_int(float %x) { | |
| ; GFX6-LABEL: v_pow_f32_const_even_int: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v1 | |
| ; GFX6-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v1, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0 | |
| ; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX6-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX6-NEXT: v_not_b32_e32 v1, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_const_even_int: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v1 | |
| ; GFX8-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0 | |
| ; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX8-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX8-NEXT: v_not_b32_e32 v1, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc | |
| ; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_const_even_int: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v1 | |
| ; GFX9-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v0, v0, v1 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0 | |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX9-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX9-NEXT: v_not_b32_e32 v1, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc | |
| ; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_const_even_int: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_sub_f32_e32 v0, v0, v1 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_const_even_int: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 | |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v1 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0 | |
| ; GFX11-NEXT: v_log_f32_e32 v0, v0 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, 2.0, v0 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-NEXT: v_exp_f32_e32 v0, v0 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 | |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] | |
| %pow = call float @llvm.pow.f32(float %x, float 2.0) | |
| ret float %pow | |
| } | |
| define float @v_pow_f32_const_odd_int(float %x) { | |
| ; GFX6-LABEL: v_pow_f32_const_odd_int: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v1, |v0|, v1 | |
| ; GFX6-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v1, 0x40400000, v1 | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX6-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX6-NEXT: v_not_b32_e32 v2, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX6-NEXT: v_and_b32_e32 v0, 0x80000000, v0 | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2 | |
| ; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 | |
| ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_const_odd_int: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX8-NEXT: v_ldexp_f32 v1, |v0|, v1 | |
| ; GFX8-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v1, 0x40400000, v1 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX8-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX8-NEXT: v_not_b32_e32 v2, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX8-NEXT: v_and_b32_e32 v0, 0x80000000, v0 | |
| ; GFX8-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 | |
| ; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_const_odd_int: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX9-NEXT: v_ldexp_f32 v1, |v0|, v1 | |
| ; GFX9-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v1, 0x40400000, v1 | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX9-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX9-NEXT: v_not_b32_e32 v2, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX9-NEXT: v_and_b32_e32 v0, 0x80000000, v0 | |
| ; GFX9-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v2, -2 | |
| ; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_const_odd_int: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX10-NEXT: v_ldexp_f32 v1, |v0|, v1 | |
| ; GFX10-NEXT: v_and_b32_e32 v0, 0x80000000, v0 | |
| ; GFX10-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX10-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v1, 0x40400000, v1 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX10-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v0 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_const_odd_int: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0 | |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_ldexp_f32 v1, |v0|, v1 | |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0x80000000, v0 | |
| ; GFX11-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, 0x40400000, v1 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v1, v0 | |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] | |
| %pow = call float @llvm.pow.f32(float %x, float 3.0) | |
| ret float %pow | |
| } | |
| define float @v_pow_f32_const_non_int(float %x) { | |
| ; GFX6-LABEL: v_pow_f32_const_non_int: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v1, |v0|, v1 | |
| ; GFX6-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x42800000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v1, 0.5, v1 | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX6-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX6-NEXT: v_not_b32_e32 v2, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 vcc, v0, 24 | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2 | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x7fc00000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_const_non_int: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX8-NEXT: v_ldexp_f32 v1, |v0|, v1 | |
| ; GFX8-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x42800000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v1, 0.5, v1 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX8-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX8-NEXT: v_not_b32_e32 v2, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 vcc, v0, 24 | |
| ; GFX8-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fc00000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_const_non_int: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX9-NEXT: v_ldexp_f32 v1, |v0|, v1 | |
| ; GFX9-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v1, 0.5, v1 | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX9-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX9-NEXT: v_not_b32_e32 v2, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, 24 | |
| ; GFX9-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_const_non_int: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s4, v0, 24 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX10-NEXT: v_ldexp_f32 v1, |v0|, v1 | |
| ; GFX10-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX10-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v1, 0.5, v1 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX10-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, 0x7fc00000, s4 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_const_non_int: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0 | |
| ; GFX11-NEXT: v_cmp_class_f32_e64 s0, v0, 24 | |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_ldexp_f32 v1, |v0|, v1 | |
| ; GFX11-NEXT: v_log_f32_e32 v1, v1 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_sub_f32_e32 v1, v1, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, 0.5, v1 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_add_f32_e32 v1, v1, v2 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-NEXT: v_exp_f32_e32 v1, v1 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v1, v1, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, 0x7fc00000, s0 | |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] | |
| %pow = call float @llvm.pow.f32(float %x, float 5.000000e-01) | |
| ret float %pow | |
| } | |
| define float @v_pow_f32_nnan(float %x, float %y) { | |
| ; GFX6-LABEL: v_pow_f32_nnan: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX6-NEXT: v_ldexp_f32_e64 v2, |v0|, v2 | |
| ; GFX6-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX6-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX6-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX6-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX6-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX6-NEXT: v_and_b32_e32 v0, 0x80000000, v0 | |
| ; GFX6-NEXT: v_ldexp_f32_e32 v2, v2, v3 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1 | |
| ; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1 | |
| ; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 | |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_nnan: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX8-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX8-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX8-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX8-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX8-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX8-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX8-NEXT: v_and_b32_e32 v0, 0x80000000, v0 | |
| ; GFX8-NEXT: v_ldexp_f32 v2, v2, v3 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1 | |
| ; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1 | |
| ; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 | |
| ; GFX8-NEXT: s_and_b64 vcc, vcc, s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_nnan: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc | |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX9-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0x42000000 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX9-NEXT: v_mov_b32_e32 v4, 0x42800000 | |
| ; GFX9-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2fc0000 | |
| ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc | |
| ; GFX9-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX9-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_not_b32_e32 v3, 63 | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc | |
| ; GFX9-NEXT: v_and_b32_e32 v0, 0x80000000, v0 | |
| ; GFX9-NEXT: v_ldexp_f32 v2, v2, v3 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1 | |
| ; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v1, -2 | |
| ; GFX9-NEXT: v_and_or_b32 v0, v2, v1, v0 | |
| ; GFX9-NEXT: s_and_b64 vcc, vcc, s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_nnan: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| | |
| ; GFX10-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s4 | |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX10-NEXT: v_and_b32_e32 v0, 0x80000000, v0 | |
| ; GFX10-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX10-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo | |
| ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1 | |
| ; GFX10-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1 | |
| ; GFX10-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v6, v3 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v6, v3 | |
| ; GFX10-NEXT: v_ldexp_f32 v2, v2, v4 | |
| ; GFX10-NEXT: s_and_b32 vcc_lo, vcc_lo, s4 | |
| ; GFX10-NEXT: v_and_or_b32 v0, 0x7fffffff, v2, v0 | |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_nnan: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| | |
| ; GFX11-NEXT: v_trunc_f32_e32 v5, v1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s0 | |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_ldexp_f32 v2, |v0|, v2 | |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0x80000000, v0 | |
| ; GFX11-NEXT: v_log_f32_e32 v2, v2 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_sub_f32_e32 v2, v2, v3 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2 | |
| ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, vcc_lo | |
| ; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_add_f32_e32 v2, v2, v3 | |
| ; GFX11-NEXT: v_mul_f32_e32 v3, 0.5, v1 | |
| ; GFX11-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_trunc_f32_e32 v6, v3 | |
| ; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v6, v3 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_ldexp_f32 v2, v2, v4 | |
| ; GFX11-NEXT: s_and_b32 vcc_lo, vcc_lo, s0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_and_or_b32 v0, 0x7fffffff, v2, v0 | |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo | |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] | |
| %pow = call nnan float @llvm.pow.f32(float %x, float %y) | |
| ret float %pow | |
| } | |
| define float @v_pow_f32_daz(float %x, float %y) #0 { | |
| ; GFX6-LABEL: v_pow_f32_daz: | |
| ; GFX6: ; %bb.0: | |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX6-NEXT: v_log_f32_e64 v2, |v0| | |
| ; GFX6-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX6-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1 | |
| ; GFX6-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX6-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX6-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX6-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX6-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX6-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1 | |
| ; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX6-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX6-NEXT: v_or_b32_e32 v1, v1, v3 | |
| ; GFX6-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 8 | |
| ; GFX6-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX6-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX8-LABEL: v_pow_f32_daz: | |
| ; GFX8: ; %bb.0: | |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX8-NEXT: v_log_f32_e64 v2, |v0| | |
| ; GFX8-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1 | |
| ; GFX8-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX8-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX8-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX8-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX8-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1 | |
| ; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 | |
| ; GFX8-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 | |
| ; GFX8-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX8-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 8 | |
| ; GFX8-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX8-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX8-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX9-LABEL: v_pow_f32_daz: | |
| ; GFX9: ; %bb.0: | |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX9-NEXT: v_log_f32_e64 v2, |v0| | |
| ; GFX9-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1 | |
| ; GFX9-NEXT: s_xor_b64 s[6:7], vcc, exec | |
| ; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX9-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX9-NEXT: v_mul_f32_e32 v1, 0.5, v1 | |
| ; GFX9-NEXT: v_trunc_f32_e32 v3, v1 | |
| ; GFX9-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1 | |
| ; GFX9-NEXT: v_bfrev_b32_e32 v1, -2 | |
| ; GFX9-NEXT: v_and_b32_e32 v3, 0x80000000, v0 | |
| ; GFX9-NEXT: v_and_or_b32 v1, v2, v1, v3 | |
| ; GFX9-NEXT: s_and_b64 s[4:5], vcc, s[4:5] | |
| ; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5] | |
| ; GFX9-NEXT: v_cmp_class_f32_e64 s[4:5], v0, 8 | |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7fc00000 | |
| ; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[6:7] | |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc | |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX10-LABEL: v_pow_f32_daz: | |
| ; GFX10: ; %bb.0: | |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX10-NEXT: v_log_f32_e64 v2, |v0| | |
| ; GFX10-NEXT: v_mul_f32_e32 v3, 0.5, v1 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v4, v1 | |
| ; GFX10-NEXT: v_and_b32_e32 v6, 0x80000000, v0 | |
| ; GFX10-NEXT: v_cmp_class_f32_e64 s6, v0, 8 | |
| ; GFX10-NEXT: v_trunc_f32_e32 v5, v3 | |
| ; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v1 | |
| ; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v1, v2 | |
| ; GFX10-NEXT: v_cmp_lg_f32_e64 s4, v5, v3 | |
| ; GFX10-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4 | |
| ; GFX10-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v6 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v1, s4 | |
| ; GFX10-NEXT: s_xor_b32 s4, vcc_lo, exec_lo | |
| ; GFX10-NEXT: s_and_b32 s4, s6, s4 | |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s4 | |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] | |
| ; | |
| ; GFX11-LABEL: v_pow_f32_daz: | |
| ; GFX11: ; %bb.0: | |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | |
| ; GFX11-NEXT: v_log_f32_e64 v2, |v0| | |
| ; GFX11-NEXT: v_trunc_f32_e32 v4, v1 | |
| ; GFX11-NEXT: v_and_b32_e32 v6, 0x80000000, v0 | |
| ; GFX11-NEXT: v_cmp_class_f32_e64 s2, v0, 8 | |
| ; GFX11-NEXT: v_mul_f32_e32 v3, 0.5, v1 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v1 | |
| ; GFX11-NEXT: v_trunc_f32_e32 v5, v3 | |
| ; GFX11-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) | |
| ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v1, v2 | |
| ; GFX11-NEXT: v_cmp_lg_f32_e64 s0, v5, v3 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) | |
| ; GFX11-NEXT: v_exp_f32_e32 v2, v2 | |
| ; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 | |
| ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) | |
| ; GFX11-NEXT: v_and_or_b32 v1, 0x7fffffff, v2, v6 | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v1, s0 | |
| ; GFX11-NEXT: s_xor_b32 s0, vcc_lo, exec_lo | |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | |
| ; GFX11-NEXT: s_and_b32 s0, s2, s0 | |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) | |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0x7fc00000, s0 | |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] | |
| %pow = call float @llvm.pow.f32(float %x, float %y) | |
| ret float %pow | |
| } | |
| declare half @llvm.pow.f16(half, half) | |
| declare float @llvm.pow.f32(float, float) | |
| declare double @llvm.pow.f64(double, double) | |
| declare half @llvm.fabs.f16(half) | |
| declare float @llvm.fabs.f32(float) | |
| declare <2 x half> @llvm.pow.v2f16(<2 x half>, <2 x half>) | |
| declare <2 x float> @llvm.pow.v2f32(<2 x float>, <2 x float>) | |
| attributes #0 = { denormal_fpenv(float:preservesign|preservesign) } |