commit 5290f50e44b632c22800df15c691394e768796be
author Sebastian Neubauer <sebastian.neubauer@amd.com> Tue Oct 20 18:23:24 2020 +0200
committer Sebastian Neubauer <sebastian.neubauer@amd.com> Wed Oct 21 12:37:52 2020 +0200
tree 375738d5b5df2ac570f44a15433d0776c90a64c6
parent 0c66606230df39e0bf4190f1fc2c2e2fb37a81ea

[AMDGPU] Fix off by one in assert

D89217 did not subtract one when accessing SubRegFromChannelTable in one
place.

Differential Revision: https://reviews.llvm.org/D89804

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index c7a0121..6000c8a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -98,9 +98,10 @@
       Width = SubRegFromChannelTableWidthMap[Width];
       if (Width == 0)
         continue;
-      assert((Width - 1) < SubRegFromChannelTable.size());
-      assert(Offset < SubRegFromChannelTable[Width].size());
-      SubRegFromChannelTable[Width - 1][Offset] = Idx;
+      unsigned TableIdx = Width - 1;
+      assert(TableIdx < SubRegFromChannelTable.size());
+      assert(Offset < SubRegFromChannelTable[TableIdx].size());
+      SubRegFromChannelTable[TableIdx][Offset] = Idx;
     }
   };