llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+experimental-xqcili | FileCheck %s --check-prefixes=RV32I
; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64I
; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+experimental-xqcili,+short-forward-branch-ialu | \
; RUN:   FileCheck %s --check-prefixes=RV32I-SFB
; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64 -mattr=+short-forward-branch-ialu | \
; RUN:   FileCheck %s --check-prefixes=RV64I-SFB

define i32 @select_example_1(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
; RV32I-LABEL: select_example_1:
; RV32I:       # %bb.0: # %entry
; RV32I-NEXT:    lui a0, 16
; RV32I-NEXT:    bnez a2, .LBB0_2
; RV32I-NEXT:  # %bb.1: # %entry
; RV32I-NEXT:    mv a0, a1
; RV32I-NEXT:  .LBB0_2: # %entry
; RV32I-NEXT:    ret
;
; RV64I-LABEL: select_example_1:
; RV64I:       # %bb.0: # %entry
; RV64I-NEXT:    lui a0, 16
; RV64I-NEXT:    bnez a2, .LBB0_2
; RV64I-NEXT:  # %bb.1: # %entry
; RV64I-NEXT:    mv a0, a1
; RV64I-NEXT:  .LBB0_2: # %entry
; RV64I-NEXT:    ret
;
; RV32I-SFB-LABEL: select_example_1:
; RV32I-SFB:       # %bb.0: # %entry
; RV32I-SFB-NEXT:    mv a0, a1
; RV32I-SFB-NEXT:    beqz a2, .LBB0_2
; RV32I-SFB-NEXT:  # %bb.1: # %entry
; RV32I-SFB-NEXT:    lui a0, 16
; RV32I-SFB-NEXT:  .LBB0_2: # %entry
; RV32I-SFB-NEXT:    ret
;
; RV64I-SFB-LABEL: select_example_1:
; RV64I-SFB:       # %bb.0: # %entry
; RV64I-SFB-NEXT:    mv a0, a1
; RV64I-SFB-NEXT:    beqz a2, .LBB0_2
; RV64I-SFB-NEXT:  # %bb.1: # %entry
; RV64I-SFB-NEXT:    lui a0, 16
; RV64I-SFB-NEXT:  .LBB0_2: # %entry
; RV64I-SFB-NEXT:    ret
entry:
  %sel = select i1 %x, i32 65536, i32 %b
  ret i32 %sel
}

define i32 @select_example_2(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
; RV32I-LABEL: select_example_2:
; RV32I:       # %bb.0: # %entry
; RV32I-NEXT:    bnez a2, .LBB1_2
; RV32I-NEXT:  # %bb.1: # %entry
; RV32I-NEXT:    mv a0, a1
; RV32I-NEXT:    ret
; RV32I-NEXT:  .LBB1_2:
; RV32I-NEXT:    qc.li a0, 65543
; RV32I-NEXT:    ret
;
; RV64I-LABEL: select_example_2:
; RV64I:       # %bb.0: # %entry
; RV64I-NEXT:    bnez a2, .LBB1_2
; RV64I-NEXT:  # %bb.1: # %entry
; RV64I-NEXT:    mv a0, a1
; RV64I-NEXT:    ret
; RV64I-NEXT:  .LBB1_2:
; RV64I-NEXT:    lui a0, 16
; RV64I-NEXT:    addi a0, a0, 7
; RV64I-NEXT:    ret
;
; RV32I-SFB-LABEL: select_example_2:
; RV32I-SFB:       # %bb.0: # %entry
; RV32I-SFB-NEXT:    mv a0, a1
; RV32I-SFB-NEXT:    beqz a2, .LBB1_2
; RV32I-SFB-NEXT:  # %bb.1: # %entry
; RV32I-SFB-NEXT:    qc.li a0, 65543
; RV32I-SFB-NEXT:  .LBB1_2: # %entry
; RV32I-SFB-NEXT:    ret
;
; RV64I-SFB-LABEL: select_example_2:
; RV64I-SFB:       # %bb.0: # %entry
; RV64I-SFB-NEXT:    mv a0, a1
; RV64I-SFB-NEXT:    lui a1, 16
; RV64I-SFB-NEXT:    beqz a2, .LBB1_2
; RV64I-SFB-NEXT:  # %bb.1: # %entry
; RV64I-SFB-NEXT:    addi a0, a1, 7
; RV64I-SFB-NEXT:  .LBB1_2: # %entry
; RV64I-SFB-NEXT:    ret
entry:
  %sel = select i1 %x, i32 65543, i32 %b
  ret i32 %sel
}

define i32 @select_example_3(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
; RV32I-LABEL: select_example_3:
; RV32I:       # %bb.0: # %entry
; RV32I-NEXT:    bnez a2, .LBB2_2
; RV32I-NEXT:  # %bb.1: # %entry
; RV32I-NEXT:    mv a0, a1
; RV32I-NEXT:    ret
; RV32I-NEXT:  .LBB2_2:
; RV32I-NEXT:    qc.e.li a0, 4198928
; RV32I-NEXT:    ret
;
; RV64I-LABEL: select_example_3:
; RV64I:       # %bb.0: # %entry
; RV64I-NEXT:    bnez a2, .LBB2_2
; RV64I-NEXT:  # %bb.1: # %entry
; RV64I-NEXT:    mv a0, a1
; RV64I-NEXT:    ret
; RV64I-NEXT:  .LBB2_2:
; RV64I-NEXT:    lui a0, 1025
; RV64I-NEXT:    addi a0, a0, 528
; RV64I-NEXT:    ret
;
; RV32I-SFB-LABEL: select_example_3:
; RV32I-SFB:       # %bb.0: # %entry
; RV32I-SFB-NEXT:    mv a0, a1
; RV32I-SFB-NEXT:    beqz a2, .LBB2_2
; RV32I-SFB-NEXT:  # %bb.1: # %entry
; RV32I-SFB-NEXT:    qc.e.li a0, 4198928
; RV32I-SFB-NEXT:  .LBB2_2: # %entry
; RV32I-SFB-NEXT:    ret
;
; RV64I-SFB-LABEL: select_example_3:
; RV64I-SFB:       # %bb.0: # %entry
; RV64I-SFB-NEXT:    mv a0, a1
; RV64I-SFB-NEXT:    lui a1, 1025
; RV64I-SFB-NEXT:    beqz a2, .LBB2_2
; RV64I-SFB-NEXT:  # %bb.1: # %entry
; RV64I-SFB-NEXT:    addi a0, a1, 528
; RV64I-SFB-NEXT:  .LBB2_2: # %entry
; RV64I-SFB-NEXT:    ret
entry:
  %sel = select i1 %x, i32 4198928, i32 %b
  ret i32 %sel
}