llvm/test/CodeGen/RISCV/rv64p.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \
; RUN:   | FileCheck %s

define i32 @abs_i32(i32 %x) {
; CHECK-LABEL: abs_i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    absw a0, a0
; CHECK-NEXT:    ret
  %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
  ret i32 %abs
}

define signext i32 @abs_i32_sext(i32 signext %x) {
; CHECK-LABEL: abs_i32_sext:
; CHECK:       # %bb.0:
; CHECK-NEXT:    absw a0, a0
; CHECK-NEXT:    ret
  %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
  ret i32 %abs
}

define i64 @abs_i64(i64 %x) {
; CHECK-LABEL: abs_i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    abs a0, a0
; CHECK-NEXT:    ret
  %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
  ret i64 %abs
}