llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s

declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.bf16(<16 x bfloat> %src, i32 %sr, float %scale)
declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f16(<16 x half> %src, i32 %sr, float %scale)
declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f32(<16 x float> %src, i32 %sr, float %scale)
declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.bf16(<16 x bfloat> %src, i32 %sr, float %scale)
declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f16(<16 x half> %src, i32 %sr, float %scale)
declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f32(<16 x float> %src, i32 %sr, float %scale)

define amdgpu_ps void @test_scalef32_sr_pk16_bf6_bf16_vv(<16 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_bf16_vv:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT:    v_cvt_scalef32_sr_pk16_bf6_bf16 v[12:14], v[0:7], v8, v9
; GFX1250-NEXT:    global_store_b96 v[10:11], v[12:14], off
; GFX1250-NEXT:    s_endpgm
  %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.bf16(<16 x bfloat> %src, i32 %sr, float %scale)
  store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_sr_pk16_bf6_bf16_sl(<16 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_bf16_sl:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-NEXT:    v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
; GFX1250-NEXT:    v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_cvt_scalef32_sr_pk16_bf6_bf16 v[10:12], v[2:9], s8, 0x42c80000
; GFX1250-NEXT:    global_store_b96 v[0:1], v[10:12], off
; GFX1250-NEXT:    s_endpgm
  %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.bf16(<16 x bfloat> %src, i32 %sr, float 100.0)
  store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_vv(<16 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_f16_vv:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT:    v_cvt_scalef32_sr_pk16_bf6_f16 v[12:14], v[0:7], v8, v9
; GFX1250-NEXT:    global_store_b96 v[10:11], v[12:14], off
; GFX1250-NEXT:    s_endpgm
  %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f16(<16 x half> %src, i32 %sr, float %scale)
  store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_sl(<16 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_bf6_f16_sl:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[2:9], s8, 0x42c80000
; GFX1250-SDAG-NEXT:    global_store_b96 v[0:1], v[10:12], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_bf6_f16_sl:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[2:9], s8, 0x42c80000
; GFX1250-GISEL-NEXT:    global_store_b96 v[0:1], v[10:12], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f16(<16 x half> %src, i32 %sr, float 100.0)
  store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_sr_pk16_fp6_bf16_vv(<16 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_bf16_vv:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT:    v_cvt_scalef32_sr_pk16_fp6_bf16 v[12:14], v[0:7], v8, v9
; GFX1250-NEXT:    global_store_b96 v[10:11], v[12:14], off
; GFX1250-NEXT:    s_endpgm
  %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.bf16(<16 x bfloat> %src, i32 %sr, float %scale)
  store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_sr_pk16_fp6_bf16_sl(<16 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_bf16_sl:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-NEXT:    v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
; GFX1250-NEXT:    v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_cvt_scalef32_sr_pk16_fp6_bf16 v[10:12], v[2:9], s8, 0x42c80000
; GFX1250-NEXT:    global_store_b96 v[0:1], v[10:12], off
; GFX1250-NEXT:    s_endpgm
  %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.bf16(<16 x bfloat> %src, i32 %sr, float 100.0)
  store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_vv(<16 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_f16_vv:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT:    v_cvt_scalef32_sr_pk16_fp6_f16 v[12:14], v[0:7], v8, v9
; GFX1250-NEXT:    global_store_b96 v[10:11], v[12:14], off
; GFX1250-NEXT:    s_endpgm
  %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f16(<16 x half> %src, i32 %sr, float %scale)
  store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_sl(<16 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_fp6_f16_sl:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[2:9], s8, 0x42c80000
; GFX1250-SDAG-NEXT:    global_store_b96 v[0:1], v[10:12], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_fp6_f16_sl:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[2:9], s8, 0x42c80000
; GFX1250-GISEL-NEXT:    global_store_b96 v[0:1], v[10:12], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f16(<16 x half> %src, i32 %sr, float 100.0)
  store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_vv(<16 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_f32_vv:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT:    v_cvt_scalef32_sr_pk16_bf6_f32 v[20:22], v[0:15], v16, v17
; GFX1250-NEXT:    global_store_b96 v[18:19], v[20:22], off
; GFX1250-NEXT:    s_endpgm
  %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f32(<16 x float> %src, i32 %sr, float %scale)
  store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_sl(<16 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_bf6_f32_sl:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_sr_pk16_bf6_f32 v[18:20], v[2:17], s16, 0x42c80000
; GFX1250-SDAG-NEXT:    global_store_b96 v[0:1], v[18:20], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_bf6_f32_sl:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[16:17], s[14:15]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[14:15], s[12:13]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[12:13], s[10:11]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[10:11], s[8:9]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_sr_pk16_bf6_f32 v[18:20], v[2:17], s16, 0x42c80000
; GFX1250-GISEL-NEXT:    global_store_b96 v[0:1], v[18:20], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f32(<16 x float> %src, i32 %sr, float 100.0)
  store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f32_vv(<16 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_f32_vv:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT:    v_cvt_scalef32_sr_pk16_fp6_f32 v[20:22], v[0:15], v16, v17
; GFX1250-NEXT:    global_store_b96 v[18:19], v[20:22], off
; GFX1250-NEXT:    s_endpgm
  %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f32(<16 x float> %src, i32 %sr, float %scale)
  store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f32_sl(<16 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_fp6_f32_sl:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    v_cvt_scalef32_sr_pk16_fp6_f32 v[18:20], v[2:17], s16, 0x42c80000
; GFX1250-SDAG-NEXT:    global_store_b96 v[0:1], v[18:20], off
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_fp6_f32_sl:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[16:17], s[14:15]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[14:15], s[12:13]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[12:13], s[10:11]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[10:11], s[8:9]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_cvt_scalef32_sr_pk16_fp6_f32 v[18:20], v[2:17], s16, 0x42c80000
; GFX1250-GISEL-NEXT:    global_store_b96 v[0:1], v[18:20], off
; GFX1250-GISEL-NEXT:    s_endpgm
  %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f32(<16 x float> %src, i32 %sr, float 100.0)
  store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
  ret void
}