llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck %s

; Check for verifier error after tail duplication. An implicit_def of
; a subregsiter is needed to maintain liveness after assignment.

define amdgpu_vs void @test(i32 inreg %cmp, i32 %e0) {
; CHECK-LABEL: test:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    s_cmp_eq_u32 s0, 0
; CHECK-NEXT:    s_mov_b32 s0, 0
; CHECK-NEXT:    s_cbranch_scc1 .LBB0_2
; CHECK-NEXT:  ; %bb.1: ; %load
; CHECK-NEXT:    s_mov_b32 s1, s0
; CHECK-NEXT:    s_mov_b32 s2, s0
; CHECK-NEXT:    s_mov_b32 s3, s0
; CHECK-NEXT:    v_mov_b32_e32 v1, 0
; CHECK-NEXT:    buffer_load_format_xy v[1:2], v1, s[0:3], 0 idxen
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    exp mrt0 v0, v1, v2, v0
; CHECK-NEXT:    s_endpgm
; CHECK-NEXT:  .LBB0_2:
; CHECK-NEXT:    v_mov_b32_e32 v1, 0
; CHECK-NEXT:    exp mrt0 v0, v1, v2, v0
; CHECK-NEXT:    s_endpgm
entry:
  %cond = icmp eq i32 %cmp, 0
  br i1 %cond, label %end, label %load

load:
  %data1 = call <2 x i32> @llvm.amdgcn.struct.buffer.load.format.v2i32(<4 x i32> zeroinitializer, i32 0, i32 0, i32 0, i32 0)
  %e1 = extractelement <2 x i32> %data1, i32 0
  %e2 = extractelement <2 x i32> %data1, i32 1
  br label %end

end:
  %out1 = phi i32 [ 0, %entry ], [ %e1, %load ]
  %out2 = phi i32 [ poison, %entry ], [ %e2, %load ]
  call void @llvm.amdgcn.exp.i32(i32 0, i32 15, i32 %e0, i32 %out1, i32 %out2, i32 %e0, i1 false, i1 false)
  ret void
}