llvm/test/CodeGen/RISCV/fixed-csr.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv64 -mattr=+reserve-x24 < %s | FileCheck %s

define noundef signext i32 @foo() {
; CHECK-LABEL: foo:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li s8, 321
; CHECK-NEXT:    li a0, 0
; CHECK-NEXT:    ret
  tail call void @llvm.write_register.i64(metadata !0, i64 321)
  ret i32 0
}

declare void @llvm.write_register.i64(metadata, i64)

define noundef signext i32 @bar() nounwind {
; CHECK-LABEL: bar:
; CHECK:       # %bb.0:
; CHECK-NEXT:    addi sp, sp, -16
; CHECK-NEXT:    sd s9, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT:    #APP
; CHECK-NEXT:    #NO_APP
; CHECK-NEXT:    li s8, 321
; CHECK-NEXT:    li a0, 0
; CHECK-NEXT:    ld s9, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT:    addi sp, sp, 16
; CHECK-NEXT:    ret
  tail call void asm sideeffect "", "~{x25}"() #3
  tail call void @llvm.write_register.i64(metadata !0, i64 321)
  ret i32 0
}

!llvm.named.register.x24 = !{!0}
!0 = !{!"x24"}