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llvm/llvm-project/4c6646f1e497e25cb4e6a633ce565c864e66de93/./llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
blob: 1afc36f8b89f43c75e8c45ae786932fd3813a4ea [file]
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s --check-prefixes=SI
; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck %s --check-prefixes=VI
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11,GFX11-SDAG
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11,GFX11-GISEL
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck %s --check-prefixes=EG
declare float @llvm.fabs.f32(float) #1
define amdgpu_kernel void @fp_to_sint_i32(ptr addrspace(1) %out, float %in) {
; SI-LABEL: fp_to_sint_i32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_cvt_i32_f32_e32 v0, s2
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fp_to_sint_i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cvt_i32_f32_e32 v0, s2
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: fp_to_sint_i32:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_clause 0x1
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v1, s2
; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_sint_i32:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_clause 0x1
; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s2
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
; EG-LABEL: fp_to_sint_i32:
; EG: ; %bb.0:
; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: TRUNC * T0.W, KC0[2].Z,
; EG-NEXT: FLT_TO_INT T0.X, PV.W,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%conv = fptosi float %in to i32
store i32 %conv, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fp_to_sint_i32_fabs(ptr addrspace(1) %out, float %in) {
; SI-LABEL: fp_to_sint_i32_fabs:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_cvt_i32_f32_e64 v0, |s2|
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fp_to_sint_i32_fabs:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cvt_i32_f32_e64 v0, |s2|
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: fp_to_sint_i32_fabs:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_clause 0x1
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cvt_i32_f32_e64 v1, |s2|
; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_sint_i32_fabs:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_clause 0x1
; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e64 v0, |s2|
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
; EG-LABEL: fp_to_sint_i32_fabs:
; EG: ; %bb.0:
; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: TRUNC * T0.W, |KC0[2].Z|,
; EG-NEXT: FLT_TO_INT T0.X, PV.W,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%in.fabs = call float @llvm.fabs.f32(float %in)
%conv = fptosi float %in.fabs to i32
store i32 %conv, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fp_to_sint_v2i32(ptr addrspace(1) %out, <2 x float> %in) {
; SI-LABEL: fp_to_sint_v2i32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_cvt_i32_f32_e32 v1, s3
; SI-NEXT: v_cvt_i32_f32_e32 v0, s2
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fp_to_sint_v2i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cvt_i32_f32_e32 v1, s3
; VI-NEXT: v_cvt_i32_f32_e32 v0, s2
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: fp_to_sint_v2i32:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v1, s3
; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v0, s2
; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_sint_v2i32:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s2
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v1, s3
; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
; EG-LABEL: fp_to_sint_v2i32:
; EG: ; %bb.0:
; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: TRUNC * T0.W, KC0[3].X,
; EG-NEXT: FLT_TO_INT T0.Y, PV.W,
; EG-NEXT: TRUNC * T0.W, KC0[2].W,
; EG-NEXT: FLT_TO_INT T0.X, PV.W,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%result = fptosi <2 x float> %in to <2 x i32>
store <2 x i32> %result, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fp_to_sint_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; SI-LABEL: fp_to_sint_v4i32:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_cvt_i32_f32_e32 v3, s7
; SI-NEXT: v_cvt_i32_f32_e32 v2, s6
; SI-NEXT: v_cvt_i32_f32_e32 v1, s5
; SI-NEXT: v_cvt_i32_f32_e32 v0, s4
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fp_to_sint_v4i32:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cvt_i32_f32_e32 v3, s7
; VI-NEXT: v_cvt_i32_f32_e32 v2, s6
; VI-NEXT: v_cvt_i32_f32_e32 v1, s5
; VI-NEXT: v_cvt_i32_f32_e32 v0, s4
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: fp_to_sint_v4i32:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v4, 0
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v3, s7
; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v2, s6
; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v1, s5
; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v0, s4
; GFX11-SDAG-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_sint_v4i32:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s4
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v1, s5
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v2, s6
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v3, s7
; GFX11-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
; EG-LABEL: fp_to_sint_v4i32:
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 9, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 6:
; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
; EG-NEXT: ALU clause starting at 8:
; EG-NEXT: MOV * T0.X, KC0[2].Z,
; EG-NEXT: ALU clause starting at 9:
; EG-NEXT: TRUNC T0.W, T0.W,
; EG-NEXT: TRUNC * T1.W, T0.Z,
; EG-NEXT: FLT_TO_INT * T0.W, PV.W,
; EG-NEXT: FLT_TO_INT T0.Z, T1.W,
; EG-NEXT: TRUNC * T1.W, T0.Y,
; EG-NEXT: FLT_TO_INT T0.Y, PV.W,
; EG-NEXT: TRUNC * T1.W, T0.X,
; EG-NEXT: FLT_TO_INT T0.X, PV.W,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%value = load <4 x float>, ptr addrspace(1) %in
%result = fptosi <4 x float> %value to <4 x i32>
store <4 x i32> %result, ptr addrspace(1) %out
ret void
}
; Check that the compiler doesn't crash with a "cannot select" error
define amdgpu_kernel void @fp_to_sint_i64 (ptr addrspace(1) %out, float %in) {
; SI-LABEL: fp_to_sint_i64:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dword s2, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s4, 0x2f800000
; SI-NEXT: s_mov_b32 s5, 0xcf800000
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_trunc_f32_e32 v0, s2
; SI-NEXT: v_mul_f32_e64 v1, |v0|, s4
; SI-NEXT: v_floor_f32_e32 v1, v1
; SI-NEXT: v_fma_f32 v2, v1, s5, |v0|
; SI-NEXT: v_cvt_u32_f32_e32 v2, v2
; SI-NEXT: v_cvt_u32_f32_e32 v1, v1
; SI-NEXT: v_ashrrev_i32_e32 v3, 31, v0
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_xor_b32_e32 v0, v2, v3
; SI-NEXT: v_xor_b32_e32 v1, v1, v3
; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; SI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fp_to_sint_i64:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT: s_mov_b32 s4, 0x2f800000
; VI-NEXT: s_mov_b32 s5, 0xcf800000
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_trunc_f32_e32 v0, s2
; VI-NEXT: v_mul_f32_e64 v1, |v0|, s4
; VI-NEXT: v_floor_f32_e32 v1, v1
; VI-NEXT: v_fma_f32 v2, v1, s5, |v0|
; VI-NEXT: v_cvt_u32_f32_e32 v2, v2
; VI-NEXT: v_cvt_u32_f32_e32 v1, v1
; VI-NEXT: v_ashrrev_i32_e32 v3, 31, v0
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: v_xor_b32_e32 v0, v2, v3
; VI-NEXT: v_xor_b32_e32 v1, v1, v3
; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v3
; VI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: fp_to_sint_i64:
; GFX11-SDAG: ; %bb.0: ; %entry
; GFX11-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x2c
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_trunc_f32_e32 v0, s0
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0|
; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v3, 31, v0
; GFX11-SDAG-NEXT: v_floor_f32_e32 v1, v1
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-NEXT: v_fma_f32 v2, 0xcf800000, v1, |v0|
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v2
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-SDAG-NEXT: v_xor_b32_e32 v1, v1, v3
; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX11-SDAG-NEXT: v_xor_b32_e32 v0, v0, v3
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v3
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_sint_i64:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_clause 0x1
; GFX11-GISEL-NEXT: s_load_b32 s6, s[4:5], 0x2c
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_trunc_f32_e32 v0, s6
; GFX11-GISEL-NEXT: s_ashr_i32 s4, s6, 31
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: s_mov_b32 s5, s4
; GFX11-GISEL-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0|
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_floor_f32_e32 v1, v1
; GFX11-GISEL-NEXT: v_fma_f32 v0, 0xcf800000, v1, |v0|
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX11-GISEL-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
; GFX11-GISEL-NEXT: s_sub_u32 s2, s2, s4
; GFX11-GISEL-NEXT: s_subb_u32 s3, s3, s4
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
; EG-LABEL: fp_to_sint_i64:
; EG: ; %bb.0: ; %entry
; EG-NEXT: ALU 40, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: MOV * T0.W, literal.x,
; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT: BFE_UINT T0.W, KC0[2].Z, literal.x, PV.W,
; EG-NEXT: AND_INT * T1.W, KC0[2].Z, literal.y,
; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT: OR_INT T1.W, PS, literal.x,
; EG-NEXT: ADD_INT * T2.W, PV.W, literal.y,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: ADD_INT T0.X, T0.W, literal.x,
; EG-NEXT: AND_INT T0.Y, PS, literal.y,
; EG-NEXT: SUB_INT T0.Z, literal.z, T0.W,
; EG-NEXT: NOT_INT T0.W, PS,
; EG-NEXT: LSHR * T3.W, PV.W, 1,
; EG-NEXT: -127(nan), 31(4.344025e-44)
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
; EG-NEXT: AND_INT T1.Y, PV.Z, literal.x,
; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, T1.W, PV.Z,
; EG-NEXT: LSHL T0.W, T1.W, PV.Y,
; EG-NEXT: AND_INT * T1.W, T2.W, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: CNDE_INT T0.W, PS, PV.X, PV.W,
; EG-NEXT: SETGT_INT * T1.W, T0.X, literal.x,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T1.Z, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T0.W, PS, PV.Z, PV.Y,
; EG-NEXT: ASHR * T1.W, KC0[2].Z, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: XOR_INT T0.W, PV.W, PS,
; EG-NEXT: XOR_INT * T2.W, PV.Z, PS,
; EG-NEXT: SUB_INT T2.W, PS, T1.W,
; EG-NEXT: SUBB_UINT * T3.W, PV.W, T1.W,
; EG-NEXT: SUB_INT T2.W, PV.W, PS,
; EG-NEXT: SETGT_INT * T3.W, 0.0, T0.X,
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T0.W, T1.W,
; EG-NEXT: CNDE_INT T0.X, T3.W, PV.W, 0.0,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%0 = fptosi float %in to i64
store i64 %0, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fp_to_sint_v2i64(ptr addrspace(1) %out, <2 x float> %x) {
; SI-LABEL: fp_to_sint_v2i64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s6, 0x2f800000
; SI-NEXT: s_mov_b32 s7, 0xcf800000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-NEXT: v_trunc_f32_e32 v0, s5
; SI-NEXT: v_mul_f32_e64 v1, |v0|, s6
; SI-NEXT: v_floor_f32_e32 v1, v1
; SI-NEXT: v_cvt_u32_f32_e32 v2, v1
; SI-NEXT: v_fma_f32 v1, v1, s7, |v0|
; SI-NEXT: v_ashrrev_i32_e32 v0, 31, v0
; SI-NEXT: v_trunc_f32_e32 v4, s4
; SI-NEXT: v_xor_b32_e32 v3, v2, v0
; SI-NEXT: v_mul_f32_e64 v2, |v4|, s6
; SI-NEXT: v_cvt_u32_f32_e32 v1, v1
; SI-NEXT: v_floor_f32_e32 v2, v2
; SI-NEXT: v_cvt_u32_f32_e32 v5, v2
; SI-NEXT: v_fma_f32 v2, v2, s7, |v4|
; SI-NEXT: v_cvt_u32_f32_e32 v6, v2
; SI-NEXT: v_xor_b32_e32 v1, v1, v0
; SI-NEXT: v_sub_i32_e32 v2, vcc, v1, v0
; SI-NEXT: v_ashrrev_i32_e32 v1, 31, v4
; SI-NEXT: v_subb_u32_e32 v3, vcc, v3, v0, vcc
; SI-NEXT: v_xor_b32_e32 v0, v6, v1
; SI-NEXT: v_xor_b32_e32 v4, v5, v1
; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fp_to_sint_v2i64:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_mov_b32 s6, 0x2f800000
; VI-NEXT: s_mov_b32 s7, 0xcf800000
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b64 s[4:5], s[2:3]
; VI-NEXT: v_trunc_f32_e32 v0, s5
; VI-NEXT: v_mul_f32_e64 v1, |v0|, s6
; VI-NEXT: v_floor_f32_e32 v1, v1
; VI-NEXT: v_cvt_u32_f32_e32 v2, v1
; VI-NEXT: v_fma_f32 v1, v1, s7, |v0|
; VI-NEXT: v_ashrrev_i32_e32 v0, 31, v0
; VI-NEXT: v_trunc_f32_e32 v4, s4
; VI-NEXT: v_xor_b32_e32 v3, v2, v0
; VI-NEXT: v_mul_f32_e64 v2, |v4|, s6
; VI-NEXT: v_cvt_u32_f32_e32 v1, v1
; VI-NEXT: v_floor_f32_e32 v2, v2
; VI-NEXT: v_cvt_u32_f32_e32 v5, v2
; VI-NEXT: v_fma_f32 v2, v2, s7, |v4|
; VI-NEXT: v_cvt_u32_f32_e32 v6, v2
; VI-NEXT: v_xor_b32_e32 v1, v1, v0
; VI-NEXT: v_sub_u32_e32 v2, vcc, v1, v0
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v4
; VI-NEXT: v_subb_u32_e32 v3, vcc, v3, v0, vcc
; VI-NEXT: v_xor_b32_e32 v0, v6, v1
; VI-NEXT: v_xor_b32_e32 v4, v5, v1
; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: fp_to_sint_v2i64:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v6, 0
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_trunc_f32_e32 v0, s3
; GFX11-SDAG-NEXT: v_trunc_f32_e32 v1, s2
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v0|
; GFX11-SDAG-NEXT: v_mul_f32_e64 v3, 0x2f800000, |v1|
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-NEXT: v_floor_f32_e32 v2, v2
; GFX11-SDAG-NEXT: v_floor_f32_e32 v3, v3
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-NEXT: v_fma_f32 v4, 0xcf800000, v2, |v0|
; GFX11-SDAG-NEXT: v_fma_f32 v5, 0xcf800000, v3, |v1|
; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v0, 31, v0
; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v1, 31, v1
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-NEXT: v_xor_b32_e32 v7, v2, v0
; GFX11-SDAG-NEXT: v_xor_b32_e32 v4, v4, v0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-NEXT: v_xor_b32_e32 v5, v5, v1
; GFX11-SDAG-NEXT: v_xor_b32_e32 v8, v3, v1
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_sub_co_u32 v2, vcc_lo, v4, v0
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v3, null, v7, v0, vcc_lo
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v5, v1
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v1, null, v8, v1, vcc_lo
; GFX11-SDAG-NEXT: global_store_b128 v6, v[0:3], s[0:1]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_sint_v2i64:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_trunc_f32_e32 v0, s2
; GFX11-GISEL-NEXT: v_trunc_f32_e32 v2, s3
; GFX11-GISEL-NEXT: s_ashr_i32 s6, s2, 31
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: s_mov_b32 s7, s6
; GFX11-GISEL-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0|
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_mul_f32_e64 v3, 0x2f800000, |v2|
; GFX11-GISEL-NEXT: v_floor_f32_e32 v1, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_floor_f32_e32 v3, v3
; GFX11-GISEL-NEXT: v_fma_f32 v0, 0xcf800000, v1, |v0|
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_fma_f32 v2, 0xcf800000, v3, |v2|
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v1
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s9, v3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v2
; GFX11-GISEL-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s8, v0
; GFX11-GISEL-NEXT: s_sub_u32 s4, s4, s6
; GFX11-GISEL-NEXT: s_subb_u32 s5, s5, s6
; GFX11-GISEL-NEXT: s_ashr_i32 s2, s3, 31
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_mov_b32 s3, s2
; GFX11-GISEL-NEXT: s_xor_b64 s[6:7], s[8:9], s[2:3]
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_sub_u32 s6, s6, s2
; GFX11-GISEL-NEXT: s_subb_u32 s7, s7, s2
; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
; GFX11-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
; EG-LABEL: fp_to_sint_v2i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 74, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: MOV * T0.W, literal.x,
; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT: BFE_UINT T0.Z, KC0[3].X, literal.x, PV.W,
; EG-NEXT: BFE_UINT T0.W, KC0[2].W, literal.x, PV.W,
; EG-NEXT: AND_INT * T1.Z, KC0[2].W, literal.y,
; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT: ADD_INT T1.W, PV.W, literal.x,
; EG-NEXT: ADD_INT * T2.W, PV.Z, literal.x,
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: AND_INT T0.X, PS, literal.x,
; EG-NEXT: AND_INT T0.Y, PV.W, literal.x,
; EG-NEXT: OR_INT T1.Z, T1.Z, literal.y,
; EG-NEXT: SUB_INT T3.W, literal.z, T0.W,
; EG-NEXT: AND_INT * T4.W, KC0[3].X, literal.w,
; EG-NEXT: 31(4.344025e-44), 8388608(1.175494e-38)
; EG-NEXT: 150(2.101948e-43), 8388607(1.175494e-38)
; EG-NEXT: OR_INT T1.X, PS, literal.x,
; EG-NEXT: AND_INT T1.Y, PV.W, literal.y,
; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PV.Z, PV.W,
; EG-NEXT: LSHL T3.W, PV.Z, PV.Y,
; EG-NEXT: AND_INT * T4.W, T1.W, literal.y,
; EG-NEXT: 8388608(1.175494e-38), 32(4.484155e-44)
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T2.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: LSHL T5.W, PV.X, T0.X,
; EG-NEXT: AND_INT * T6.W, T2.W, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T0.X, PS, PV.W, 0.0,
; EG-NEXT: NOT_INT T1.Y, T1.W,
; EG-NEXT: SUB_INT T3.Z, literal.x, T0.Z,
; EG-NEXT: NOT_INT T1.W, T2.W, BS:VEC_120/SCL_212
; EG-NEXT: LSHR * T2.W, T1.X, 1,
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: LSHR T2.X, T1.Z, 1,
; EG-NEXT: ADD_INT T2.Y, T0.Z, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, PS, PV.W,
; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, T1.X, PV.Z,
; EG-NEXT: AND_INT * T2.W, PV.Z, literal.y,
; EG-NEXT: -127(nan), 32(4.484155e-44)
; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T3.Y, T6.W, PV.Z, T5.W, BS:VEC_021/SCL_122
; EG-NEXT: SETGT_INT T0.Z, PV.Y, literal.x,
; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, PV.X, T1.Y,
; EG-NEXT: ADD_INT * T0.W, T0.W, literal.y,
; EG-NEXT: 23(3.222986e-44), -127(nan)
; EG-NEXT: CNDE_INT T2.X, T4.W, PV.W, T3.W,
; EG-NEXT: SETGT_INT T1.Y, PS, literal.x,
; EG-NEXT: CNDE_INT T1.Z, PV.Z, 0.0, PV.Y,
; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.X, T0.X,
; EG-NEXT: ASHR * T2.W, KC0[3].X, literal.y,
; EG-NEXT: 23(3.222986e-44), 31(4.344025e-44)
; EG-NEXT: XOR_INT T0.X, PV.W, PS,
; EG-NEXT: XOR_INT T3.Y, PV.Z, PS,
; EG-NEXT: CNDE_INT T0.Z, PV.Y, 0.0, PV.X,
; EG-NEXT: CNDE_INT T1.W, PV.Y, T2.Z, T0.Y,
; EG-NEXT: ASHR * T3.W, KC0[2].W, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: XOR_INT T0.Y, PV.W, PS,
; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,
; EG-NEXT: SUB_INT T1.W, PV.Y, T2.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W,
; EG-NEXT: SUB_INT T1.Y, PV.W, PS,
; EG-NEXT: SETGT_INT T1.Z, 0.0, T2.Y,
; EG-NEXT: SUB_INT T1.W, PV.Z, T3.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W,
; EG-NEXT: SUB_INT T0.Z, PV.W, PS,
; EG-NEXT: SETGT_INT T0.W, 0.0, T0.W,
; EG-NEXT: CNDE_INT * T1.W, PV.Z, PV.Y, 0.0,
; EG-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W,
; EG-NEXT: CNDE_INT T1.Z, T1.Z, PV.W, 0.0,
; EG-NEXT: SUB_INT * T2.W, T0.Y, T3.W,
; EG-NEXT: CNDE_INT T1.X, T0.W, PV.W, 0.0,
; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%conv = fptosi <2 x float> %x to <2 x i64>
store <2 x i64> %conv, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fp_to_sint_v4i64(ptr addrspace(1) %out, <4 x float> %x) {
; SI-LABEL: fp_to_sint_v4i64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s4, 0x2f800000
; SI-NEXT: s_mov_b32 s5, 0xcf800000
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_trunc_f32_e32 v0, s9
; SI-NEXT: v_mul_f32_e64 v1, |v0|, s4
; SI-NEXT: v_floor_f32_e32 v1, v1
; SI-NEXT: v_fma_f32 v2, v1, s5, |v0|
; SI-NEXT: v_cvt_u32_f32_e32 v2, v2
; SI-NEXT: v_trunc_f32_e32 v4, s8
; SI-NEXT: v_cvt_u32_f32_e32 v1, v1
; SI-NEXT: v_mul_f32_e64 v3, |v4|, s4
; SI-NEXT: v_floor_f32_e32 v3, v3
; SI-NEXT: v_ashrrev_i32_e32 v0, 31, v0
; SI-NEXT: v_cvt_u32_f32_e32 v5, v3
; SI-NEXT: v_fma_f32 v3, v3, s5, |v4|
; SI-NEXT: v_xor_b32_e32 v2, v2, v0
; SI-NEXT: v_cvt_u32_f32_e32 v6, v3
; SI-NEXT: v_xor_b32_e32 v1, v1, v0
; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
; SI-NEXT: v_subb_u32_e32 v3, vcc, v1, v0, vcc
; SI-NEXT: v_ashrrev_i32_e32 v1, 31, v4
; SI-NEXT: v_xor_b32_e32 v4, v5, v1
; SI-NEXT: v_trunc_f32_e32 v5, s11
; SI-NEXT: v_xor_b32_e32 v0, v6, v1
; SI-NEXT: v_mul_f32_e64 v6, |v5|, s4
; SI-NEXT: v_floor_f32_e32 v6, v6
; SI-NEXT: v_cvt_u32_f32_e32 v7, v6
; SI-NEXT: v_fma_f32 v6, v6, s5, |v5|
; SI-NEXT: v_cvt_u32_f32_e32 v6, v6
; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; SI-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc
; SI-NEXT: v_ashrrev_i32_e32 v4, 31, v5
; SI-NEXT: v_trunc_f32_e32 v8, s10
; SI-NEXT: v_xor_b32_e32 v5, v6, v4
; SI-NEXT: v_mul_f32_e64 v6, |v8|, s4
; SI-NEXT: v_floor_f32_e32 v6, v6
; SI-NEXT: v_cvt_u32_f32_e32 v9, v6
; SI-NEXT: v_fma_f32 v6, v6, s5, |v8|
; SI-NEXT: v_cvt_u32_f32_e32 v10, v6
; SI-NEXT: v_xor_b32_e32 v7, v7, v4
; SI-NEXT: v_sub_i32_e32 v6, vcc, v5, v4
; SI-NEXT: v_ashrrev_i32_e32 v5, 31, v8
; SI-NEXT: v_subb_u32_e32 v7, vcc, v7, v4, vcc
; SI-NEXT: v_xor_b32_e32 v4, v10, v5
; SI-NEXT: v_xor_b32_e32 v8, v9, v5
; SI-NEXT: v_sub_i32_e32 v4, vcc, v4, v5
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_subb_u32_e32 v5, vcc, v8, v5, vcc
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fp_to_sint_v4i64:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT: s_mov_b32 s4, 0x2f800000
; VI-NEXT: s_mov_b32 s5, 0xcf800000
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_trunc_f32_e32 v0, s9
; VI-NEXT: v_mul_f32_e64 v1, |v0|, s4
; VI-NEXT: v_floor_f32_e32 v1, v1
; VI-NEXT: v_fma_f32 v2, v1, s5, |v0|
; VI-NEXT: v_cvt_u32_f32_e32 v2, v2
; VI-NEXT: v_trunc_f32_e32 v4, s8
; VI-NEXT: v_cvt_u32_f32_e32 v1, v1
; VI-NEXT: v_mul_f32_e64 v3, |v4|, s4
; VI-NEXT: v_floor_f32_e32 v3, v3
; VI-NEXT: v_ashrrev_i32_e32 v0, 31, v0
; VI-NEXT: v_cvt_u32_f32_e32 v5, v3
; VI-NEXT: v_fma_f32 v3, v3, s5, |v4|
; VI-NEXT: v_xor_b32_e32 v2, v2, v0
; VI-NEXT: v_cvt_u32_f32_e32 v6, v3
; VI-NEXT: v_xor_b32_e32 v1, v1, v0
; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0
; VI-NEXT: v_subb_u32_e32 v3, vcc, v1, v0, vcc
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v4
; VI-NEXT: v_xor_b32_e32 v4, v5, v1
; VI-NEXT: v_trunc_f32_e32 v5, s11
; VI-NEXT: v_xor_b32_e32 v0, v6, v1
; VI-NEXT: v_mul_f32_e64 v6, |v5|, s4
; VI-NEXT: v_floor_f32_e32 v6, v6
; VI-NEXT: v_cvt_u32_f32_e32 v7, v6
; VI-NEXT: v_fma_f32 v6, v6, s5, |v5|
; VI-NEXT: v_cvt_u32_f32_e32 v6, v6
; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
; VI-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc
; VI-NEXT: v_ashrrev_i32_e32 v4, 31, v5
; VI-NEXT: v_trunc_f32_e32 v8, s10
; VI-NEXT: v_xor_b32_e32 v5, v6, v4
; VI-NEXT: v_mul_f32_e64 v6, |v8|, s4
; VI-NEXT: v_floor_f32_e32 v6, v6
; VI-NEXT: v_cvt_u32_f32_e32 v9, v6
; VI-NEXT: v_fma_f32 v6, v6, s5, |v8|
; VI-NEXT: v_cvt_u32_f32_e32 v10, v6
; VI-NEXT: v_xor_b32_e32 v7, v7, v4
; VI-NEXT: v_sub_u32_e32 v6, vcc, v5, v4
; VI-NEXT: v_ashrrev_i32_e32 v5, 31, v8
; VI-NEXT: v_subb_u32_e32 v7, vcc, v7, v4, vcc
; VI-NEXT: v_xor_b32_e32 v4, v10, v5
; VI-NEXT: v_xor_b32_e32 v8, v9, v5
; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v5
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: v_subb_u32_e32 v5, vcc, v8, v5, vcc
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: fp_to_sint_v4i64:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_clause 0x1
; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
; GFX11-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v8, 0
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_trunc_f32_e32 v0, s1
; GFX11-SDAG-NEXT: v_trunc_f32_e32 v2, s3
; GFX11-SDAG-NEXT: v_trunc_f32_e32 v3, s2
; GFX11-SDAG-NEXT: v_trunc_f32_e32 v1, s0
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-NEXT: v_mul_f32_e64 v4, 0x2f800000, |v0|
; GFX11-SDAG-NEXT: v_mul_f32_e64 v7, 0x2f800000, |v2|
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-NEXT: v_mul_f32_e64 v11, 0x2f800000, |v3|
; GFX11-SDAG-NEXT: v_mul_f32_e64 v6, 0x2f800000, |v1|
; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v5, 31, v0
; GFX11-SDAG-NEXT: v_floor_f32_e32 v4, v4
; GFX11-SDAG-NEXT: v_floor_f32_e32 v7, v7
; GFX11-SDAG-NEXT: v_floor_f32_e32 v11, v11
; GFX11-SDAG-NEXT: v_floor_f32_e32 v6, v6
; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v10, 31, v2
; GFX11-SDAG-NEXT: v_fma_f32 v0, 0xcf800000, v4, |v0|
; GFX11-SDAG-NEXT: v_fma_f32 v2, 0xcf800000, v7, |v2|
; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v12, 31, v3
; GFX11-SDAG-NEXT: v_fma_f32 v3, 0xcf800000, v11, |v3|
; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v9, 31, v1
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-SDAG-NEXT: v_fma_f32 v1, 0xcf800000, v6, |v1|
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v13, v4
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v4, v6
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v6, v7
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-SDAG-NEXT: v_xor_b32_e32 v0, v0, v5
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v7, v11
; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX11-SDAG-NEXT: v_xor_b32_e32 v11, v13, v5
; GFX11-SDAG-NEXT: v_xor_b32_e32 v13, v4, v9
; GFX11-SDAG-NEXT: v_xor_b32_e32 v4, v6, v10
; GFX11-SDAG-NEXT: v_xor_b32_e32 v6, v2, v10
; GFX11-SDAG-NEXT: v_xor_b32_e32 v15, v3, v12
; GFX11-SDAG-NEXT: v_sub_co_u32 v2, vcc_lo, v0, v5
; GFX11-SDAG-NEXT: v_xor_b32_e32 v14, v7, v12
; GFX11-SDAG-NEXT: v_xor_b32_e32 v1, v1, v9
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v3, null, v11, v5, vcc_lo
; GFX11-SDAG-NEXT: v_sub_co_u32 v6, vcc_lo, v6, v10
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v7, null, v4, v10, vcc_lo
; GFX11-SDAG-NEXT: v_sub_co_u32 v4, vcc_lo, v15, v12
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v5, null, v14, v12, vcc_lo
; GFX11-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v1, v9
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e64 v1, null, v13, v9, vcc_lo
; GFX11-SDAG-NEXT: s_clause 0x1
; GFX11-SDAG-NEXT: global_store_b128 v8, v[4:7], s[4:5] offset:16
; GFX11-SDAG-NEXT: global_store_b128 v8, v[0:3], s[4:5]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_sint_v4i64:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_clause 0x1
; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
; GFX11-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_trunc_f32_e32 v0, s0
; GFX11-GISEL-NEXT: v_trunc_f32_e32 v1, s1
; GFX11-GISEL-NEXT: v_trunc_f32_e32 v2, s2
; GFX11-GISEL-NEXT: v_trunc_f32_e32 v4, s3
; GFX11-GISEL-NEXT: s_ashr_i32 s6, s0, 31
; GFX11-GISEL-NEXT: v_mul_f32_e64 v3, 0x2f800000, |v0|
; GFX11-GISEL-NEXT: v_mul_f32_e64 v5, 0x2f800000, |v1|
; GFX11-GISEL-NEXT: v_mul_f32_e64 v6, 0x2f800000, |v2|
; GFX11-GISEL-NEXT: v_mul_f32_e64 v7, 0x2f800000, |v4|
; GFX11-GISEL-NEXT: s_mov_b32 s7, s6
; GFX11-GISEL-NEXT: v_floor_f32_e32 v3, v3
; GFX11-GISEL-NEXT: v_floor_f32_e32 v5, v5
; GFX11-GISEL-NEXT: v_floor_f32_e32 v6, v6
; GFX11-GISEL-NEXT: v_floor_f32_e32 v7, v7
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_fma_f32 v0, 0xcf800000, v3, |v0|
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-GISEL-NEXT: v_fma_f32 v1, 0xcf800000, v5, |v1|
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX11-GISEL-NEXT: v_fma_f32 v2, 0xcf800000, v6, |v2|
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s9, v3
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s11, v5
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s8, v0
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v1
; GFX11-GISEL-NEXT: v_fma_f32 v4, 0xcf800000, v7, |v4|
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v7
; GFX11-GISEL-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7]
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s10, v0
; GFX11-GISEL-NEXT: s_sub_u32 s8, s8, s6
; GFX11-GISEL-NEXT: s_subb_u32 s9, s9, s6
; GFX11-GISEL-NEXT: s_ashr_i32 s0, s1, 31
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s7, v6
; GFX11-GISEL-NEXT: s_mov_b32 s1, s0
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s6, v2
; GFX11-GISEL-NEXT: s_xor_b64 s[10:11], s[10:11], s[0:1]
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v4
; GFX11-GISEL-NEXT: s_sub_u32 s10, s10, s0
; GFX11-GISEL-NEXT: s_subb_u32 s11, s11, s0
; GFX11-GISEL-NEXT: s_ashr_i32 s12, s2, 31
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s15, v1
; GFX11-GISEL-NEXT: s_mov_b32 s13, s12
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s14, v0
; GFX11-GISEL-NEXT: s_xor_b64 s[0:1], s[6:7], s[12:13]
; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
; GFX11-GISEL-NEXT: s_sub_u32 s0, s0, s12
; GFX11-GISEL-NEXT: s_subb_u32 s1, s1, s12
; GFX11-GISEL-NEXT: s_ashr_i32 s6, s3, 31
; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
; GFX11-GISEL-NEXT: s_mov_b32 s7, s6
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_xor_b64 s[2:3], s[14:15], s[6:7]
; GFX11-GISEL-NEXT: s_sub_u32 s2, s2, s6
; GFX11-GISEL-NEXT: s_subb_u32 s3, s3, s6
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v7, s3
; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v5, s1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, s0
; GFX11-GISEL-NEXT: s_clause 0x1
; GFX11-GISEL-NEXT: global_store_b128 v8, v[0:3], s[4:5]
; GFX11-GISEL-NEXT: global_store_b128 v8, v[4:7], s[4:5] offset:16
; GFX11-GISEL-NEXT: s_endpgm
;
; EG-LABEL: fp_to_sint_v4i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 102, @6, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 49, @109, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T1.X, 0
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 6:
; EG-NEXT: MOV * T0.W, literal.x,
; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT: BFE_UINT T1.W, KC0[4].X, literal.x, PV.W,
; EG-NEXT: AND_INT * T2.W, KC0[4].X, literal.y,
; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT: OR_INT T2.W, PS, literal.x,
; EG-NEXT: ADD_INT * T3.W, PV.W, literal.y,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: ADD_INT T0.X, T1.W, literal.x,
; EG-NEXT: AND_INT T0.Y, PS, literal.y,
; EG-NEXT: SUB_INT T0.Z, literal.z, T1.W,
; EG-NEXT: NOT_INT T1.W, PS,
; EG-NEXT: LSHR * T4.W, PV.W, 1,
; EG-NEXT: -127(nan), 31(4.344025e-44)
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
; EG-NEXT: AND_INT T1.Y, PV.Z, literal.x,
; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, T2.W, PV.Z,
; EG-NEXT: LSHL T1.W, T2.W, PV.Y,
; EG-NEXT: AND_INT * T2.W, T3.W, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: CNDE_INT T1.W, PS, PV.X, PV.W,
; EG-NEXT: SETGT_INT * T2.W, T0.X, literal.x,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T1.Z, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T1.W, PS, PV.Z, PV.Y,
; EG-NEXT: ASHR * T2.W, KC0[4].X, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: XOR_INT T0.Z, PV.W, PS,
; EG-NEXT: BFE_UINT T1.W, KC0[3].Z, literal.x, T0.W,
; EG-NEXT: XOR_INT * T3.W, PV.Z, PS,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: AND_INT T0.Y, KC0[3].Z, literal.x,
; EG-NEXT: ADD_INT T1.Z, PV.W, literal.y,
; EG-NEXT: SUB_INT T3.W, PS, T2.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.Z, T2.W,
; EG-NEXT: 8388607(1.175494e-38), -150(nan)
; EG-NEXT: SUB_INT T1.Y, PV.W, PS,
; EG-NEXT: AND_INT T2.Z, PV.Z, literal.x,
; EG-NEXT: BFE_UINT T3.W, KC0[3].Y, literal.y, T0.W,
; EG-NEXT: OR_INT * T4.W, PV.Y, literal.z,
; EG-NEXT: 31(4.344025e-44), 23(3.222986e-44)
; EG-NEXT: 8388608(1.175494e-38), 0(0.000000e+00)
; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X,
; EG-NEXT: AND_INT T0.Y, KC0[3].Y, literal.x,
; EG-NEXT: ADD_INT T3.Z, PV.W, literal.y,
; EG-NEXT: LSHL T5.W, PS, PV.Z,
; EG-NEXT: AND_INT * T6.W, T1.Z, literal.z,
; EG-NEXT: 8388607(1.175494e-38), -150(nan)
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: BFE_UINT T1.X, KC0[3].W, literal.x, T0.W,
; EG-NEXT: CNDE_INT T2.Y, PS, PV.W, 0.0,
; EG-NEXT: AND_INT T2.Z, PV.Z, literal.y,
; EG-NEXT: OR_INT T0.W, PV.Y, literal.z,
; EG-NEXT: SUB_INT * T7.W, literal.w, T1.W,
; EG-NEXT: 23(3.222986e-44), 31(4.344025e-44)
; EG-NEXT: 8388608(1.175494e-38), 150(2.101948e-43)
; EG-NEXT: NOT_INT T2.X, T1.Z,
; EG-NEXT: LSHR T0.Y, T4.W, 1,
; EG-NEXT: AND_INT T1.Z, PS, literal.x,
; EG-NEXT: BIT_ALIGN_INT T4.W, 0.0, T4.W, PS,
; EG-NEXT: ADD_INT * T1.W, T1.W, literal.y,
; EG-NEXT: 32(4.484155e-44), -127(nan)
; EG-NEXT: SETGT_INT T3.X, PS, literal.x,
; EG-NEXT: CNDE_INT T3.Y, PV.Z, PV.W, 0.0,
; EG-NEXT: BIT_ALIGN_INT T1.Z, 0.0, PV.Y, PV.X,
; EG-NEXT: LSHL T4.W, T0.W, T2.Z,
; EG-NEXT: AND_INT * T7.W, T3.Z, literal.y,
; EG-NEXT: 23(3.222986e-44), 32(4.484155e-44)
; EG-NEXT: AND_INT T2.X, KC0[3].W, literal.x,
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T1.Z, T6.W, PV.Z, T5.W,
; EG-NEXT: CNDE_INT T5.W, PV.X, PV.Y, T2.Y,
; EG-NEXT: ASHR * T6.W, KC0[3].Z, literal.y,
; EG-NEXT: 8388607(1.175494e-38), 31(4.344025e-44)
; EG-NEXT: XOR_INT T4.X, PV.W, PS,
; EG-NEXT: SUB_INT T2.Y, literal.x, T3.W,
; EG-NEXT: NOT_INT T2.Z, T3.Z,
; EG-NEXT: LSHR T5.W, T0.W, 1,
; EG-NEXT: CNDE_INT * T8.W, T3.X, 0.0, PV.Z, BS:VEC_021/SCL_122
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: XOR_INT T3.X, PS, T6.W,
; EG-NEXT: ADD_INT T3.Y, T3.W, literal.x,
; EG-NEXT: BIT_ALIGN_INT T1.Z, 0.0, PV.W, PV.Z,
; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, T0.W, PV.Y, BS:VEC_021/SCL_122
; EG-NEXT: AND_INT * T3.W, PV.Y, literal.y,
; EG-NEXT: -127(nan), 32(4.484155e-44)
; EG-NEXT: CNDE_INT T5.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T2.Y, T7.W, PV.Z, T4.W,
; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,
; EG-NEXT: SUB_INT T0.W, PV.X, T6.W,
; EG-NEXT: SUBB_UINT * T3.W, T4.X, T6.W,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: SUB_INT T3.X, PV.W, PS,
; EG-NEXT: CNDE_INT T2.Y, PV.Z, 0.0, PV.Y,
; EG-NEXT: CNDE_INT T1.Z, PV.Z, PV.X, T0.Y,
; EG-NEXT: OR_INT T0.W, T2.X, literal.x,
; EG-NEXT: ADD_INT * T3.W, T1.X, literal.y,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: ADD_INT * T2.X, T1.X, literal.x,
; EG-NEXT: -127(nan), 0(0.000000e+00)
; EG-NEXT: ALU clause starting at 109:
; EG-NEXT: AND_INT T0.Y, T3.W, literal.x,
; EG-NEXT: SUB_INT T2.Z, literal.y, T1.X,
; EG-NEXT: NOT_INT T4.W, T3.W,
; EG-NEXT: LSHR * T5.W, T0.W, 1,
; EG-NEXT: 31(4.344025e-44), 150(2.101948e-43)
; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
; EG-NEXT: AND_INT T4.Y, PV.Z, literal.x,
; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, T0.W, PV.Z,
; EG-NEXT: LSHL T0.W, T0.W, PV.Y,
; EG-NEXT: AND_INT * T3.W, T3.W, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: ASHR T5.X, KC0[3].Y, literal.x,
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T2.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: CNDE_INT T0.W, PS, PV.X, PV.W,
; EG-NEXT: SETGT_INT * T3.W, T2.X, literal.y,
; EG-NEXT: 31(4.344025e-44), 23(3.222986e-44)
; EG-NEXT: CNDE_INT T1.X, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T0.Y, PS, PV.Z, PV.Y,
; EG-NEXT: ASHR T2.Z, KC0[3].W, literal.x,
; EG-NEXT: XOR_INT T0.W, T1.Z, PV.X,
; EG-NEXT: XOR_INT * T3.W, T2.Y, PV.X,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: SETGT_INT T6.X, 0.0, T1.W,
; EG-NEXT: SUB_INT T2.Y, PS, T5.X,
; EG-NEXT: SUBB_UINT T1.Z, PV.W, T5.X,
; EG-NEXT: XOR_INT T1.W, PV.Y, PV.Z,
; EG-NEXT: XOR_INT * T3.W, PV.X, PV.Z,
; EG-NEXT: SUB_INT T1.X, PS, T2.Z,
; EG-NEXT: SUBB_UINT T0.Y, PV.W, T2.Z,
; EG-NEXT: SUB_INT T1.Z, PV.Y, PV.Z,
; EG-NEXT: SETGT_INT T3.W, 0.0, T3.Y,
; EG-NEXT: CNDE_INT * T4.W, PV.X, T3.X, 0.0,
; EG-NEXT: SUB_INT T3.X, T4.X, T6.W,
; EG-NEXT: CNDE_INT T4.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT T1.Z, PV.X, PV.Y,
; EG-NEXT: SETGT_INT T5.W, 0.0, T2.X,
; EG-NEXT: CNDE_INT * T6.W, T0.X, T1.Y, 0.0,
; EG-NEXT: CNDE_INT T6.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: CNDE_INT T4.Z, T6.X, PV.X, 0.0,
; EG-NEXT: SUB_INT T2.W, T0.Z, T2.W,
; EG-NEXT: SUB_INT * T0.W, T0.W, T5.X,
; EG-NEXT: CNDE_INT T4.X, T3.W, PS, 0.0,
; EG-NEXT: CNDE_INT T6.Z, T0.X, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T1.W, T2.Z, BS:VEC_120/SCL_212
; EG-NEXT: CNDE_INT T6.X, T5.W, PV.W, 0.0,
; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT: ADD_INT * T1.X, PS, literal.x,
; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)
%conv = fptosi <4 x float> %x to <4 x i64>
store <4 x i64> %conv, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fp_to_uint_f32_to_i1(ptr addrspace(1) %out, float %in) #0 {
; SI-LABEL: fp_to_uint_f32_to_i1:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s6, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, s6
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fp_to_uint_f32_to_i1:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s6, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, s6
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: fp_to_uint_f32_to_i1:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_clause 0x1
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_eq_f32_e64 s2, -1.0, s2
; GFX11-SDAG-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-SDAG-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-SDAG-NEXT: global_store_b8 v0, v1, s[0:1]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_uint_f32_to_i1:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_clause 0x1
; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s2
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX11-GISEL-NEXT: s_and_b32 s2, s2, 1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-NEXT: global_store_b8 v1, v0, s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
; EG-LABEL: fp_to_uint_f32_to_i1:
; EG: ; %bb.0:
; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
; EG-NEXT: SETE_DX10 * T1.W, KC0[2].Z, literal.y,
; EG-NEXT: 3(4.203895e-45), -1082130432(-1.000000e+00)
; EG-NEXT: AND_INT T1.W, PS, 1,
; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
; EG-NEXT: LSHL T0.X, PV.W, PS,
; EG-NEXT: LSHL * T0.W, literal.x, PS,
; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
; EG-NEXT: MOV T0.Y, 0.0,
; EG-NEXT: MOV * T0.Z, 0.0,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%conv = fptosi float %in to i1
store i1 %conv, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(ptr addrspace(1) %out, float %in) #0 {
; SI-LABEL: fp_to_uint_fabs_f32_to_i1:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s6, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, |s6|
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fp_to_uint_fabs_f32_to_i1:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s6, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, |s6|
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: fp_to_uint_fabs_f32_to_i1:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_clause 0x1
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_eq_f32_e64 s2, -1.0, |s2|
; GFX11-SDAG-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-SDAG-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-SDAG-NEXT: global_store_b8 v0, v1, s[0:1]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_uint_fabs_f32_to_i1:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_clause 0x1
; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e64 v0, |s2|
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX11-GISEL-NEXT: s_and_b32 s2, s2, 1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-NEXT: global_store_b8 v1, v0, s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
; EG-LABEL: fp_to_uint_fabs_f32_to_i1:
; EG: ; %bb.0:
; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
; EG-NEXT: SETE_DX10 * T1.W, |KC0[2].Z|, literal.y,
; EG-NEXT: 3(4.203895e-45), -1082130432(-1.000000e+00)
; EG-NEXT: AND_INT T1.W, PS, 1,
; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
; EG-NEXT: LSHL T0.X, PV.W, PS,
; EG-NEXT: LSHL * T0.W, literal.x, PS,
; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
; EG-NEXT: MOV T0.Y, 0.0,
; EG-NEXT: MOV * T0.Z, 0.0,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%in.fabs = call float @llvm.fabs.f32(float %in)
%conv = fptosi float %in.fabs to i1
store i1 %conv, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fp_to_sint_f32_i16(ptr addrspace(1) %out, float %in) #0 {
; SI-LABEL: fp_to_sint_f32_i16:
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_cvt_i32_f32_e32 v0, s2
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fp_to_sint_f32_i16:
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cvt_i32_f32_e32 v0, s2
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: fp_to_sint_f32_i16:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_clause 0x1
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v0, s2
; GFX11-SDAG-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_sint_f32_i16:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_clause 0x1
; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s2
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX11-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
; GFX11-GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
; EG-LABEL: fp_to_sint_f32_i16:
; EG: ; %bb.0:
; EG-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: TRUNC T0.W, KC0[2].Z,
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
; EG-NEXT: FLT_TO_INT * T0.W, PV.W,
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
; EG-NEXT: LSHL T0.X, PV.W, PS,
; EG-NEXT: LSHL * T0.W, literal.x, PS,
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
; EG-NEXT: MOV T0.Y, 0.0,
; EG-NEXT: MOV * T0.Z, 0.0,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%sint = fptosi float %in to i16
store i16 %sint, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fp_to_sint_v2f32_to_v2i16(ptr addrspace(1) %out, <2 x float> %in) {
; SI-LABEL: fp_to_sint_v2f32_to_v2i16:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_cvt_i32_f32_e32 v0, s3
; SI-NEXT: v_cvt_i32_f32_e32 v1, s2
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fp_to_sint_v2f32_to_v2i16:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3
; VI-NEXT: v_cvt_i32_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; VI-NEXT: v_cvt_i32_f32_e32 v1, s2
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: fp_to_sint_v2f32_to_v2i16:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cvt_pk_i16_f32 v1, s2, s3
; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_sint_v2f32_to_v2i16:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s2
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v1, s3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s2, s2, s3
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
; EG-LABEL: fp_to_sint_v2f32_to_v2i16:
; EG: ; %bb.0:
; EG-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: TRUNC T0.W, KC0[2].W,
; EG-NEXT: TRUNC * T1.W, KC0[3].X,
; EG-NEXT: FLT_TO_INT T1.W, PS,
; EG-NEXT: FLT_TO_INT * T0.W, PV.W,
; EG-NEXT: AND_INT T0.W, PS, literal.x,
; EG-NEXT: LSHL * T1.W, PV.W, literal.y,
; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
; EG-NEXT: OR_INT T4.X, PV.W, PS,
; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%sint = fptosi <2 x float> %in to <2 x i16>
store <2 x i16> %sint, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fp_to_sint_f32_to_v2i16(ptr addrspace(1) %out, float %in0, float %in1) {
; SI-LABEL: fp_to_sint_f32_to_v2i16:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_cvt_i32_f32_e32 v0, s3
; SI-NEXT: v_cvt_i32_f32_e32 v1, s2
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fp_to_sint_f32_to_v2i16:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_cvt_i32_f32_e32 v0, s2
; VI-NEXT: v_cvt_i32_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: fp_to_sint_f32_to_v2i16:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cvt_pk_i16_f32 v1, s2, s3
; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_sint_f32_to_v2i16:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s2
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v1, s3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s2, s2, s3
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
; EG-LABEL: fp_to_sint_f32_to_v2i16:
; EG: ; %bb.0:
; EG-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: TRUNC T0.W, KC0[2].W,
; EG-NEXT: TRUNC * T1.W, KC0[2].Z,
; EG-NEXT: FLT_TO_INT T1.W, PS,
; EG-NEXT: FLT_TO_INT * T0.W, PV.W,
; EG-NEXT: LSHL T0.W, PS, literal.x,
; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)
; EG-NEXT: OR_INT T4.X, PV.W, PS,
; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%sint0 = fptosi float %in0 to i16
%sint1 = fptosi float %in1 to i16
%res0 = insertelement <2 x i16> poison, i16 %sint0, i32 0
%res1 = insertelement <2 x i16> %res0, i16 %sint1, i32 1
store <2 x i16> %res1, ptr addrspace(1) %out
ret void
}
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX11: {{.*}}