llvm/test/Transforms/LoopVersioning/preserve-memoryssa.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt -passes='require<memoryssa>,loop-versioning' -verify-memoryssa -S %s | FileCheck %s

define i32 @inner_cfg(ptr %a, ptr %b, i64 %n, i1 %c) {
; CHECK-LABEL: define i32 @inner_cfg(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]], i1 [[C:%.*]]) {
; CHECK-NEXT:  [[LOOP_LVER_CHECK:.*:]]
; CHECK-NEXT:    [[TMP0:%.*]] = shl i64 [[N]], 2
; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP0]]
; CHECK-NEXT:    [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP0]]
; CHECK-NEXT:    [[BOUND0:%.*]] = icmp ult ptr [[B]], [[SCEVGEP1]]
; CHECK-NEXT:    [[BOUND1:%.*]] = icmp ult ptr [[A]], [[SCEVGEP]]
; CHECK-NEXT:    [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
; CHECK-NEXT:    br i1 [[FOUND_CONFLICT]], label %[[LOOP_PH_LVER_ORIG:.*]], label %[[LOOP_PH:.*]]
; CHECK:       [[LOOP_PH_LVER_ORIG]]:
; CHECK-NEXT:    br label %[[LOOP_LVER_ORIG:.*]]
; CHECK:       [[LOOP_LVER_ORIG]]:
; CHECK-NEXT:    [[IV_LVER_ORIG:%.*]] = phi i64 [ 0, %[[LOOP_PH_LVER_ORIG]] ], [ [[IV_NEXT_LVER_ORIG:%.*]], %[[LATCH_LVER_ORIG:.*]] ]
; CHECK-NEXT:    [[GEP_A_LVER_ORIG:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV_LVER_ORIG]]
; CHECK-NEXT:    [[L_LVER_ORIG:%.*]] = load i32, ptr [[GEP_A_LVER_ORIG]], align 4
; CHECK-NEXT:    br i1 [[C]], label %[[THEN_LVER_ORIG:.*]], label %[[LATCH_LVER_ORIG]]
; CHECK:       [[THEN_LVER_ORIG]]:
; CHECK-NEXT:    [[GEP_B_LVER_ORIG:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV_LVER_ORIG]]
; CHECK-NEXT:    store i32 [[L_LVER_ORIG]], ptr [[GEP_B_LVER_ORIG]], align 4
; CHECK-NEXT:    br label %[[LATCH_LVER_ORIG]]
; CHECK:       [[LATCH_LVER_ORIG]]:
; CHECK-NEXT:    [[IV_NEXT_LVER_ORIG]] = add nuw nsw i64 [[IV_LVER_ORIG]], 1
; CHECK-NEXT:    [[EC_LVER_ORIG:%.*]] = icmp eq i64 [[IV_NEXT_LVER_ORIG]], [[N]]
; CHECK-NEXT:    br i1 [[EC_LVER_ORIG]], label %[[EXIT_LOOPEXIT:.*]], label %[[LOOP_LVER_ORIG]]
; CHECK:       [[LOOP_PH]]:
; CHECK-NEXT:    br label %[[LOOP:.*]]
; CHECK:       [[LOOP]]:
; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[LOOP_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
; CHECK-NEXT:    [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
; CHECK-NEXT:    [[L:%.*]] = load i32, ptr [[GEP_A]], align 4, !alias.scope [[META5:![0-9]+]]
; CHECK-NEXT:    br i1 [[C]], label %[[THEN:.*]], label %[[LATCH]]
; CHECK:       [[THEN]]:
; CHECK-NEXT:    [[GEP_B:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]
; CHECK-NEXT:    store i32 [[L]], ptr [[GEP_B]], align 4, !alias.scope [[META8:![0-9]+]], !noalias [[META5]]
; CHECK-NEXT:    br label %[[LATCH]]
; CHECK:       [[LATCH]]:
; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-NEXT:    br i1 [[EC]], label %[[EXIT_LOOPEXIT2:.*]], label %[[LOOP]]
; CHECK:       [[EXIT_LOOPEXIT]]:
; CHECK-NEXT:    br label %[[EXIT:.*]]
; CHECK:       [[EXIT_LOOPEXIT2]]:
; CHECK-NEXT:    br label %[[EXIT]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    [[LV:%.*]] = load i32, ptr [[A]], align 4
; CHECK-NEXT:    ret i32 [[LV]]
;
entry:
  br label %loop

loop:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ]
  %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv
  %l = load i32, ptr %gep.a, align 4
  br i1 %c, label %then, label %latch

then:
  %gep.b = getelementptr inbounds i32, ptr %b, i64 %iv
  store i32 %l, ptr %gep.b, align 4
  br label %latch

latch:
  %iv.next = add nuw nsw i64 %iv, 1
  %ec = icmp eq i64 %iv.next, %n
  br i1 %ec, label %exit, label %loop

exit:
  %lv = load i32, ptr %a, align 4
  ret i32 %lv
}

; Versioning the inner loop of a nest: the exit block is inside the outer loop,
; so the new exit edges feed a MemoryPhi that already has other incoming values.
define void @nested(ptr %a, ptr %b, i64 %n) {
; CHECK-LABEL: define void @nested(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    [[TMP0:%.*]] = shl i64 [[N]], 2
; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP0]]
; CHECK-NEXT:    [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP0]]
; CHECK-NEXT:    br label %[[INNER_LVER_CHECK:.*]]
; CHECK:       [[INNER_LVER_CHECK]]:
; CHECK-NEXT:    [[J:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[J_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
; CHECK-NEXT:    store i32 0, ptr [[A]], align 4
; CHECK-NEXT:    [[BOUND0:%.*]] = icmp ult ptr [[B]], [[SCEVGEP1]]
; CHECK-NEXT:    [[BOUND1:%.*]] = icmp ult ptr [[A]], [[SCEVGEP]]
; CHECK-NEXT:    [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
; CHECK-NEXT:    br i1 [[FOUND_CONFLICT]], label %[[INNER_PH_LVER_ORIG:.*]], label %[[INNER_PH:.*]]
; CHECK:       [[INNER_PH_LVER_ORIG]]:
; CHECK-NEXT:    br label %[[INNER_LVER_ORIG:.*]]
; CHECK:       [[INNER_LVER_ORIG]]:
; CHECK-NEXT:    [[IV_LVER_ORIG:%.*]] = phi i64 [ 0, %[[INNER_PH_LVER_ORIG]] ], [ [[IV_NEXT_LVER_ORIG:%.*]], %[[INNER_LVER_ORIG]] ]
; CHECK-NEXT:    [[GEP_A_LVER_ORIG:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV_LVER_ORIG]]
; CHECK-NEXT:    [[L_LVER_ORIG:%.*]] = load i32, ptr [[GEP_A_LVER_ORIG]], align 4
; CHECK-NEXT:    [[GEP_B_LVER_ORIG:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV_LVER_ORIG]]
; CHECK-NEXT:    store i32 [[L_LVER_ORIG]], ptr [[GEP_B_LVER_ORIG]], align 4
; CHECK-NEXT:    [[IV_NEXT_LVER_ORIG]] = add nuw nsw i64 [[IV_LVER_ORIG]], 1
; CHECK-NEXT:    [[EC_LVER_ORIG:%.*]] = icmp eq i64 [[IV_NEXT_LVER_ORIG]], [[N]]
; CHECK-NEXT:    br i1 [[EC_LVER_ORIG]], label %[[OUTER_LATCH_LOOPEXIT:.*]], label %[[INNER_LVER_ORIG]]
; CHECK:       [[INNER_PH]]:
; CHECK-NEXT:    br label %[[INNER:.*]]
; CHECK:       [[INNER]]:
; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[INNER_PH]] ], [ [[IV_NEXT:%.*]], %[[INNER]] ]
; CHECK-NEXT:    [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
; CHECK-NEXT:    [[L:%.*]] = load i32, ptr [[GEP_A]], align 4, !alias.scope [[META10:![0-9]+]]
; CHECK-NEXT:    [[GEP_B:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]]
; CHECK-NEXT:    store i32 [[L]], ptr [[GEP_B]], align 4, !alias.scope [[META13:![0-9]+]], !noalias [[META10]]
; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-NEXT:    br i1 [[EC]], label %[[OUTER_LATCH_LOOPEXIT2:.*]], label %[[INNER]]
; CHECK:       [[OUTER_LATCH_LOOPEXIT]]:
; CHECK-NEXT:    br label %[[OUTER_LATCH]]
; CHECK:       [[OUTER_LATCH_LOOPEXIT2]]:
; CHECK-NEXT:    br label %[[OUTER_LATCH]]
; CHECK:       [[OUTER_LATCH]]:
; CHECK-NEXT:    store i32 1, ptr [[B]], align 4
; CHECK-NEXT:    [[J_NEXT]] = add nuw nsw i64 [[J]], 1
; CHECK-NEXT:    [[EC_O:%.*]] = icmp eq i64 [[J_NEXT]], [[N]]
; CHECK-NEXT:    br i1 [[EC_O]], label %[[EXIT:.*]], label %[[INNER_LVER_CHECK]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %outer

outer:
  %j = phi i64 [ 0, %entry ], [ %j.next, %outer.latch ]
  store i32 0, ptr %a, align 4
  br label %inner

inner:
  %iv = phi i64 [ 0, %outer ], [ %iv.next, %inner ]
  %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv
  %l = load i32, ptr %gep.a, align 4
  %gep.b = getelementptr inbounds i32, ptr %b, i64 %iv
  store i32 %l, ptr %gep.b, align 4
  %iv.next = add nuw nsw i64 %iv, 1
  %ec = icmp eq i64 %iv.next, %n
  br i1 %ec, label %outer.latch, label %inner

outer.latch:
  store i32 1, ptr %b, align 4
  %j.next = add nuw nsw i64 %j, 1
  %ec.o = icmp eq i64 %j.next, %n
  br i1 %ec.o, label %exit, label %outer

exit:
  ret void
}