llvm/test/CodeGen/AMDGPU/permute.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s

define amdgpu_kernel void @lsh8_or_and(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: lsh8_or_and:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    v_mov_b32_e32 v3, 0x6050400
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v2, v[0:1]
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_perm_b32 v2, v2, s2, v3
; GCN-NEXT:    flat_store_dword v[0:1], v2
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %tmp = load i32, ptr addrspace(1) %gep, align 4
  %tmp2 = shl i32 %tmp, 8
  %tmp3 = and i32 %arg1, 255
  %tmp4 = or i32 %tmp2, %tmp3
  store i32 %tmp4, ptr addrspace(1) %gep, align 4
  ret void
}

define amdgpu_kernel void @lsr24_or_and(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: lsr24_or_and:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    v_mov_b32_e32 v3, 0x7060503
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v2, v[0:1]
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_perm_b32 v2, s2, v2, v3
; GCN-NEXT:    flat_store_dword v[0:1], v2
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %tmp = load i32, ptr addrspace(1) %gep, align 4
  %tmp2 = lshr i32 %tmp, 24
  %tmp3 = and i32 %arg1, 4294967040 ; 0xffffff00
  %tmp4 = or i32 %tmp2, %tmp3
  store i32 %tmp4, ptr addrspace(1) %gep, align 4
  ret void
}

define amdgpu_kernel void @and_or_lsr24(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: and_or_lsr24:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    v_mov_b32_e32 v3, 0x7060503
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v2, v[0:1]
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_perm_b32 v2, v2, s2, v3
; GCN-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
; GCN-NEXT:    flat_store_dword v[0:1], v2
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %tmp = load i32, ptr addrspace(1) %gep, align 4
  %tmp2 = and i32 %tmp, 4294967040 ; 0xffffff00
  %tmp3 = lshr i32 %arg1, 24
  %tmp4 = or i32 %tmp2, %tmp3
  %tmp5 = xor i32 %tmp4, -2147483648
  store i32 %tmp5, ptr addrspace(1) %gep, align 4
  ret void
}

define amdgpu_kernel void @and_or_and(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: and_or_and:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    v_mov_b32_e32 v3, 0x7020500
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v2, v[0:1]
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_perm_b32 v2, v2, s2, v3
; GCN-NEXT:    flat_store_dword v[0:1], v2
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %tmp = load i32, ptr addrspace(1) %gep, align 4
  %tmp2 = and i32 %tmp, -16711936
  %tmp3 = and i32 %arg1, 16711935
  %tmp4 = or i32 %tmp2, %tmp3
  store i32 %tmp4, ptr addrspace(1) %gep, align 4
  ret void
}

; FIXME: produce v_alignbit_b32 v2, v2, s0, 24 instead of v_perm
define amdgpu_kernel void @lsh8_or_lsr24(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: lsh8_or_lsr24:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v2, v[0:1]
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_alignbit_b32 v2, v2, s2, 24
; GCN-NEXT:    flat_store_dword v[0:1], v2
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %tmp = load i32, ptr addrspace(1) %gep, align 4
  %tmp2 = shl i32 %tmp, 8
  %tmp3 = lshr i32 %arg1, 24
  %tmp4 = or i32 %tmp2, %tmp3
  store i32 %tmp4, ptr addrspace(1) %gep, align 4
  ret void
}

define amdgpu_kernel void @lsh16_or_lsr24(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: lsh16_or_lsr24:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    v_mov_b32_e32 v3, 0x5040c03
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v2, v[0:1]
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_perm_b32 v2, v2, s2, v3
; GCN-NEXT:    flat_store_dword v[0:1], v2
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %tmp = load i32, ptr addrspace(1) %gep, align 4
  %tmp2 = shl i32 %tmp, 16
  %tmp3 = lshr i32 %arg1, 24
  %tmp4 = or i32 %tmp2, %tmp3
  store i32 %tmp4, ptr addrspace(1) %gep, align 4
  ret void
}

define amdgpu_kernel void @and_xor_and(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: and_xor_and:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    v_mov_b32_e32 v3, 0x7020104
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v2, v[0:1]
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_perm_b32 v2, v2, s2, v3
; GCN-NEXT:    flat_store_dword v[0:1], v2
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %tmp = load i32, ptr addrspace(1) %gep, align 4
  %tmp2 = and i32 %tmp, -16776961
  %tmp3 = and i32 %arg1, 16776960
  %tmp4 = xor i32 %tmp2, %tmp3
  store i32 %tmp4, ptr addrspace(1) %gep, align 4
  ret void
}

; FIXME here should have been "v_perm_b32" with 0xffff0500 mask.
define amdgpu_kernel void @and_or_or_and(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: and_or_or_and:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v2, v[0:1]
; GCN-NEXT:    s_and_b32 s0, s2, 0xff00
; GCN-NEXT:    s_or_b32 s0, s0, 0xffff0000
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_and_b32_e32 v2, 0xff00ff, v2
; GCN-NEXT:    v_or_b32_e32 v2, s0, v2
; GCN-NEXT:    flat_store_dword v[0:1], v2
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %tmp = load i32, ptr addrspace(1) %gep, align 4
  %and = and i32 %tmp, 16711935     ; 0x00ff00ff
  %tmp1 = and i32 %arg1, 4294967040 ; 0xffffff00
  %tmp2 = or i32 %tmp1, -65536
  %tmp3 = or i32 %tmp2, %and
  store i32 %tmp3, ptr addrspace(1) %gep, align 4
  ret void
}

define amdgpu_kernel void @and_or_and_shl(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: and_or_and_shl:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    v_mov_b32_e32 v3, 0x50c0c00
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v2, v[0:1]
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_perm_b32 v2, v2, s2, v3
; GCN-NEXT:    flat_store_dword v[0:1], v2
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %tmp = load i32, ptr addrspace(1) %gep, align 4
  %tmp2 = shl i32 %tmp, 16
  %tmp3 = and i32 %arg1, 65535
  %tmp4 = or i32 %tmp2, %tmp3
  %and = and i32 %tmp4, 4278190335
  store i32 %and, ptr addrspace(1) %gep, align 4
  ret void
}

define amdgpu_kernel void @or_and_or(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: or_and_or:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    v_mov_b32_e32 v3, 0x7020104
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v2, v[0:1]
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_perm_b32 v2, v2, s2, v3
; GCN-NEXT:    flat_store_dword v[0:1], v2
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %tmp = load i32, ptr addrspace(1) %gep, align 4
  %or1 = or i32 %tmp, 16776960    ; 0x00ffff00
  %or2 = or i32 %arg1, 4278190335 ; 0xff0000ff
  %and = and i32 %or1, %or2
  store i32 %and, ptr addrspace(1) %gep, align 4
  ret void
}

; FIXME here should have been "v_perm_b32" with 0xffff0500 mask.
define amdgpu_kernel void @known_ffff0500(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: known_ffff0500:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    v_mov_b32_e32 v5, 0xffff8004
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v4, v[0:1]
; GCN-NEXT:    s_bitset1_b32 s2, 15
; GCN-NEXT:    v_mov_b32_e32 v3, s1
; GCN-NEXT:    v_mov_b32_e32 v2, s0
; GCN-NEXT:    s_and_b32 s0, s2, 0xff00
; GCN-NEXT:    s_or_b32 s0, s0, 0xffff0000
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_or_b32_e32 v4, 4, v4
; GCN-NEXT:    v_and_b32_e32 v4, 0xff00ff, v4
; GCN-NEXT:    v_or_b32_e32 v4, s0, v4
; GCN-NEXT:    flat_store_dword v[0:1], v4
; GCN-NEXT:    flat_store_dword v[2:3], v5
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %load = load i32, ptr addrspace(1) %gep, align 4
  %mask1 = or i32 %arg1, 32768 ; 0x8000
  %mask2 = or i32 %load, 4
  %and = and i32 %mask2, 16711935     ; 0x00ff00ff
  %tmp1 = and i32 %mask1, 4294967040 ; 0xffffff00
  %tmp2 = or i32 %tmp1, 4294901760   ; 0xffff0000
  %tmp3 = or i32 %tmp2, %and
  store i32 %tmp3, ptr addrspace(1) %gep, align 4
  %v = and i32 %tmp3, 4294934532 ; 0xffff8004
  store i32 %v, ptr addrspace(1) %arg, align 4
  ret void
}

define amdgpu_kernel void @known_050c0c00(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: known_050c0c00:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    v_mov_b32_e32 v5, 0x50c0c00
; GCN-NEXT:    v_mov_b32_e32 v6, 4
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v4, v[0:1]
; GCN-NEXT:    s_or_b32 s2, s2, 4
; GCN-NEXT:    v_mov_b32_e32 v3, s1
; GCN-NEXT:    v_mov_b32_e32 v2, s0
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_perm_b32 v4, v4, s2, v5
; GCN-NEXT:    flat_store_dword v[0:1], v4
; GCN-NEXT:    flat_store_dword v[2:3], v6
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %tmp = load i32, ptr addrspace(1) %gep, align 4
  %tmp2 = shl i32 %tmp, 16
  %mask = or i32 %arg1, 4
  %tmp3 = and i32 %mask, 65535
  %tmp4 = or i32 %tmp2, %tmp3
  %and = and i32 %tmp4, 4278190335
  store i32 %and, ptr addrspace(1) %gep, align 4
  %v = and i32 %and, 16776964
  store i32 %v, ptr addrspace(1) %arg, align 4
  ret void
}

define amdgpu_kernel void @known_ffff8004(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: known_ffff8004:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    v_mov_b32_e32 v5, 0xffff0500
; GCN-NEXT:    v_mov_b32_e32 v6, 0xffff8004
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v4, v[0:1]
; GCN-NEXT:    s_or_b32 s2, s2, 4
; GCN-NEXT:    v_mov_b32_e32 v3, s1
; GCN-NEXT:    v_mov_b32_e32 v2, s0
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_or_b32_e32 v4, 0x8000, v4
; GCN-NEXT:    v_perm_b32 v4, v4, s2, v5
; GCN-NEXT:    flat_store_dword v[0:1], v4
; GCN-NEXT:    flat_store_dword v[2:3], v6
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %load = load i32, ptr addrspace(1) %gep, align 4
  %mask1 = or i32 %arg1, 4
  %mask2 = or i32 %load, 32768 ; 0x8000
  %and = and i32 %mask1, 16711935     ; 0x00ff00ff
  %tmp1 = and i32 %mask2, 4294967040 ; 0xffffff00
  %tmp2 = or i32 %tmp1, 4294901760   ; 0xffff0000
  %tmp3 = or i32 %tmp2, %and
  store i32 %tmp3, ptr addrspace(1) %gep, align 4
  %v = and i32 %tmp3, 4294934532 ; 0xffff8004
  store i32 %v, ptr addrspace(1) %arg, align 4
  ret void
}

; Byte 2 of (ashr x, 24) is the sign bit of byte 0, not byte 0 itself, so the
; v_perm_b32 matcher must not treat it as a source byte.
define amdgpu_kernel void @sext_i8_to_high_byte_pack(ptr addrspace(1) nocapture %arg) {
; GCN-LABEL: sext_i8_to_high_byte_pack:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v2, v[0:1]
; GCN-NEXT:    s_mov_b32 s0, 0x702050c
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_and_b32_e32 v3, 0x7f, v2
; GCN-NEXT:    v_mul_u32_u24_e32 v3, v3, v3
; GCN-NEXT:    v_bfe_i32 v3, v3, 0, 8
; GCN-NEXT:    v_perm_b32 v2, v2, v3, s0
; GCN-NEXT:    v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GCN-NEXT:    flat_store_dword v[0:1], v2
; GCN-NEXT:    s_endpgm
bb:
  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id
  %salt = load i32, ptr addrspace(1) %gep, align 4
  %byte = and i32 %salt, 127
  %mul.shl = shl nuw nsw i32 %byte, 24
  %prod = mul i32 %mul.shl, %byte
  %sext = ashr exact i32 %prod, 24
  %lo.shr = lshr i32 %sext, 16
  %lo = and i32 %lo.shr, 255
  %mid = and i32 %sext, 16711680        ; 0x00ff0000
  %salt.b1b3 = and i32 %salt, -16711936 ; 0xff00ff00
  %or1 = or disjoint i32 %salt.b1b3, %mid
  %res = or disjoint i32 %or1, %lo
  store i32 %res, ptr addrspace(1) %gep, align 4
  ret void
}

define amdgpu_kernel void @dword_from_v16i16_combine_loop(ptr addrspace(1) %out) {
; GCN-LABEL: dword_from_v16i16_combine_loop:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    v_and_b32_e32 v1, 3, v0
; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
; GCN-NEXT:    v_mov_b32_e32 v0, 0
; GCN-NEXT:    s_and_saveexec_b64 s[0:1], vcc
; GCN-NEXT:    s_or_b64 exec, exec, s[0:1]
; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v2, s1
; GCN-NEXT:    v_mov_b32_e32 v1, s0
; GCN-NEXT:    flat_store_byte v[1:2], v0
; GCN-NEXT:    s_endpgm
entry:
  %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
  %ins = insertelement <2 x i32> poison, i32 %tid, i64 0
  %splat = shufflevector <2 x i32> %ins, <2 x i32> poison, <2 x i32> zeroinitializer
  %masked = and <2 x i32> %splat, <i32 31, i32 7>
  %e1 = extractelement <2 x i32> %masked, i64 1
  %and = and i32 %e1, 3
  %cond = icmp eq i32 %and, 0
  br i1 %cond, label %bb1, label %bb2

bb1:
  %wide = shufflevector <2 x i32> %masked, <2 x i32> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
  %trunc = trunc <16 x i32> %wide to <16 x i16>
  %s0 = shufflevector <16 x i16> <i16 0, i16 0, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 9, i16 poison, i16 100, i16 poison, i16 poison>, <16 x i16> %trunc, <16 x i32> <i32 0, i32 1, i32 16, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 11, i32 poison, i32 13, i32 poison, i32 poison>
  %s1 = insertelement <16 x i16> %s0, i16 7, i64 5
  %s2 = shufflevector <16 x i16> %s1, <16 x i16> %trunc, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 11, i32 poison, i32 13, i32 poison, i32 poison>
  %s3 = shufflevector <16 x i16> %s2, <16 x i16> <i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 0, i16 0, i16 0, i16 0, i16 poison, i16 0, i16 poison, i16 0, i16 0>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 23, i32 24, i32 25, i32 26, i32 11, i32 28, i32 13, i32 30, i32 31>
  %max = tail call <16 x i16> @llvm.smax.v16i16(<16 x i16> %s3, <16 x i16> zeroinitializer)
  %bytes = bitcast <16 x i16> %max to <32 x i8>
  br label %bb2

bb2:
  %phi = phi <32 x i8> [ %bytes, %bb1 ], [ zeroinitializer, %entry ]
  %byte16 = extractelement <32 x i8> %phi, i64 16
  store i8 %byte16, ptr addrspace(1) %out, align 1
  ret void
}

define amdgpu_kernel void @dword_from_v16i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GCN-LABEL: dword_from_v16i16:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GCN-NEXT:    v_lshlrev_b32_e32 v0, 5, v0
; GCN-NEXT:    v_mov_b32_e32 v4, 8
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v1, s3
; GCN-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:    v_add_u32_e32 v2, vcc, 20, v0
; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GCN-NEXT:    flat_load_dword v2, v[2:3]
; GCN-NEXT:    flat_load_dword v3, v[0:1]
; GCN-NEXT:    s_mov_b32 s2, 0xc0c0500
; GCN-NEXT:    s_mov_b32 s3, 0x4020c0c
; GCN-NEXT:    v_mov_b32_e32 v0, s0
; GCN-NEXT:    v_mov_b32_e32 v1, s1
; GCN-NEXT:    s_waitcnt vmcnt(1)
; GCN-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_lshlrev_b32_sdwa v4, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GCN-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT:    v_perm_b32 v3, v4, v3, s2
; GCN-NEXT:    v_perm_b32 v2, v5, v2, s3
; GCN-NEXT:    v_or_b32_e32 v2, v3, v2
; GCN-NEXT:    flat_store_dword v[0:1], v2
; GCN-NEXT:    s_endpgm
  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %gep = getelementptr <16 x i16>, ptr addrspace(1) %in, i32 %tid
  %v = load <16 x i16>, ptr addrspace(1) %gep, align 32
  %e0 = extractelement <16 x i16> %v, i32 0
  %e1 = extractelement <16 x i16> %v, i32 1
  %e10 = extractelement <16 x i16> %v, i32 10
  %e11 = extractelement <16 x i16> %v, i32 11
  %z0 = zext i16 %e0 to i32
  %z1 = zext i16 %e1 to i32
  %z10 = zext i16 %e10 to i32
  %z11 = zext i16 %e11 to i32
  %b0 = and i32 %z0, 255
  %b1 = shl i32 %z1, 8
  %b1m = and i32 %b1, 65280
  %b2 = shl i32 %z10, 16
  %b2m = and i32 %b2, 16711680
  %b3 = shl i32 %z11, 24
  %b3m = and i32 %b3, 4278190080
  %o1 = or i32 %b0, %b1m
  %o2 = or i32 %b2m, %b3m
  %r = or i32 %o1, %o2
  store i32 %r, ptr addrspace(1) %out
  ret void
}

declare i32 @llvm.amdgcn.workitem.id.x()