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llvm / llvm-project / 4b30076f16fc55891da8952bda3f2d81dbeec5a5 / . / llvm / lib / Target / ARM / ARMInstrThumb2.td
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//===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file describes the Thumb2 instruction set.
//
//===----------------------------------------------------------------------===//
// IT block predicate field
def it_pred_asmoperand : AsmOperandClass {
let Name = "ITCondCode";
let ParserMethod = "parseITCondCode";
}
def it_pred : Operand<i32> {
let PrintMethod = "printMandatoryPredicateOperand";
let ParserMatchClass = it_pred_asmoperand;
}
// IT block condition mask
def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
def it_mask : Operand<i32> {
let PrintMethod = "printThumbITMask";
let ParserMatchClass = it_mask_asmoperand;
let EncoderMethod = "getITMaskOpValue";
}
// t2_shift_imm: An integer that encodes a shift amount and the type of shift
// (asr or lsl). The 6-bit immediate encodes as:
// {5} 0 ==> lsl
// 1 asr
// {4-0} imm5 shift amount.
// asr #32 not allowed
def t2_shift_imm : Operand<i32> {
let PrintMethod = "printShiftImmOperand";
let ParserMatchClass = ShifterImmAsmOperand;
let DecoderMethod = "DecodeT2ShifterImmOperand";
}
def mve_shift_imm : AsmOperandClass {
let Name = "MVELongShift";
let RenderMethod = "addImmOperands";
let DiagnosticString = "operand must be an immediate in the range [1,32]";
}
def long_shift : Operand<i32>,
ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]> {
let ParserMatchClass = mve_shift_imm;
let DecoderMethod = "DecodeLongShiftOperand";
}
// Shifted operands. No register controlled shifts for Thumb2.
// Note: We do not support rrx shifted operands yet.
def t2_so_reg : Operand<i32>, // reg imm
ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
[shl,srl,sra,rotr]> {
let EncoderMethod = "getT2SORegOpValue";
let PrintMethod = "printT2SOOperand";
let DecoderMethod = "DecodeSORegImmOperand";
let ParserMatchClass = ShiftedImmAsmOperand;
let MIOperandInfo = (ops rGPR, i32imm);
}
// Same as above, but only matching on a single use node.
def t2_so_reg_oneuse : Operand<i32>,
ComplexPattern<i32, 2,
"SelectShiftImmShifterOperandOneUse",
[shl,srl,sra,rotr]>;
// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
MVT::i32);
}]>;
// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N),
MVT::i32);
}]>;
// so_imm_notSext_XFORM - Return a so_imm value packed into the format
// described for so_imm_notSext def below, with sign extension from 16
// bits.
def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
APInt apIntN = N->getAPIntValue();
unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32);
}]>;
// t2_so_imm - Match a 32-bit immediate operand, which is an
// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
// immediate splatted into multiple bytes of the word.
def t2_so_imm_asmoperand : AsmOperandClass {
let Name = "T2SOImm";
let RenderMethod = "addImmOperands";
}
def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
return ARM_AM::getT2SOImmVal(Imm) != -1;
}]> {
let ParserMatchClass = t2_so_imm_asmoperand;
let EncoderMethod = "getT2SOImmOpValue";
let DecoderMethod = "DecodeT2SOImm";
}
// t2_so_imm_not - Match an immediate that is a complement
// of a t2_so_imm.
// Note: this pattern doesn't require an encoder method and such, as it's
// only used on aliases (Pat<> and InstAlias<>). The actual encoding
// is handled by the destination instructions, which use t2_so_imm.
def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
}], t2_so_imm_not_XFORM> {
let ParserMatchClass = t2_so_imm_not_asmoperand;
}
// t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
// if the upper 16 bits are zero.
def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
APInt apIntN = N->getAPIntValue();
if (!apIntN.isIntN(16)) return false;
unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
}], t2_so_imm_notSext16_XFORM> {
let ParserMatchClass = t2_so_imm_not_asmoperand;
}
// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
def t2_so_imm_neg : Operand<i32>, ImmLeaf<i32, [{
return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
}], t2_so_imm_neg_XFORM> {
let ParserMatchClass = t2_so_imm_neg_asmoperand;
}
/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0,4095].
def imm0_4095_asmoperand: ImmAsmOperand<0,4095> { let Name = "Imm0_4095"; }
def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
return Imm >= 0 && Imm < 4096;
}]> {
let ParserMatchClass = imm0_4095_asmoperand;
}
def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
return (uint32_t)(-N->getZExtValue()) < 4096;
}], imm_neg_XFORM> {
let ParserMatchClass = imm0_4095_neg_asmoperand;
}
def imm1_255_neg : PatLeaf<(i32 imm), [{
uint32_t Val = -N->getZExtValue();
return (Val > 0 && Val < 255);
}], imm_neg_XFORM>;
def imm0_255_not : PatLeaf<(i32 imm), [{
return (uint32_t)(~N->getZExtValue()) < 255;
}], imm_not_XFORM>;
def lo5AllOne : PatLeaf<(i32 imm), [{
// Returns true if all low 5-bits are 1.
return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
}]>;
// Define Thumb2 specific addressing modes.
// t2_addr_offset_none := reg
def MemNoOffsetT2AsmOperand
: AsmOperandClass { let Name = "MemNoOffsetT2"; }
def t2_addr_offset_none : MemOperand {
let PrintMethod = "printAddrMode7Operand";
let DecoderMethod = "DecodeGPRnopcRegisterClass";
let ParserMatchClass = MemNoOffsetT2AsmOperand;
let MIOperandInfo = (ops GPRnopc:$base);
}
// t2_nosp_addr_offset_none := reg
def MemNoOffsetT2NoSpAsmOperand
: AsmOperandClass { let Name = "MemNoOffsetT2NoSp"; }
def t2_nosp_addr_offset_none : MemOperand {
let PrintMethod = "printAddrMode7Operand";
let DecoderMethod = "DecoderGPRRegisterClass";
let ParserMatchClass = MemNoOffsetT2NoSpAsmOperand;
let MIOperandInfo = (ops rGPR:$base);
}
// t2addrmode_imm12 := reg + imm12
def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
def t2addrmode_imm12 : MemOperand,
ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
let PrintMethod = "printAddrModeImm12Operand<false>";
let EncoderMethod = "getAddrModeImm12OpValue";
let DecoderMethod = "DecodeT2AddrModeImm12";
let ParserMatchClass = t2addrmode_imm12_asmoperand;
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
}
// t2ldrlabel := imm12
def t2ldrlabel : MemOperand {
let EncoderMethod = "getAddrModeImm12OpValue";
let PrintMethod = "printThumbLdrLabelOperand";
}
def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
def t2ldr_pcrel_imm12 : Operand<i32> {
let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
// used for assembler pseudo instruction and maps to t2ldrlabel, so
// doesn't need encoder or print methods of its own.
}
// ADR instruction labels.
def t2adrlabel : Operand<i32> {
let EncoderMethod = "getT2AdrLabelOpValue";
let PrintMethod = "printAdrLabelOperand<0>";
}
// t2addrmode_posimm8 := reg + imm8
def MemPosImm8OffsetAsmOperand : AsmOperandClass {
let Name="MemPosImm8Offset";
let RenderMethod = "addMemImmOffsetOperands";
}
def t2addrmode_posimm8 : MemOperand {
let PrintMethod = "printT2AddrModeImm8Operand<false>";
let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";
let DecoderMethod = "DecodeT2AddrModeImm8";
let ParserMatchClass = MemPosImm8OffsetAsmOperand;
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
}
// t2addrmode_negimm8 := reg - imm8
def MemNegImm8OffsetAsmOperand : AsmOperandClass {
let Name="MemNegImm8Offset";
let RenderMethod = "addMemImmOffsetOperands";
}
def t2addrmode_negimm8 : MemOperand,
ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
let PrintMethod = "printT2AddrModeImm8Operand<false>";
let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";
let DecoderMethod = "DecodeT2AddrModeImm8";
let ParserMatchClass = MemNegImm8OffsetAsmOperand;
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
}
// t2addrmode_imm8 := reg +/- imm8
def MemImm8OffsetAsmOperand : AsmOperandClass {
let Name = "MemImm8Offset";
let RenderMethod = "addMemImmOffsetOperands";
}
class T2AddrMode_Imm8 : MemOperand,
ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";
let DecoderMethod = "DecodeT2AddrModeImm8";
let ParserMatchClass = MemImm8OffsetAsmOperand;
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
}
def t2addrmode_imm8 : T2AddrMode_Imm8 {
let PrintMethod = "printT2AddrModeImm8Operand<false>";
}
def t2addrmode_imm8_pre : T2AddrMode_Imm8 {
let PrintMethod = "printT2AddrModeImm8Operand<true>";
}
def t2am_imm8_offset : MemOperand,
ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
[], [SDNPWantRoot]> {
let PrintMethod = "printT2AddrModeImm8OffsetOperand";
let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
let DecoderMethod = "DecodeT2Imm8";
}
// t2addrmode_imm8s4 := reg +/- (imm8 << 2)
def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
class T2AddrMode_Imm8s4 : MemOperand,
ComplexPattern<i32, 2, "SelectT2AddrModeImm8<2>", []> {
let EncoderMethod = "getT2AddrModeImm8s4OpValue";
let DecoderMethod = "DecodeT2AddrModeImm8s4";
let ParserMatchClass = MemImm8s4OffsetAsmOperand;
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
}
def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 {
let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
}
def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 {
let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
}
def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
def t2am_imm8s4_offset : MemOperand {
let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
let EncoderMethod = "getT2ScaledImmOpValue<8,2>";
let DecoderMethod = "DecodeT2Imm8S4";
}
// t2addrmode_imm7s4 := reg +/- (imm7 << 2)
def MemImm7s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm7s4Offset";}
class T2AddrMode_Imm7s4 : MemOperand {
let EncoderMethod = "getT2AddrModeImm7s4OpValue";
let DecoderMethod = "DecodeT2AddrModeImm7<2,0>";
let ParserMatchClass = MemImm7s4OffsetAsmOperand;
let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
}
def t2addrmode_imm7s4 : T2AddrMode_Imm7s4 {
// They are printed the same way as the imm8 version
let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
}
def t2addrmode_imm7s4_pre : T2AddrMode_Imm7s4 {
// They are printed the same way as the imm8 version
let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
}
def t2am_imm7s4_offset_asmoperand : AsmOperandClass { let Name = "Imm7s4"; }
def t2am_imm7s4_offset : MemOperand {
// They are printed the same way as the imm8 version
let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
let ParserMatchClass = t2am_imm7s4_offset_asmoperand;
let EncoderMethod = "getT2ScaledImmOpValue<7,2>";
let DecoderMethod = "DecodeT2Imm7S4";
}
// t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
let Name = "MemImm0_1020s4Offset";
}
def t2addrmode_imm0_1020s4 : MemOperand,
ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> {
let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
}
// t2addrmode_so_reg := reg + (reg << imm2)
def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
def t2addrmode_so_reg : MemOperand,
ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
let PrintMethod = "printT2AddrModeSoRegOperand";
let EncoderMethod = "getT2AddrModeSORegOpValue";
let DecoderMethod = "DecodeT2AddrModeSOReg";
let ParserMatchClass = t2addrmode_so_reg_asmoperand;
let MIOperandInfo = (ops GPRnopc:$base, rGPR:$offsreg, i32imm:$offsimm);
}
// Addresses for the TBB/TBH instructions.
def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
def addrmode_tbb : MemOperand {
let PrintMethod = "printAddrModeTBB";
let ParserMatchClass = addrmode_tbb_asmoperand;
let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
}
def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
def addrmode_tbh : MemOperand {
let PrintMethod = "printAddrModeTBH";
let ParserMatchClass = addrmode_tbh_asmoperand;
let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
}
// Define ARMv8.1-M specific addressing modes.
// Label operands for BF/BFL/WLS/DLS/LE
class BFLabelOp<string signed, string isNeg, string zeroPermitted, string size,
string fixup>
: Operand<OtherVT> {
let EncoderMethod = !strconcat("getBFTargetOpValue<", isNeg, ", ",
fixup, ">");
let OperandType = "OPERAND_PCREL";
let DecoderMethod = !strconcat("DecodeBFLabelOperand<", signed, ", ",
isNeg, ", ", zeroPermitted, ", ", size, ">");
}
def bflabel_u4 : BFLabelOp<"false", "false", "false", "4", "ARM::fixup_bf_branch">;
def bflabel_s12 : BFLabelOp<"true", "false", "true", "12", "ARM::fixup_bfc_target">;
def bflabel_s16 : BFLabelOp<"true", "false", "true", "16", "ARM::fixup_bf_target">;
def bflabel_s18 : BFLabelOp<"true", "false", "true", "18", "ARM::fixup_bfl_target">;
def wlslabel_u11_asmoperand : AsmOperandClass {
let Name = "WLSLabel";
let RenderMethod = "addImmOperands";
let PredicateMethod = "isUnsignedOffset<11, 1>";
let DiagnosticString =
"loop end is out of range or not a positive multiple of 2";
}
def wlslabel_u11 : BFLabelOp<"false", "false", "true", "11", "ARM::fixup_wls"> {
let ParserMatchClass = wlslabel_u11_asmoperand;
}
def lelabel_u11_asmoperand : AsmOperandClass {
let Name = "LELabel";
let RenderMethod = "addImmOperands";
let PredicateMethod = "isLEOffset";
let DiagnosticString =
"loop start is out of range or not a negative multiple of 2";
}
def lelabel_u11 : BFLabelOp<"false", "true", "true", "11", "ARM::fixup_le"> {
let ParserMatchClass = lelabel_u11_asmoperand;
}
def bfafter_target : Operand<OtherVT> {
let EncoderMethod = "getBFAfterTargetOpValue";
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBFAfterTargetOperand";
}
// pred operand excluding AL
def pred_noal_asmoperand : AsmOperandClass {
let Name = "CondCodeNoAL";
let RenderMethod = "addITCondCodeOperands";
let PredicateMethod = "isITCondCodeNoAL";
let ParserMethod = "parseITCondCode";
}
def pred_noal : Operand<i32> {
let PrintMethod = "printMandatoryPredicateOperand";
let ParserMatchClass = pred_noal_asmoperand;
let DecoderMethod = "DecodePredNoALOperand";
}
// CSEL aliases inverted predicate
def pred_noal_inv_asmoperand : AsmOperandClass {
let Name = "CondCodeNoALInv";
let RenderMethod = "addITCondCodeInvOperands";
let PredicateMethod = "isITCondCodeNoAL";
let ParserMethod = "parseITCondCode";
}
def pred_noal_inv : Operand<i32> {
let PrintMethod = "printMandatoryInvertedPredicateOperand";
let ParserMatchClass = pred_noal_inv_asmoperand;
}
//===----------------------------------------------------------------------===//
// Multiclass helpers...
//
class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<12> imm;
let Inst{11-8} = Rd;
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0};
}
class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2sI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
let Inst{11-8} = Rd;
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0};
}
class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rn;
bits<12> imm;
let Inst{19-16} = Rn;
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0};
}
class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<12> ShiftedRm;
let Inst{11-8} = Rd;
let Inst{3-0} = ShiftedRm{3-0};
let Inst{5-4} = ShiftedRm{6-5};
let Inst{14-12} = ShiftedRm{11-9};
let Inst{7-6} = ShiftedRm{8-7};
}
class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2sI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<12> ShiftedRm;
let Inst{11-8} = Rd;
let Inst{3-0} = ShiftedRm{3-0};
let Inst{5-4} = ShiftedRm{6-5};
let Inst{14-12} = ShiftedRm{11-9};
let Inst{7-6} = ShiftedRm{8-7};
}
class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rn;
bits<12> ShiftedRm;
let Inst{19-16} = Rn;
let Inst{3-0} = ShiftedRm{3-0};
let Inst{5-4} = ShiftedRm{6-5};
let Inst{14-12} = ShiftedRm{11-9};
let Inst{7-6} = ShiftedRm{8-7};
}
class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rm;
let Inst{11-8} = Rd;
let Inst{3-0} = Rm;
}
class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2sI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rm;
let Inst{11-8} = Rd;
let Inst{3-0} = Rm;
}
class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rn;
bits<4> Rm;
let Inst{19-16} = Rn;
let Inst{3-0} = Rm;
}
class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
let Inst{11-8} = Rd;
let Inst{19-16} = Rn;
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0};
}
class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2sI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
let Inst{11-8} = Rd;
let Inst{19-16} = Rn;
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0};
}
class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rm;
bits<5> imm;
let Inst{11-8} = Rd;
let Inst{3-0} = Rm;
let Inst{14-12} = imm{4-2};
let Inst{7-6} = imm{1-0};
}
class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2sI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rm;
bits<5> imm;
let Inst{11-8} = Rd;
let Inst{3-0} = Rm;
let Inst{14-12} = imm{4-2};
let Inst{7-6} = imm{1-0};
}
class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{11-8} = Rd;
let Inst{19-16} = Rn;
let Inst{3-0} = Rm;
}
class T2ThreeRegNoP<dag oops, dag iops, InstrItinClass itin,
string asm, list<dag> pattern>
: T2XI<oops, iops, itin, asm, pattern> {
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{11-8} = Rd;
let Inst{19-16} = Rn;
let Inst{3-0} = Rm;
}
class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2sI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{11-8} = Rd;
let Inst{19-16} = Rn;
let Inst{3-0} = Rm;
}
class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rn;
bits<12> ShiftedRm;
let Inst{11-8} = Rd;
let Inst{19-16} = Rn;
let Inst{3-0} = ShiftedRm{3-0};
let Inst{5-4} = ShiftedRm{6-5};
let Inst{14-12} = ShiftedRm{11-9};
let Inst{7-6} = ShiftedRm{8-7};
}
class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2sI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rn;
bits<12> ShiftedRm;
let Inst{11-8} = Rd;
let Inst{19-16} = Rn;
let Inst{3-0} = ShiftedRm{3-0};
let Inst{5-4} = ShiftedRm{6-5};
let Inst{14-12} = ShiftedRm{11-9};
let Inst{7-6} = ShiftedRm{8-7};
}
class T2FourReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
bits<4> Ra;
let Inst{19-16} = Rn;
let Inst{15-12} = Ra;
let Inst{11-8} = Rd;
let Inst{3-0} = Rm;
}
class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
string opc, list<dag> pattern>
: T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>,
Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]> {
bits<4> RdLo;
bits<4> RdHi;
bits<4> Rn;
bits<4> Rm;
let Inst{31-23} = 0b111110111;
let Inst{22-20} = opc22_20;
let Inst{19-16} = Rn;
let Inst{15-12} = RdLo;
let Inst{11-8} = RdHi;
let Inst{7-4} = opc7_4;
let Inst{3-0} = Rm;
}
class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, string opc>
: T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> {
bits<4> RdLo;
bits<4> RdHi;
bits<4> Rn;
bits<4> Rm;
let Inst{31-23} = 0b111110111;
let Inst{22-20} = opc22_20;
let Inst{19-16} = Rn;
let Inst{15-12} = RdLo;
let Inst{11-8} = RdHi;
let Inst{7-4} = opc7_4;
let Inst{3-0} = Rm;
}
/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
/// binary operation that produces a value. These are predicable and can be
/// changed to modify CPSR.
multiclass T2I_bin_irs<bits<4> opcod, string opc,
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
SDPatternOperator opnode, bit Commutable = 0,
string wide = ""> {
// shifted imm
def ri : T2sTwoRegImm<
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
opc, "\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
Sched<[WriteALU, ReadALU]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
let Inst{15} = 0;
}
// register
def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
Sched<[WriteALU, ReadALU, ReadALU]> {
let isCommutable = Commutable;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
let Inst{15} = 0b0;
// In most of these instructions, and most versions of the Arm
// architecture, bit 15 of this encoding is listed as (0) rather
// than 0, i.e. setting it to 1 is UNPREDICTABLE or a soft-fail
// rather than a hard failure. In v8.1-M, this requirement is
// upgraded to a hard one for ORR, so that the encodings with 1
// in this bit can be reused for other instructions (such as
// CSEL). Setting Unpredictable{15} = 1 here would reintroduce
// that encoding clash in the auto- generated MC decoder, so I
// comment it out.
let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1);
let Inst{14-12} = 0b000; // imm3
let Inst{7-6} = 0b00; // imm2
let Inst{5-4} = 0b00; // type
}
// shifted register
def rs : T2sTwoRegShiftedReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
Sched<[WriteALUsi, ReadALU]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
let Inst{15} = 0;
let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1); // see above
}
// Assembly aliases for optional destination operand when it's the same
// as the source operand.
def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
(!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
t2_so_imm:$imm, pred:$p,
cc_out:$s)>;
def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
(!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
rGPR:$Rm, pred:$p,
cc_out:$s)>;
def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
(!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
t2_so_reg:$shift, pred:$p,
cc_out:$s)>;
}
/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
// the ".w" suffix to indicate that they are wide.
multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
SDPatternOperator opnode, bit Commutable = 0> :
T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
// Assembler aliases w/ the ".w" suffix.
def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
(!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
cc_out:$s)>;
// Assembler aliases w/o the ".w" suffix.
def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
(!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
cc_out:$s)>;
def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
(!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
pred:$p, cc_out:$s)>;
// and with the optional destination operand, too.
def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
(!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
pred:$p, cc_out:$s)>;
def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
(!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
cc_out:$s)>;
def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
(!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
pred:$p, cc_out:$s)>;
}
/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
/// reversed. The 'rr' form is only defined for the disassembler; for codegen
/// it is equivalent to the T2I_bin_irs counterpart.
multiclass T2I_rbin_irs<bits<4> opcod, string opc, SDNode opnode> {
// shifted imm
def ri : T2sTwoRegImm<
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
opc, ".w\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
Sched<[WriteALU, ReadALU]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
let Inst{15} = 0;
}
// register
def rr : T2sThreeReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
opc, "\t$Rd, $Rn, $Rm",
[/* For disassembly only; pattern left blank */]>,
Sched<[WriteALU, ReadALU, ReadALU]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
let Inst{14-12} = 0b000; // imm3
let Inst{7-6} = 0b00; // imm2
let Inst{5-4} = 0b00; // type
}
// shifted register
def rs : T2sTwoRegShiftedReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
[(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
Sched<[WriteALUsi, ReadALU]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
}
}
/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
/// instruction modifies the CPSR register.
///
/// These opcodes will be converted to the real non-S opcodes by
/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
let hasPostISelHook = 1, Defs = [CPSR] in {
multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
InstrItinClass iis, SDNode opnode,
bit Commutable = 0> {
// shifted imm
def ri : t2PseudoInst<(outs rGPR:$Rd),
(ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
4, iii,
[(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
t2_so_imm:$imm))]>,
Sched<[WriteALU, ReadALU]>;
// register
def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
4, iir,
[(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
rGPR:$Rm))]>,
Sched<[WriteALU, ReadALU, ReadALU]> {
let isCommutable = Commutable;
}
// shifted register
def rs : t2PseudoInst<(outs rGPR:$Rd),
(ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
4, iis,
[(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
t2_so_reg:$ShiftedRm))]>,
Sched<[WriteALUsi, ReadALUsr]>;
}
}
/// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
/// operands are reversed.
let hasPostISelHook = 1, Defs = [CPSR] in {
multiclass T2I_rbin_s_is<SDNode opnode> {
// shifted imm
def ri : t2PseudoInst<(outs rGPR:$Rd),
(ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
4, IIC_iALUi,
[(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
rGPR:$Rn))]>,
Sched<[WriteALU, ReadALU]>;
// shifted register
def rs : t2PseudoInst<(outs rGPR:$Rd),
(ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
4, IIC_iALUsi,
[(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
rGPR:$Rn))]>,
Sched<[WriteALUsi, ReadALU]>;
}
}
/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
/// patterns for a binary operation that produces a value.
multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDNode opnode,
bit Commutable = 0> {
// shifted imm
// The register-immediate version is re-materializable. This is useful
// in particular for taking the address of a local.
let isReMaterializable = 1 in {
def spImm : T2sTwoRegImm<
(outs GPRsp:$Rd), (ins GPRsp:$Rn, t2_so_imm:$imm), IIC_iALUi,
opc, ".w\t$Rd, $Rn, $imm",
[]>,
Sched<[WriteALU, ReadALU]> {
let Rn = 13;
let Rd = 13;
let Inst{31-27} = 0b11110;
let Inst{25-24} = 0b01;
let Inst{23-21} = op23_21;
let Inst{15} = 0;
let DecoderMethod = "DecodeT2AddSubSPImm";
}
def ri : T2sTwoRegImm<
(outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
opc, ".w\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
Sched<[WriteALU, ReadALU]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24} = 1;
let Inst{23-21} = op23_21;
let Inst{15} = 0;
}
}
// 12-bit imm
def ri12 : T2I<
(outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
!strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
Sched<[WriteALU, ReadALU]> {
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
let Inst{31-27} = 0b11110;
let Inst{26} = imm{11};
let Inst{25-24} = 0b10;
let Inst{23-21} = op23_21;
let Inst{20} = 0; // The S bit.
let Inst{19-16} = Rn;
let Inst{15} = 0;
let Inst{14-12} = imm{10-8};
let Inst{11-8} = Rd;
let Inst{7-0} = imm{7-0};
}
def spImm12 : T2I<
(outs GPRsp:$Rd), (ins GPRsp:$Rn, imm0_4095:$imm), IIC_iALUi,
!strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
[]>,
Sched<[WriteALU, ReadALU]> {
bits<4> Rd = 13;
bits<4> Rn = 13;
bits<12> imm;
let Inst{31-27} = 0b11110;
let Inst{26} = imm{11};
let Inst{25-24} = 0b10;
let Inst{23-21} = op23_21;
let Inst{20} = 0; // The S bit.
let Inst{19-16} = Rn;
let Inst{15} = 0;
let Inst{14-12} = imm{10-8};
let Inst{11-8} = Rd;
let Inst{7-0} = imm{7-0};
let DecoderMethod = "DecodeT2AddSubSPImm";
}
// register
def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
[(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
Sched<[WriteALU, ReadALU, ReadALU]> {
let isCommutable = Commutable;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24} = 1;
let Inst{23-21} = op23_21;
let Inst{14-12} = 0b000; // imm3
let Inst{7-6} = 0b00; // imm2
let Inst{5-4} = 0b00; // type
}
// shifted register
def rs : T2sTwoRegShiftedReg<
(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
[(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
Sched<[WriteALUsi, ReadALU]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24} = 1;
let Inst{23-21} = op23_21;
}
}
/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
/// for a binary operation that produces a value and use the carry
/// bit. It's not predicable.
let Defs = [CPSR], Uses = [CPSR] in {
multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode,
bit Commutable = 0> {
// shifted imm
def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
let Inst{15} = 0;
}
// register
def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
opc, ".w\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
let isCommutable = Commutable;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
let Inst{14-12} = 0b000; // imm3
let Inst{7-6} = 0b00; // imm2
let Inst{5-4} = 0b00; // type
}
// shifted register
def rs : T2sTwoRegShiftedReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
[(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
}
}
}
/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
// rotate operation that produces a value.
multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, SDNode opnode> {
// 5-bit imm
def ri : T2sTwoRegShiftImm<
(outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
opc, ".w\t$Rd, $Rm, $imm",
[(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
Sched<[WriteALU]> {
let Inst{31-27} = 0b11101;
let Inst{26-21} = 0b010010;
let Inst{19-16} = 0b1111; // Rn
let Inst{15} = 0b0;
let Inst{5-4} = opcod;
}
// register
def rr : T2sThreeReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
opc, ".w\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
Sched<[WriteALU]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
let Inst{22-21} = opcod;
let Inst{15-12} = 0b1111;
let Inst{7-4} = 0b0000;
}
// Optional destination register
def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
(!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
cc_out:$s)>;
def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
(!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
cc_out:$s)>;
// Assembler aliases w/o the ".w" suffix.
def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
(!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
cc_out:$s)>;
def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
(!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
cc_out:$s)>;
// and with the optional destination operand, too.
def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
(!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
cc_out:$s)>;
def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
(!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
cc_out:$s)>;
}
/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
/// patterns. Similar to T2I_bin_irs except the instruction does not produce
/// a explicit result, only implicitly set CPSR.
multiclass T2I_cmp_irs<bits<4> opcod, string opc, RegisterClass LHSGPR,
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
SDPatternOperator opnode> {
let isCompare = 1, Defs = [CPSR] in {
// shifted imm
def ri : T2OneRegCmpImm<
(outs), (ins LHSGPR:$Rn, t2_so_imm:$imm), iii,
opc, ".w\t$Rn, $imm",
[(opnode LHSGPR:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
let Inst{20} = 1; // The S bit.
let Inst{15} = 0;
let Inst{11-8} = 0b1111; // Rd
}
// register
def rr : T2TwoRegCmp<
(outs), (ins LHSGPR:$Rn, rGPR:$Rm), iir,
opc, ".w\t$Rn, $Rm",
[(opnode LHSGPR:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
let Inst{20} = 1; // The S bit.
let Inst{14-12} = 0b000; // imm3
let Inst{11-8} = 0b1111; // Rd
let Inst{7-6} = 0b00; // imm2
let Inst{5-4} = 0b00; // type
}
// shifted register
def rs : T2OneRegCmpShiftedReg<
(outs), (ins LHSGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
opc, ".w\t$Rn, $ShiftedRm",
[(opnode LHSGPR:$Rn, t2_so_reg:$ShiftedRm)]>,
Sched<[WriteCMPsi]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
let Inst{20} = 1; // The S bit.
let Inst{11-8} = 0b1111; // Rd
}
}
// Assembler aliases w/o the ".w" suffix.
// No alias here for 'rr' version as not all instantiations of this
// multiclass want one (CMP in particular, does not).
def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
(!cast<Instruction>(NAME#"ri") LHSGPR:$Rn, t2_so_imm:$imm, pred:$p)>;
def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
(!cast<Instruction>(NAME#"rs") LHSGPR:$Rn, t2_so_reg:$shift, pred:$p)>;
}
/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
InstrItinClass iii, InstrItinClass iis, RegisterClass target,
PatFrag opnode> {
def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
opc, ".w\t$Rt, $addr",
[(set target:$Rt, (opnode t2addrmode_imm12:$addr))]>,
Sched<[WriteLd]> {
bits<4> Rt;
bits<17> addr;
let Inst{31-25} = 0b1111100;
let Inst{24} = signed;
let Inst{23} = 1;
let Inst{22-21} = opcod;
let Inst{20} = 1; // load
let Inst{19-16} = addr{16-13}; // Rn
let Inst{15-12} = Rt;
let Inst{11-0} = addr{11-0}; // imm
let DecoderMethod = "DecodeT2LoadImm12";
}
def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
opc, "\t$Rt, $addr",
[(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]>,
Sched<[WriteLd]> {
bits<4> Rt;
bits<13> addr;
let Inst{31-27} = 0b11111;
let Inst{26-25} = 0b00;
let Inst{24} = signed;
let Inst{23} = 0;
let Inst{22-21} = opcod;
let Inst{20} = 1; // load
let Inst{19-16} = addr{12-9}; // Rn
let Inst{15-12} = Rt;
let Inst{11} = 1;
// Offset: index==TRUE, wback==FALSE
let Inst{10} = 1; // The P bit.
let Inst{9} = addr{8}; // U
let Inst{8} = 0; // The W bit.
let Inst{7-0} = addr{7-0}; // imm
let DecoderMethod = "DecodeT2LoadImm8";
}
def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
opc, ".w\t$Rt, $addr",
[(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]>,
Sched<[WriteLd]> {
let Inst{31-27} = 0b11111;
let Inst{26-25} = 0b00;
let Inst{24} = signed;
let Inst{23} = 0;
let Inst{22-21} = opcod;
let Inst{20} = 1; // load
let Inst{11-6} = 0b000000;
bits<4> Rt;
let Inst{15-12} = Rt;
bits<10> addr;
let Inst{19-16} = addr{9-6}; // Rn
let Inst{3-0} = addr{5-2}; // Rm
let Inst{5-4} = addr{1-0}; // imm
let DecoderMethod = "DecodeT2LoadShift";
}
// pci variant is very similar to i12, but supports negative offsets
// from the PC.
def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
opc, ".w\t$Rt, $addr",
[(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]>,
Sched<[WriteLd]> {
let isReMaterializable = 1;
let Inst{31-27} = 0b11111;
let Inst{26-25} = 0b00;
let Inst{24} = signed;
let Inst{22-21} = opcod;
let Inst{20} = 1; // load
let Inst{19-16} = 0b1111; // Rn
bits<4> Rt;
let Inst{15-12} = Rt{3-0};
bits<13> addr;
let Inst{23} = addr{12}; // add = (U == '1')
let Inst{11-0} = addr{11-0};
let DecoderMethod = "DecodeT2LoadLabel";
}
}
/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
multiclass T2I_st<bits<2> opcod, string opc,
InstrItinClass iii, InstrItinClass iis, RegisterClass target,
PatFrag opnode> {
def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
opc, ".w\t$Rt, $addr",
[(opnode target:$Rt, t2addrmode_imm12:$addr)]>,
Sched<[WriteST]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0001;
let Inst{22-21} = opcod;
let Inst{20} = 0; // !load
bits<4> Rt;
let Inst{15-12} = Rt;
bits<17> addr;
let addr{12} = 1; // add = TRUE
let Inst{19-16} = addr{16-13}; // Rn
let Inst{23} = addr{12}; // U
let Inst{11-0} = addr{11-0}; // imm
}
def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
opc, "\t$Rt, $addr",
[(opnode target:$Rt, t2addrmode_negimm8:$addr)]>,
Sched<[WriteST]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0000;
let Inst{22-21} = opcod;
let Inst{20} = 0; // !load
let Inst{11} = 1;
// Offset: index==TRUE, wback==FALSE
let Inst{10} = 1; // The P bit.
let Inst{8} = 0; // The W bit.
bits<4> Rt;
let Inst{15-12} = Rt;
bits<13> addr;
let Inst{19-16} = addr{12-9}; // Rn
let Inst{9} = addr{8}; // U
let Inst{7-0} = addr{7-0}; // imm
}
def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
opc, ".w\t$Rt, $addr",
[(opnode target:$Rt, t2addrmode_so_reg:$addr)]>,
Sched<[WriteST]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0000;
let Inst{22-21} = opcod;
let Inst{20} = 0; // !load
let Inst{11-6} = 0b000000;
bits<4> Rt;
let Inst{15-12} = Rt;
bits<10> addr;
let Inst{19-16} = addr{9-6}; // Rn
let Inst{3-0} = addr{5-2}; // Rm
let Inst{5-4} = addr{1-0}; // imm
}
}
/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24.
class T2I_ext_rrot_base<bits<3> opcod, dag iops, dag oops,
string opc, string oprs,
list<dag> pattern>
: T2TwoReg<iops, oops, IIC_iEXTr, opc, oprs, pattern> {
bits<2> rot;
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod;
let Inst{19-16} = 0b1111; // Rn
let Inst{15-12} = 0b1111;
let Inst{7} = 1;
let Inst{5-4} = rot; // rotate
}
class T2I_ext_rrot<bits<3> opcod, string opc>
: T2I_ext_rrot_base<opcod,
(outs rGPR:$Rd),
(ins rGPR:$Rm, rot_imm:$rot),
opc, ".w\t$Rd, $Rm$rot", []>,
Requires<[IsThumb2]>,
Sched<[WriteALU, ReadALU]>;
// UXTB16, SXTB16 - Requires HasDSP, does not need the .w qualifier.
class T2I_ext_rrot_xtb16<bits<3> opcod, string opc>
: T2I_ext_rrot_base<opcod,
(outs rGPR:$Rd),
(ins rGPR:$Rm, rot_imm:$rot),
opc, "\t$Rd, $Rm$rot", []>,
Requires<[HasDSP, IsThumb2]>,
Sched<[WriteALU, ReadALU]>;
/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24.
class T2I_exta_rrot<bits<3> opcod, string opc>
: T2ThreeReg<(outs rGPR:$Rd),
(ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
Requires<[HasDSP, IsThumb2]>,
Sched<[WriteALU, ReadALU]> {
bits<2> rot;
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod;
let Inst{15-12} = 0b1111;
let Inst{7} = 1;
let Inst{5-4} = rot;
}
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Miscellaneous Instructions.
//
class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
string asm, list<dag> pattern>
: T2XI<oops, iops, itin, asm, pattern> {
bits<4> Rd;
bits<12> label;
let Inst{11-8} = Rd;
let Inst{26} = label{11};
let Inst{14-12} = label{10-8};
let Inst{7-0} = label{7-0};
}
// LEApcrel - Load a pc-relative address into a register without offending the
// assembler.
def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
(ins t2adrlabel:$addr, pred:$p),
IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
Sched<[WriteALU, ReadALU]> {
let Inst{31-27} = 0b11110;
let Inst{25-24} = 0b10;
// Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
let Inst{22} = 0;
let Inst{20} = 0;
let Inst{19-16} = 0b1111; // Rn
let Inst{15} = 0;
bits<4> Rd;
bits<13> addr;
let Inst{11-8} = Rd;
let Inst{23} = addr{12};
let Inst{21} = addr{12};
let Inst{26} = addr{11};
let Inst{14-12} = addr{10-8};
let Inst{7-0} = addr{7-0};
let DecoderMethod = "DecodeT2Adr";
}
let hasSideEffects = 0, isReMaterializable = 1 in
def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
let hasSideEffects = 1 in
def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
(ins i32imm:$label, pred:$p),
4, IIC_iALUi,
[]>, Sched<[WriteALU, ReadALU]>;
//===----------------------------------------------------------------------===//
// Load / store Instructions.
//
// Load
let canFoldAsLoad = 1, isReMaterializable = 1 in
defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, load>;
// Loads with zero extension
defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
GPRnopc, zextloadi16>;
defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
GPRnopc, zextloadi8>;
// Loads with sign extension
defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
GPRnopc, sextloadi16>;
defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
GPRnopc, sextloadi8>;
let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
// Load doubleword
def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
(ins t2addrmode_imm8s4:$addr),
IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "",
[(set rGPR:$Rt, rGPR:$Rt2, (ARMldrd t2addrmode_imm8s4:$addr))]>,
Sched<[WriteLd]>;
} // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
// zextload i1 -> zextload i8
def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
(t2LDRBi12 t2addrmode_imm12:$addr)>;
def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
(t2LDRBi8 t2addrmode_negimm8:$addr)>;
def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
(t2LDRBs t2addrmode_so_reg:$addr)>;
def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
(t2LDRBpci tconstpool:$addr)>;
// extload -> zextload
// FIXME: Reduce the number of patterns by legalizing extload to zextload
// earlier?
def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
(t2LDRBi12 t2addrmode_imm12:$addr)>;
def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
(t2LDRBi8 t2addrmode_negimm8:$addr)>;
def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
(t2LDRBs t2addrmode_so_reg:$addr)>;
def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
(t2LDRBpci tconstpool:$addr)>;
def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
(t2LDRBi12 t2addrmode_imm12:$addr)>;
def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
(t2LDRBi8 t2addrmode_negimm8:$addr)>;
def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
(t2LDRBs t2addrmode_so_reg:$addr)>;
def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
(t2LDRBpci tconstpool:$addr)>;
def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
(t2LDRHi12 t2addrmode_imm12:$addr)>;
def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
(t2LDRHi8 t2addrmode_negimm8:$addr)>;
def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
(t2LDRHs t2addrmode_so_reg:$addr)>;
def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
(t2LDRHpci tconstpool:$addr)>;
// FIXME: The destination register of the loads and stores can't be PC, but
// can be SP. We need another regclass (similar to rGPR) to represent
// that. Not a pressing issue since these are selected manually,
// not via pattern.
// Indexed loads
let mayLoad = 1, hasSideEffects = 0 in {
def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
"ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
Sched<[WriteLd]>;
def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
"ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
Sched<[WriteLd]>;
def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
"ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
Sched<[WriteLd]>;
def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
"ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
Sched<[WriteLd]>;
def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
"ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
Sched<[WriteLd]>;
def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
"ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
Sched<[WriteLd]>;
def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
"ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
[]>, Sched<[WriteLd]>;
def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
"ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
Sched<[WriteLd]>;
def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
"ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
[]>, Sched<[WriteLd]>;
def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
"ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
Sched<[WriteLd]>;
} // mayLoad = 1, hasSideEffects = 0
// F5.1.72 LDR (immediate) T4
// .w suffixes; Constraints can't be used on t2InstAlias to describe
// "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
def t2LDR_PRE_imm : t2AsmPseudo<"ldr${p}.w $Rt, $addr!",
(ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;
def t2LDR_POST_imm : t2AsmPseudo<"ldr${p}.w $Rt, $Rn, $imm",
(ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;
// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
: T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
"\t$Rt, $addr", []>, Sched<[WriteLd]> {
bits<4> Rt;
bits<13> addr;
let Inst{31-27} = 0b11111;
let Inst{26-25} = 0b00;
let Inst{24} = signed;
let Inst{23} = 0;
let Inst{22-21} = type;
let Inst{20} = 1; // load
let Inst{19-16} = addr{12-9};
let Inst{15-12} = Rt;
let Inst{11} = 1;
let Inst{10-8} = 0b110; // PUW.
let Inst{7-0} = addr{7-0};
let DecoderMethod = "DecodeT2LoadT";
}
def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops,
string opc, string asm, list<dag> pattern>
: Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary,
opc, asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]> {
bits<4> Rt;
bits<4> addr;
let Inst{31-27} = 0b11101;
let Inst{26-24} = 0b000;
let Inst{23-20} = bits23_20;
let Inst{11-6} = 0b111110;
let Inst{5-4} = bit54;
let Inst{3-0} = 0b1111;
// Encode instruction operands
let Inst{19-16} = addr;
let Inst{15-12} = Rt;
}
def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt),
(ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>,
Sched<[WriteLd]>;
def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
(ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>,
Sched<[WriteLd]>;
def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt),
(ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>,
Sched<[WriteLd]>;
// Store
defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, store>;
defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
rGPR, truncstorei8>;
defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
rGPR, truncstorei16>;
// Store doubleword
let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in
def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
(ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "",
[(ARMstrd rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr)]>,
Sched<[WriteST]>;
// Indexed stores
let mayStore = 1, hasSideEffects = 0 in {
def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
(ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
"str", "\t$Rt, $addr!",
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
Sched<[WriteST]>;
def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
(ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
"strh", "\t$Rt, $addr!",
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
Sched<[WriteST]>;
def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
(ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
"strb", "\t$Rt, $addr!",
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
Sched<[WriteST]>;
} // mayStore = 1, hasSideEffects = 0
def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
(ins GPRnopc:$Rt, addr_offset_none:$Rn,
t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
"str", "\t$Rt, $Rn$offset",
"$Rn = $Rn_wb,@earlyclobber $Rn_wb",
[(set GPRnopc:$Rn_wb,
(post_store GPRnopc:$Rt, addr_offset_none:$Rn,
t2am_imm8_offset:$offset))]>,
Sched<[WriteST]>;
def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
(ins rGPR:$Rt, addr_offset_none:$Rn,
t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
"strh", "\t$Rt, $Rn$offset",
"$Rn = $Rn_wb,@earlyclobber $Rn_wb",
[(set GPRnopc:$Rn_wb,
(post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
t2am_imm8_offset:$offset))]>,
Sched<[WriteST]>;
def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
(ins rGPR:$Rt, addr_offset_none:$Rn,
t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
"strb", "\t$Rt, $Rn$offset",
"$Rn = $Rn_wb,@earlyclobber $Rn_wb",
[(set GPRnopc:$Rn_wb,
(post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
t2am_imm8_offset:$offset))]>,
Sched<[WriteST]>;
// Pseudo-instructions for pattern matching the pre-indexed stores. We can't
// put the patterns on the instruction definitions directly as ISel wants
// the address base and offset to be separate operands, not a single
// complex operand like we represent the instructions themselves. The
// pseudos map between the two.
let usesCustomInserter = 1,
Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
(ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
4, IIC_iStore_ru,
[(set GPRnopc:$Rn_wb,
(pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,
Sched<[WriteST]>;
def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
(ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
4, IIC_iStore_ru,
[(set GPRnopc:$Rn_wb,
(pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,
Sched<[WriteST]>;
def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
(ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
4, IIC_iStore_ru,
[(set GPRnopc:$Rn_wb,
(pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,
Sched<[WriteST]>;
}
// F5.1.229 STR (immediate) T4
// .w suffixes; Constraints can't be used on t2InstAlias to describe
// "$Rn = $Rn_wb,@earlyclobber $Rn_wb" on POST or
// "$addr.base = $Rn_wb,@earlyclobber $Rn_wb" on PRE.
def t2STR_PRE_imm : t2AsmPseudo<"str${p}.w $Rt, $addr!",
(ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;
def t2STR_POST_imm : t2AsmPseudo<"str${p}.w $Rt, $Rn, $imm",
(ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;
// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
// only.
// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
class T2IstT<bits<2> type, string opc, InstrItinClass ii>
: T2Ii8<(outs), (ins rGPR:$Rt, t2addrmode_imm8:$addr), ii, opc,
"\t$Rt, $addr", []>, Sched<[WriteST]> {
let Inst{31-27} = 0b11111;
let Inst{26-25} = 0b00;
let Inst{24} = 0; // not signed
let Inst{23} = 0;
let Inst{22-21} = type;
let Inst{20} = 0; // store
let Inst{11} = 1;
let Inst{10-8} = 0b110; // PUW
bits<4> Rt;
bits<13> addr;
let Inst{15-12} = Rt;
let Inst{19-16} = addr{12-9};
let Inst{7-0} = addr{7-0};
}
def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
// ldrd / strd pre / post variants
let mayLoad = 1, hasSideEffects = 0 in
def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
(ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
"ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
Sched<[WriteLd]> {
let DecoderMethod = "DecodeT2LDRDPreInstruction";
}
let mayLoad = 1, hasSideEffects = 0 in
def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
(ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
"$addr.base = $wb", []>, Sched<[WriteLd]>;
let mayStore = 1, hasSideEffects = 0 in
def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
(ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
"$addr.base = $wb", []>, Sched<[WriteST]> {
let DecoderMethod = "DecodeT2STRDPreInstruction";
}
let mayStore = 1, hasSideEffects = 0 in
def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
(ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
t2am_imm8s4_offset:$imm),
IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
"$addr.base = $wb", []>, Sched<[WriteST]>;
class T2Istrrel<bits<2> bit54, dag oops, dag iops,
string opc, string asm, list<dag> pattern>
: Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc,
asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]>,
Sched<[WriteST]> {
bits<4> Rt;
bits<4> addr;
let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0001100;
let Inst{11-6} = 0b111110;
let Inst{5-4} = bit54;
let Inst{3-0} = 0b1111;
// Encode instruction operands
let Inst{19-16} = addr;
let Inst{15-12} = Rt;
}
def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
"stl", "\t$Rt, $addr", []>;
def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
"stlb", "\t$Rt, $addr", []>;
def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
"stlh", "\t$Rt, $addr", []>;
// T2Ipl (Preload Data/Instruction) signals the memory system of possible future
// data/instruction access.
// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
// (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
"\t$addr",
[(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,
Sched<[WritePreLd]> {
let Inst{31-25} = 0b1111100;
let Inst{24} = instr;
let Inst{23} = 1;
let Inst{22} = 0;
let Inst{21} = write;
let Inst{20} = 1;
let Inst{15-12} = 0b1111;
bits<17> addr;
let Inst{19-16} = addr{16-13}; // Rn
let Inst{11-0} = addr{11-0}; // imm12
let DecoderMethod = "DecodeT2LoadImm12";
}
def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
"\t$addr",
[(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,
Sched<[WritePreLd]> {
let Inst{31-25} = 0b1111100;
let Inst{24} = instr;
let Inst{23} = 0; // U = 0
let Inst{22} = 0;
let Inst{21} = write;
let Inst{20} = 1;
let Inst{15-12} = 0b1111;
let Inst{11-8} = 0b1100;
bits<13> addr;
let Inst{19-16} = addr{12-9}; // Rn
let Inst{7-0} = addr{7-0}; // imm8
let DecoderMethod = "DecodeT2LoadImm8";
}
def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
"\t$addr",
[(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,
Sched<[WritePreLd]> {
let Inst{31-25} = 0b1111100;
let Inst{24} = instr;
let Inst{23} = 0; // add = TRUE for T1
let Inst{22} = 0;
let Inst{21} = write;
let Inst{20} = 1;
let Inst{15-12} = 0b1111;
let Inst{11-6} = 0b000000;
bits<10> addr;
let Inst{19-16} = addr{9-6}; // Rn
let Inst{3-0} = addr{5-2}; // Rm
let Inst{5-4} = addr{1-0}; // imm2
let DecoderMethod = "DecodeT2LoadShift";
}
}
defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
// PLD/PLDW/PLI aliases w/ the optional .w suffix
def : t2InstAlias<"pld${p}.w\t$addr",
(t2PLDi12 t2addrmode_imm12:$addr, pred:$p)>;
def : t2InstAlias<"pld${p}.w\t$addr",
(t2PLDi8 t2addrmode_negimm8:$addr, pred:$p)>;
def : t2InstAlias<"pld${p}.w\t$addr",
(t2PLDs t2addrmode_so_reg:$addr, pred:$p)>;
def : InstAlias<"pldw${p}.w\t$addr",
(t2PLDWi12 t2addrmode_imm12:$addr, pred:$p), 0>,
Requires<[IsThumb2,HasV7,HasMP]>;
def : InstAlias<"pldw${p}.w\t$addr",
(t2PLDWi8 t2addrmode_negimm8:$addr, pred:$p), 0>,
Requires<[IsThumb2,HasV7,HasMP]>;
def : InstAlias<"pldw${p}.w\t$addr",
(t2PLDWs t2addrmode_so_reg:$addr, pred:$p), 0>,
Requires<[IsThumb2,HasV7,HasMP]>;
def : InstAlias<"pli${p}.w\t$addr",
(t2PLIi12 t2addrmode_imm12:$addr, pred:$p), 0>,
Requires<[IsThumb2,HasV7]>;
def : InstAlias<"pli${p}.w\t$addr",
(t2PLIi8 t2addrmode_negimm8:$addr, pred:$p), 0>,
Requires<[IsThumb2,HasV7]>;
def : InstAlias<"pli${p}.w\t$addr",
(t2PLIs t2addrmode_so_reg:$addr, pred:$p), 0>,
Requires<[IsThumb2,HasV7]>;
// pci variant is very similar to i12, but supports negative offsets
// from the PC. Only PLD and PLI have pci variants (not PLDW)
class T2Iplpci<bits<1> inst, string opc> : T2Ipc<(outs), (ins t2ldrlabel:$addr),
IIC_Preload, opc, "\t$addr",
[(ARMPreload (ARMWrapper tconstpool:$addr),
(i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
let Inst{31-25} = 0b1111100;
let Inst{24} = inst;
let Inst{22-20} = 0b001;
let Inst{19-16} = 0b1111;
let Inst{15-12} = 0b1111;
bits<13> addr;
let Inst{23} = addr{12}; // add = (U == '1')
let Inst{11-0} = addr{11-0}; // imm12
let DecoderMethod = "DecodeT2LoadLabel";
}
def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
def : t2InstAlias<"pld${p}.w $addr",
(t2PLDpci t2ldrlabel:$addr, pred:$p)>;
def : InstAlias<"pli${p}.w $addr",
(t2PLIpci t2ldrlabel:$addr, pred:$p), 0>,
Requires<[IsThumb2,HasV7]>;
// PLD/PLI with alternate literal form.
def : t2InstAlias<"pld${p} $addr",
(t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
def : InstAlias<"pli${p} $addr",
(t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
Requires<[IsThumb2,HasV7]>;
def : t2InstAlias<"pld${p}.w $addr",
(t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
def : InstAlias<"pli${p}.w $addr",
(t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
Requires<[IsThumb2,HasV7]>;
//===----------------------------------------------------------------------===//
// Load / store multiple Instructions.
//
multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
InstrItinClass itin_upd, bit L_bit> {
def IA :
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
bits<4> Rn;
bits<16> regs;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00;
let Inst{24-23} = 0b01; // Increment After
let Inst{22} = 0;
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
let Inst{19-16} = Rn;
let Inst{15-0} = regs;
}
def IA_UPD :
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
bits<4> Rn;
bits<16> regs;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00;
let Inst{24-23} = 0b01; // Increment After
let Inst{22} = 0;
let Inst{21} = 1; // Writeback
let Inst{20} = L_bit;
let Inst{19-16} = Rn;
let Inst{15-0} = regs;
}
def DB :
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
bits<4> Rn;
bits<16> regs;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00;
let Inst{24-23} = 0b10; // Decrement Before
let Inst{22} = 0;
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
let Inst{19-16} = Rn;
let Inst{15-0} = regs;
}
def DB_UPD :
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
bits<4> Rn;
bits<16> regs;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00;
let Inst{24-23} = 0b10; // Decrement Before
let Inst{22} = 0;
let Inst{21} = 1; // Writeback
let Inst{20} = L_bit;
let Inst{19-16} = Rn;
let Inst{15-0} = regs;
}
}
let hasSideEffects = 0 in {
let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
multiclass thumb2_st_mult<string asm, InstrItinClass itin,
InstrItinClass itin_upd, bit L_bit> {
def IA :
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
bits<4> Rn;
bits<16> regs;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00;
let Inst{24-23} = 0b01; // Increment After
let Inst{22} = 0;
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
let Inst{19-16} = Rn;
let Inst{15} = 0;
let Inst{14} = regs{14};
let Inst{13} = 0;
let Inst{12-0} = regs{12-0};
}
def IA_UPD :
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
bits<4> Rn;
bits<16> regs;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00;
let Inst{24-23} = 0b01; // Increment After
let Inst{22} = 0;
let Inst{21} = 1; // Writeback
let Inst{20} = L_bit;
let Inst{19-16} = Rn;
let Inst{15} = 0;
let Inst{14} = regs{14};
let Inst{13} = 0;
let Inst{12-0} = regs{12-0};
}
def DB :
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
bits<4> Rn;
bits<16> regs;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00;
let Inst{24-23} = 0b10; // Decrement Before
let Inst{22} = 0;
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
let Inst{19-16} = Rn;
let Inst{15} = 0;
let Inst{14} = regs{14};
let Inst{13} = 0;
let Inst{12-0} = regs{12-0};
}
def DB_UPD :
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
bits<4> Rn;
bits<16> regs;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00;
let Inst{24-23} = 0b10; // Decrement Before
let Inst{22} = 0;
let Inst{21} = 1; // Writeback
let Inst{20} = L_bit;
let Inst{19-16} = Rn;
let Inst{15} = 0;
let Inst{14} = regs{14};
let Inst{13} = 0;
let Inst{12-0} = regs{12-0};
}
}
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
} // hasSideEffects
//===----------------------------------------------------------------------===//
// Move Instructions.
//
let hasSideEffects = 0 in
def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rm), IIC_iMOVr,
"mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = 0b0010;
let Inst{19-16} = 0b1111; // Rn
let Inst{15} = 0b0;
let Inst{14-12} = 0b000;
let Inst{7-4} = 0b0000;
}
def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
pred:$p, zero_reg)>;
def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
pred:$p, CPSR)>;
def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
pred:$p, CPSR)>;
// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
AddedComplexity = 1 in
def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
"mov", ".w\t$Rd, $imm",
[(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = 0b0010;
let Inst{19-16} = 0b1111; // Rn
let Inst{15} = 0;
}
// cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
// Use aliases to get that to play nice here.
def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
pred:$p, CPSR)>;
def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
pred:$p, CPSR)>;
def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
pred:$p, zero_reg)>;
def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
pred:$p, zero_reg)>;
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
"movw", "\t$Rd, $imm",
[(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>,
Requires<[IsThumb, HasV8MBaseline]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 1;
let Inst{24-21} = 0b0010;
let Inst{20} = 0; // The S bit.
let Inst{15} = 0;
bits<4> Rd;
bits<16> imm;
let Inst{11-8} = Rd;
let Inst{19-16} = imm{15-12};
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0};
let DecoderMethod = "DecodeT2MOVTWInstruction";
}
def : InstAlias<"mov${p} $Rd, $imm",
(t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,
Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteALU]>;
def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
(ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
Sched<[WriteALU]>;
let Constraints = "$src = $Rd" in {
def t2MOVTi16 : T2I<(outs rGPR:$Rd),
(ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
"movt", "\t$Rd, $imm",
[(set rGPR:$Rd,
(or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
Sched<[WriteALU]>,
Requires<[IsThumb, HasV8MBaseline]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 1;
let Inst{24-21} = 0b0110;
let Inst{20} = 0; // The S bit.
let Inst{15} = 0;
bits<4> Rd;
bits<16> imm;
let Inst{11-8} = Rd;
let Inst{19-16} = imm{15-12};
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0};
let DecoderMethod = "DecodeT2MOVTWInstruction";
}
def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
(ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>;
} // Constraints
def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
//===----------------------------------------------------------------------===//
// Extend Instructions.
//
// Sign extenders
def t2SXTB : T2I_ext_rrot<0b100, "sxtb">;
def t2SXTH : T2I_ext_rrot<0b000, "sxth">;
def t2SXTB16 : T2I_ext_rrot_xtb16<0b010, "sxtb16">;
def t2SXTAB : T2I_exta_rrot<0b100, "sxtab">;
def t2SXTAH : T2I_exta_rrot<0b000, "sxtah">;
def t2SXTAB16 : T2I_exta_rrot<0b010, "sxtab16">;
def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i8),
(t2SXTB rGPR:$Rn, rot_imm:$rot)>;
def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i16),
(t2SXTH rGPR:$Rn, rot_imm:$rot)>;
def : Thumb2DSPPat<(add rGPR:$Rn,
(sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i8)),
(t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
def : Thumb2DSPPat<(add rGPR:$Rn,
(sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i16)),
(t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
def : Thumb2DSPPat<(int_arm_sxtb16 rGPR:$Rn),
(t2SXTB16 rGPR:$Rn, 0)>;
def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, rGPR:$Rm),
(t2SXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>;
def : Thumb2DSPPat<(int_arm_sxtb16 (rotr rGPR:$Rn, rot_imm:$rot)),
(t2SXTB16 rGPR:$Rn, rot_imm:$rot)>;
def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)),
(t2SXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
// A simple right-shift can also be used in most cases (the exception is the
// SXTH operations with a rotate of 24: there the non-contiguous bits are
// relevant).
def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
(srl rGPR:$Rm, rot_imm:$rot), i8)),
(t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
(srl rGPR:$Rm, imm8_or_16:$rot), i16)),
(t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
(rotr rGPR:$Rm, (i32 24)), i16)),
(t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;
def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
(or (srl rGPR:$Rm, (i32 24)),
(shl rGPR:$Rm, (i32 8))), i16)),
(t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;
// Zero extenders
let AddedComplexity = 16 in {
def t2UXTB : T2I_ext_rrot<0b101, "uxtb">;
def t2UXTH : T2I_ext_rrot<0b001, "uxth">;
def t2UXTB16 : T2I_ext_rrot_xtb16<0b011, "uxtb16">;
def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x000000FF),
(t2UXTB rGPR:$Rm, rot_imm:$rot)>;
def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x0000FFFF),
(t2UXTH rGPR:$Rm, rot_imm:$rot)>;
def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x00FF00FF),
(t2UXTB16 rGPR:$Rm, rot_imm:$rot)>;
def : Thumb2DSPPat<(int_arm_uxtb16 rGPR:$Rm),
(t2UXTB16 rGPR:$Rm, 0)>;
def : Thumb2DSPPat<(int_arm_uxtb16 (rotr rGPR:$Rn, rot_imm:$rot)),
(t2UXTB16 rGPR:$Rn, rot_imm:$rot)>;
// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
// The transformation should probably be done as a combiner action
// instead so we can include a check for masking back in the upper
// eight bits of the source into the lower eight bits of the result.
//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
// (t2UXTB16 rGPR:$Src, 3)>,
// Requires<[HasDSP, IsThumb2]>;
def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
(t2UXTB16 rGPR:$Src, 1)>,
Requires<[HasDSP, IsThumb2]>;
def t2UXTAB : T2I_exta_rrot<0b101, "uxtab">;
def t2UXTAH : T2I_exta_rrot<0b001, "uxtah">;
def t2UXTAB16 : T2I_exta_rrot<0b011, "uxtab16">;
def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot),
0x00FF)),
(t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot),
0xFFFF)),
(t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot),
0xFF)),
(t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot),
0xFFFF)),
(t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, rGPR:$Rm),
(t2UXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>;
def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)),
(t2UXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
}
//===----------------------------------------------------------------------===//
// Arithmetic Instructions.
//
let isAdd = 1 in
defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>;
defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>;
// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
//
// Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
// selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
// AdjustInstrPostInstrSelection where we determine whether or n