| //===- ARCInstrInfo.h - ARC Instruction Information -------------*- C++ -*-===// |
| // |
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| // See https://llvm.org/LICENSE.txt for license information. |
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // This file contains the ARC implementation of the TargetInstrInfo class. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| #ifndef LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H |
| #define LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H |
| |
| #include "ARCRegisterInfo.h" |
| #include "llvm/CodeGen/TargetInstrInfo.h" |
| |
| #define GET_INSTRINFO_HEADER |
| #include "ARCGenInstrInfo.inc" |
| |
| namespace llvm { |
| |
| class ARCSubtarget; |
| |
| class ARCInstrInfo : public ARCGenInstrInfo { |
| const ARCRegisterInfo RI; |
| virtual void anchor(); |
| |
| public: |
| ARCInstrInfo(const ARCSubtarget &); |
| |
| const ARCRegisterInfo &getRegisterInfo() const { return RI; } |
| |
| /// If the specified machine instruction is a direct |
| /// load from a stack slot, return the virtual or physical register number of |
| /// the destination along with the FrameIndex of the loaded stack slot. If |
| /// not, return 0. This predicate must return 0 if the instruction has |
| /// any side effects other than loading from the stack slot. |
| unsigned isLoadFromStackSlot(const MachineInstr &MI, |
| int &FrameIndex) const override; |
| |
| /// If the specified machine instruction is a direct |
| /// store to a stack slot, return the virtual or physical register number of |
| /// the source reg along with the FrameIndex of the loaded stack slot. If |
| /// not, return 0. This predicate must return 0 if the instruction has |
| /// any side effects other than storing to the stack slot. |
| unsigned isStoreToStackSlot(const MachineInstr &MI, |
| int &FrameIndex) const override; |
| |
| unsigned getInstSizeInBytes(const MachineInstr &MI) const override; |
| |
| bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
| MachineBasicBlock *&FBB, |
| SmallVectorImpl<MachineOperand> &Cond, |
| bool AllowModify) const override; |
| |
| unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
| MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, |
| const DebugLoc &, |
| int *BytesAdded = nullptr) const override; |
| |
| unsigned removeBranch(MachineBasicBlock &MBB, |
| int *BytesRemoved = nullptr) const override; |
| |
| void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| const DebugLoc &, MCRegister DestReg, MCRegister SrcReg, |
| bool KillSrc) const override; |
| |
| void storeRegToStackSlot(MachineBasicBlock &MBB, |
| MachineBasicBlock::iterator MI, Register SrcReg, |
| bool IsKill, int FrameIndex, |
| const TargetRegisterClass *RC, |
| const TargetRegisterInfo *TRI) const override; |
| |
| void loadRegFromStackSlot(MachineBasicBlock &MBB, |
| MachineBasicBlock::iterator MI, Register DestReg, |
| int FrameIndex, const TargetRegisterClass *RC, |
| const TargetRegisterInfo *TRI) const override; |
| |
| bool |
| reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; |
| |
| |
| bool isPostIncrement(const MachineInstr &MI) const override; |
| |
| // ARC-specific |
| bool isPreIncrement(const MachineInstr &MI) const; |
| |
| virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, |
| unsigned &BasePos, |
| unsigned &OffsetPos) const override; |
| |
| // Emit code before MBBI to load immediate value into physical register Reg. |
| // Returns an iterator to the new instruction. |
| MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, |
| MachineBasicBlock::iterator MI, |
| unsigned Reg, uint64_t Value) const; |
| }; |
| |
| } // end namespace llvm |
| |
| #endif // LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H |