llvm/test/CodeGen/AArch64/force-enable-intervals.mir

# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
# RUN:  -misched-dump-reserved-cycles=true \
# RUN:  -run-pass=machine-scheduler -debug-only=machine-scheduler \
# RUN:  -o - %s 2>&1 -misched-topdown| FileCheck %s 

# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
# RUN:  -misched-dump-reserved-cycles=true -sched-model-force-enable-intervals=true \
# RUN:  -run-pass=machine-scheduler -debug-only=machine-scheduler \
# RUN:  -o - %s 2>&1 -misched-topdown| FileCheck %s  --check-prefix=FORCE

# REQUIRES: asserts, aarch64-registered-target
---
name: f
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0, $x10
    $x1 = ADDXrr $x0, $x0
    $x2 = ADDXrr $x1, $x1
    $x3 = ADDXrr $x2, $x2
    STRXui $x3, $x10, 1 :: (store (s64))


# CHECK-LABEL: Scheduling SU(3) STRXui $x3, $x10, 1 :: (store (s64))
# CHECK-NEXT:   Ready @5c
# CHECK-NEXT:   CortexA55UnitSt +1x2u
# CHECK-NEXT:   TopQ.A TopLatency SU(3) 5c
# CHECK-NEXT: TopQ.A @5c
# CHECK-NEXT:   Retired: 4
# CHECK-NEXT:   Executed: 5c
# CHECK-NEXT:   Critical: 2c, 4 MOps
# CHECK-NEXT:   ExpectedLatency: 5c
# CHECK-NEXT:   - Latency limited.
# CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 4294967295
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295
# CHECK-NEXT: CortexA55UnitDiv(0) = 4294967295
# CHECK-NEXT: CortexA55UnitFPALU(0) = 4294967295
# CHECK-NEXT: CortexA55UnitFPALU(1) = 4294967295
# CHECK-NEXT: CortexA55UnitFPDIV(0) = 4294967295
# CHECK-NEXT: CortexA55UnitFPMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitFPMAC(1) = 4294967295
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 6


# FORCE-LABEL: Scheduling SU(3) STRXui $x3, $x10, 1 :: (store (s64))
# FORCE-NEXT:   Ready @5c
# FORCE-NEXT:   CortexA55UnitSt +1x2u
# FORCE-NEXT:   TopQ.A TopLatency SU(3) 5c
# FORCE-NEXT: TopQ.A @5c
# FORCE-NEXT:   Retired: 4
# FORCE-NEXT:   Executed: 5c
# FORCE-NEXT:   Critical: 2c, 4 MOps
# FORCE-NEXT:   ExpectedLatency: 5c
# FORCE-NEXT:   - Latency limited.
# FORCE-NEXT: CortexA55UnitALU(0) = { [0, 3), }
# FORCE-NEXT: CortexA55UnitALU(1) = { }
# FORCE-NEXT: CortexA55UnitB(0) = { }
# FORCE-NEXT: CortexA55UnitDiv(0) = { }
# FORCE-NEXT: CortexA55UnitFPALU(0) = { }
# FORCE-NEXT: CortexA55UnitFPALU(1) = { }
# FORCE-NEXT: CortexA55UnitFPDIV(0) = { }
# FORCE-NEXT: CortexA55UnitFPMAC(0) = { }
# FORCE-NEXT: CortexA55UnitFPMAC(1) = { }
# FORCE-NEXT: CortexA55UnitLd(0) = { }
# FORCE-NEXT: CortexA55UnitMAC(0) = { }
# FORCE-NEXT: CortexA55UnitSt(0) = { [5, 6), }