| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc < %s -mtriple aarch64-none-linux-gnu | FileCheck %s |
| |
| define <16 x i8> @test_combine_v8i16_to_v16i8(<8 x i16> %x, <8 x i16> %y) { |
| ; CHECK-LABEL: test_combine_v8i16_to_v16i8: |
| ; CHECK: // %bb.0: // %entry |
| ; CHECK-NEXT: movi v2.2d, #0000000000000000 |
| ; CHECK-NEXT: raddhn v0.8b, v0.8h, v2.8h |
| ; CHECK-NEXT: raddhn2 v0.16b, v1.8h, v2.8h |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %x, i32 8) |
| %res2 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %y, i32 8) |
| %shuffle = shufflevector <8 x i8> %res, <8 x i8> %res2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> |
| ret <16 x i8> %shuffle |
| } |
| |
| define <8 x i16> @test_combine_v4i32_to_v8i16(<4 x i32> %x, <4 x i32> %y) { |
| ; CHECK-LABEL: test_combine_v4i32_to_v8i16: |
| ; CHECK: // %bb.0: // %entry |
| ; CHECK-NEXT: movi v2.2d, #0000000000000000 |
| ; CHECK-NEXT: raddhn v0.4h, v0.4s, v2.4s |
| ; CHECK-NEXT: raddhn2 v0.8h, v1.4s, v2.4s |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %x, i32 16) |
| %res2 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %y, i32 16) |
| %shuffle = shufflevector <4 x i16> %res, <4 x i16> %res2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> |
| ret <8 x i16> %shuffle |
| } |
| |
| define <4 x i32> @test_combine_v2i64_to_v4i32(<2 x i64> %x, <2 x i64> %y) { |
| ; CHECK-LABEL: test_combine_v2i64_to_v4i32: |
| ; CHECK: // %bb.0: // %entry |
| ; CHECK-NEXT: movi v2.2d, #0000000000000000 |
| ; CHECK-NEXT: raddhn v0.2s, v0.2d, v2.2d |
| ; CHECK-NEXT: raddhn2 v0.4s, v1.2d, v2.2d |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %x, i32 32) |
| %res2 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %y, i32 32) |
| %shuffle = shufflevector <2 x i32> %res, <2 x i32> %res2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> |
| ret <4 x i32> %shuffle |
| } |
| |
| declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32) |
| declare <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32>, i32) |
| declare <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64>, i32) |