llvm/test/CodeGen/X86/amx_tile_pair_preconfigure_O0.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-bf16,+avx512f, \
# RUN: -mattr=+amx-transpose -run-pass=fastpretileconfig -o - %s | FileCheck %s

---
name:            test_tile_2rpntlvwz0
alignment:       16
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
callsEHReturn:   false
callsUnwindInit: false
hasEHCatchret:   false
hasEHScopes:     false
hasEHFunclets:   false
failsVerification: false
tracksDebugUserValues: false
registers:
  - { id: 0, class: gr64_nosp, preferred-register: '' }
  - { id: 1, class: gr16, preferred-register: '' }
  - { id: 2, class: gr16, preferred-register: '' }
  - { id: 3, class: gr16, preferred-register: '' }
  - { id: 4, class: gr64, preferred-register: '' }
  - { id: 5, class: gr64, preferred-register: '' }
  - { id: 6, class: gr64, preferred-register: '' }
  - { id: 7, class: gr64_nosp, preferred-register: '' }
  - { id: 8, class: tilepair, preferred-register: '' }
  - { id: 9, class: tile, preferred-register: '' }
  - { id: 10, class: tile, preferred-register: '' }
  - { id: 11, class: tile, preferred-register: '' }
  - { id: 181, class: tile, preferred-register: '' }
  - { id: 183, class: tile, preferred-register: '' }
  - { id: 185, class: tile, preferred-register: '' }
  - { id: 186, class: tile, preferred-register: '' }
liveins:
  - { reg: '$edi', virtual-reg: '%0' }
  - { reg: '$esi', virtual-reg: '%1' }
  - { reg: '$edx', virtual-reg: '%2' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1024
  adjustsStack:    false
  hasCalls:        true
  stackProtector:  ''
  functionContext: ''
  maxCallFrameSize: 4294967295
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  hasTailCall:     false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 18, name: '', type: default, offset: 0, size: 8, alignment: 8,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 19, name: '', type: default, offset: 0, size: 8, alignment: 8,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 20, name: '', type: default, offset: 0, size: 8, alignment: 8,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 21, name: '', type: default, offset: 0, size: 8,
      alignment: 8, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
debugValueSubstitutions: []
constants:       []
machineFunctionInfo:
  amxProgModel: ManagedRA
body:             |
  bb.0.entry:
    liveins: $rdi, $rsi, $rdx, $rax

    ; CHECK-LABEL: name: test_tile_2rpntlvwz0
    ; CHECK: liveins: $rdi, $rsi, $rdx, $rax
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[AVX512_512_SET0_:%[0-9]+]]:vr512 = AVX512_512_SET0
    ; CHECK-NEXT: VMOVUPSZmr %stack.4, 1, $noreg, 0, $noreg, [[AVX512_512_SET0_]] :: (store (s512) into %stack.4, align 4)
    ; CHECK-NEXT: MOV8mi %stack.4, 1, $noreg, 0, $noreg, 1 :: (store (s512) into %stack.4, align 4)
    ; CHECK-NEXT: [[MOV32ri64_:%[0-9]+]]:gr64_nosp = MOV32ri64 64
    ; CHECK-NEXT: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 64
    ; CHECK-NEXT: [[MOV16ri1:%[0-9]+]]:gr16 = MOV16ri 16
    ; CHECK-NEXT: [[MOV16ri2:%[0-9]+]]:gr16 = MOV16ri 16
    ; CHECK-NEXT: PLDTILECFGV %stack.4, 1, $noreg, 0, $noreg, implicit-def $tmm0, implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3, implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7 :: (load (s512) from %stack.4, align 4)
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64_nosp = COPY $rax
    ; CHECK-NEXT: [[PT2RPNTLVWZ0V:%[0-9]+]]:tilepair = PT2RPNTLVWZ0V [[MOV16ri]], [[MOV16ri1]], [[MOV16ri2]], [[COPY2]], 1, killed [[COPY3]], 0, $noreg
    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:tile = COPY [[PT2RPNTLVWZ0V]].sub_t1
    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:tile = COPY [[PT2RPNTLVWZ0V]].sub_t0
    ; CHECK-NEXT: PTILESTOREDV [[MOV16ri]], [[MOV16ri1]], [[COPY]], 1, [[MOV32ri64_]], 0, $noreg, killed [[COPY5]]
    ; CHECK-NEXT: PTILESTOREDV [[MOV16ri]], [[MOV16ri2]], [[COPY1]], 1, [[MOV32ri64_]], 0, $noreg, killed [[COPY4]]
    ; CHECK-NEXT: [[PTILEZEROV:%[0-9]+]]:tile = PTILEZEROV [[MOV16ri]], [[MOV16ri1]]
    ; CHECK-NEXT: PTILESTOREDV [[MOV16ri]], [[MOV16ri1]], [[COPY2]], 1, [[MOV32ri64_]], 0, $noreg, killed [[PTILEZEROV]]
    ; CHECK-NEXT: [[PTILELOADDV:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri]], [[MOV16ri1]], [[COPY]], 1, [[MOV32ri64_]], 0, $noreg
    ; CHECK-NEXT: [[PTILELOADDV1:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri]], [[MOV16ri2]], [[COPY1]], 1, [[MOV32ri64_]], 0, $noreg
    ; CHECK-NEXT: [[PTILELOADDV2:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri]], [[MOV16ri1]], [[COPY2]], 1, [[MOV32ri64_]], 0, $noreg
    ; CHECK-NEXT: [[PTDPBSSDV:%[0-9]+]]:tile = PTDPBSSDV [[MOV16ri]], [[MOV16ri1]], [[MOV16ri2]], [[PTILELOADDV]], killed [[PTILELOADDV1]], killed [[PTILELOADDV2]]
    ; CHECK-NEXT: PTILESTOREDV killed [[MOV16ri]], killed [[MOV16ri1]], killed [[COPY2]], 1, killed [[MOV32ri64_]], 0, $noreg, killed [[PTDPBSSDV]]
    %0:gr64_nosp = MOV32ri64 64
    %1:gr16 = MOV16ri 64
    %2:gr16 = MOV16ri 16
    %3:gr16 = MOV16ri 16
    %4:gr64 = COPY $rsi
    %5:gr64 = COPY $rdi
    %6:gr64 = COPY $rdx
    %7:gr64_nosp = COPY $rax
    %8:tilepair = PT2RPNTLVWZ0V %1, %2, %3, %6, 1, killed %7, 0, $noreg
    %9:tile = COPY %8.sub_t1
    %10:tile = COPY %8.sub_t0
    PTILESTOREDV %1, %2, %4, 1, %0, 0, $noreg, killed %10
    PTILESTOREDV %1, %3, %5, 1, %0, 0, $noreg, killed %9
    %11:tile = PTILEZEROV %1, %2
    PTILESTOREDV %1, %2, %6, 1, %0, 0, $noreg, killed %11
    %181:tile = PTILELOADDV %1, %2, %4, 1, %0, 0, $noreg
    %183:tile = PTILELOADDV %1, %3, %5, 1, %0, 0, $noreg
    %185:tile = PTILELOADDV %1, %2, %6, 1, %0, 0, $noreg
    %186:tile = PTDPBSSDV %1, %2, %3, %181, killed %183, killed %185
    PTILESTOREDV killed %1, killed %2, killed %6, 1, killed %0, 0, $noreg, killed %186
...