llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx90a | FileCheck %s

define amdgpu_kernel void @copy_to_reg_frameindex(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: copy_to_reg_frameindex:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    ; implicit-def: $vgpr0
; CHECK-NEXT:  .LBB0_1: ; %loop
; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    s_cmp_lt_u32 0, 16
; CHECK-NEXT:    s_set_gpr_idx_on 0, gpr_idx(DST)
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    s_set_gpr_idx_off
; CHECK-NEXT:    s_cbranch_scc1 .LBB0_1
; CHECK-NEXT:  ; %bb.2: ; %done
; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; CHECK-NEXT:    v_mov_b32_e32 v1, 0
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    global_store_dword v1, v0, s[0:1]
; CHECK-NEXT:    s_endpgm
entry:
  %B = srem i32 %c, -1
  br label %loop

loop:
  %promotealloca = phi <16 x i32> [ undef, %entry ], [ %0, %loop ]
  %inc = phi i32 [ 0, %entry ], [ %inc.i, %loop ]
  %0 = insertelement <16 x i32> %promotealloca, i32 %inc, i32 %inc
  %inc.i = add i32 %inc, %B
  %cnd = icmp uge i32 %inc.i, 16
  br i1 %cnd, label %done, label %loop

done:
  %1 = extractelement <16 x i32> %0, i32 0
  store i32 %1, ptr addrspace(1) %out, align 4
  ret void
}