| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --prefix-filecheck-ir-name VAR_ --version 6 |
| ; RUN: opt -S -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=2 < %s | FileCheck %s |
| |
| @global = global i32 0, align 4 |
| @global.1 = global i32 0, align 4 |
| @global.2 = global float 0x3EF0000000000000, align 4 |
| |
| define void @PR33706(ptr nocapture readonly %arg, ptr nocapture %arg1, i32 %arg2) { |
| ; CHECK-LABEL: define void @PR33706( |
| ; CHECK-SAME: ptr readonly captures(none) [[ARG:%.*]], ptr captures(none) [[ARG1:%.*]], i32 [[ARG2:%.*]]) { |
| ; CHECK-NEXT: [[BB:.*:]] |
| ; CHECK-NEXT: [[TMP:%.*]] = load i32, ptr @global.1, align 4 |
| ; CHECK-NEXT: [[VAR_TMP3:%.*]] = getelementptr inbounds float, ptr [[ARG]], i64 190 |
| ; CHECK-NEXT: [[VAR_TMP4:%.*]] = getelementptr inbounds float, ptr [[ARG1]], i64 512 |
| ; CHECK-NEXT: [[VAR_TMP5:%.*]] = and i32 [[TMP]], 65535 |
| ; CHECK-NEXT: [[VAR_TMP6:%.*]] = icmp ugt i32 [[ARG2]], 65536 |
| ; CHECK-NEXT: br i1 [[VAR_TMP6]], label %[[VAR_BB7:.*]], label %[[VAR_BB9:.*]] |
| ; CHECK: [[VAR_BB7]]: |
| ; CHECK-NEXT: [[VAR_TMP8:%.*]] = load i32, ptr @global, align 4 |
| ; CHECK-NEXT: br label %[[VAR_BB27:.*]] |
| ; CHECK: [[VAR_BB9]]: |
| ; CHECK-NEXT: [[VAR_TMP10:%.*]] = udiv i32 65536, [[ARG2]] |
| ; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[ARG2]] to i16 |
| ; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TMP0]] to i32 |
| ; CHECK-NEXT: [[TMP2:%.*]] = add nsw i32 [[VAR_TMP10]], -1 |
| ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 |
| ; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 2 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]] |
| ; CHECK: [[VECTOR_SCEVCHECK]]: |
| ; CHECK-NEXT: [[TMP5:%.*]] = add nsw i32 [[VAR_TMP10]], -1 |
| ; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[ARG2]] to i16 |
| ; CHECK-NEXT: [[TMP7:%.*]] = sub i16 0, [[TMP6]] |
| ; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP]] to i16 |
| ; CHECK-NEXT: [[TMP9:%.*]] = icmp slt i16 [[TMP6]], 0 |
| ; CHECK-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i16 [[TMP7]], i16 [[TMP6]] |
| ; CHECK-NEXT: [[TMP11:%.*]] = trunc i32 [[TMP5]] to i16 |
| ; CHECK-NEXT: [[MUL:%.*]] = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 [[TMP10]], i16 [[TMP11]]) |
| ; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i16, i1 } [[MUL]], 0 |
| ; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i16, i1 } [[MUL]], 1 |
| ; CHECK-NEXT: [[TMP12:%.*]] = add i16 [[TMP8]], [[MUL_RESULT]] |
| ; CHECK-NEXT: [[TMP13:%.*]] = sub i16 [[TMP8]], [[MUL_RESULT]] |
| ; CHECK-NEXT: [[TMP14:%.*]] = icmp ult i16 [[TMP12]], [[TMP8]] |
| ; CHECK-NEXT: [[TMP15:%.*]] = icmp ugt i16 [[TMP13]], [[TMP8]] |
| ; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], i1 [[TMP15]], i1 [[TMP14]] |
| ; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP16]], [[MUL_OVERFLOW]] |
| ; CHECK-NEXT: [[TMP18:%.*]] = icmp ugt i32 [[TMP5]], 65535 |
| ; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i16 [[TMP6]], 0 |
| ; CHECK-NEXT: [[TMP20:%.*]] = and i1 [[TMP18]], [[TMP19]] |
| ; CHECK-NEXT: [[TMP21:%.*]] = or i1 [[TMP17]], [[TMP20]] |
| ; CHECK-NEXT: br i1 [[TMP21]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[TMP22:%.*]] = and i64 [[TMP4]], 1 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP4]], [[TMP22]] |
| ; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[N_VEC]] to i32 |
| ; CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[TMP23]], [[TMP1]] |
| ; CHECK-NEXT: [[TMP25:%.*]] = add i32 [[VAR_TMP5]], [[TMP24]] |
| ; CHECK-NEXT: [[TMP26:%.*]] = shl i64 [[N_VEC]], 2 |
| ; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[VAR_TMP4]], i64 [[TMP26]] |
| ; CHECK-NEXT: [[TMP28:%.*]] = sub i32 [[VAR_TMP10]], [[TMP23]] |
| ; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP23]], [[ARG2]] |
| ; CHECK-NEXT: [[TMP30:%.*]] = add i32 [[TMP]], [[TMP29]] |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[ARG2]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <2 x i32> poison, i32 [[VAR_TMP5]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT1]], <2 x i32> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP1]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT3]], <2 x i32> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP31:%.*]] = mul <2 x i32> <i32 0, i32 1>, [[BROADCAST_SPLAT4]] |
| ; CHECK-NEXT: [[INDUCTION:%.*]] = add <2 x i32> [[BROADCAST_SPLAT2]], [[TMP31]] |
| ; CHECK-NEXT: [[TMP32:%.*]] = shl i32 [[TMP1]], 1 |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement <2 x i32> poison, i32 [[TMP32]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT5]], <2 x i32> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT7:%.*]] = insertelement <2 x i32> poison, i32 [[TMP]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT8:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT7]], <2 x i32> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP33:%.*]] = mul <2 x i32> <i32 0, i32 1>, [[BROADCAST_SPLAT]] |
| ; CHECK-NEXT: [[INDUCTION9:%.*]] = add <2 x i32> [[BROADCAST_SPLAT8]], [[TMP33]] |
| ; CHECK-NEXT: [[TMP34:%.*]] = shl i32 [[ARG2]], 1 |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT10:%.*]] = insertelement <2 x i32> poison, i32 [[TMP34]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT11:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT10]], <2 x i32> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND12:%.*]] = phi <2 x i32> [ [[INDUCTION9]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT13:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP35:%.*]] = shl i64 [[INDEX]], 2 |
| ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[VAR_TMP4]], i64 [[TMP35]] |
| ; CHECK-NEXT: [[TMP36:%.*]] = sitofp <2 x i32> [[VEC_IND]] to <2 x float> |
| ; CHECK-NEXT: store <2 x float> [[TMP36]], ptr [[NEXT_GEP]], align 4 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 |
| ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], [[BROADCAST_SPLAT6]] |
| ; CHECK-NEXT: [[VEC_IND_NEXT13]] = add <2 x i32> [[VEC_IND12]], [[BROADCAST_SPLAT11]] |
| ; CHECK-NEXT: [[TMP37:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP37]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[TMP38:%.*]] = add <2 x i32> [[VEC_IND12]], [[BROADCAST_SPLAT]] |
| ; CHECK-NEXT: [[TMP39:%.*]] = and <2 x i32> [[TMP38]], splat (i32 65535) |
| ; CHECK-NEXT: [[TMP40:%.*]] = extractelement <2 x i32> [[TMP39]], i64 1 |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP4]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label %[[VAR_BB22:.*]], label %[[SCALAR_PH]] |
| ; CHECK: [[SCALAR_PH]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP25]], %[[MIDDLE_BLOCK]] ], [ [[VAR_TMP5]], %[[VAR_BB9]] ], [ [[VAR_TMP5]], %[[VECTOR_SCEVCHECK]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL14:%.*]] = phi ptr [ [[TMP27]], %[[MIDDLE_BLOCK]] ], [ [[VAR_TMP4]], %[[VAR_BB9]] ], [ [[VAR_TMP4]], %[[VECTOR_SCEVCHECK]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL15:%.*]] = phi i32 [ [[TMP28]], %[[MIDDLE_BLOCK]] ], [ [[VAR_TMP10]], %[[VAR_BB9]] ], [ [[VAR_TMP10]], %[[VECTOR_SCEVCHECK]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL16:%.*]] = phi i32 [ [[TMP30]], %[[MIDDLE_BLOCK]] ], [ [[TMP]], %[[VAR_BB9]] ], [ [[TMP]], %[[VECTOR_SCEVCHECK]] ] |
| ; CHECK-NEXT: br label %[[VAR_BB11:.*]] |
| ; CHECK: [[VAR_BB11]]: |
| ; CHECK-NEXT: [[VAR_TMP12:%.*]] = phi i32 [ [[VAR_TMP20:%.*]], %[[VAR_BB11]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] |
| ; CHECK-NEXT: [[VAR_TMP13:%.*]] = phi ptr [ [[VAR_TMP18:%.*]], %[[VAR_BB11]] ], [ [[BC_RESUME_VAL14]], %[[SCALAR_PH]] ] |
| ; CHECK-NEXT: [[VAR_TMP14:%.*]] = phi i32 [ [[VAR_TMP16:%.*]], %[[VAR_BB11]] ], [ [[BC_RESUME_VAL15]], %[[SCALAR_PH]] ] |
| ; CHECK-NEXT: [[VAR_TMP15:%.*]] = phi i32 [ [[VAR_TMP19:%.*]], %[[VAR_BB11]] ], [ [[BC_RESUME_VAL16]], %[[SCALAR_PH]] ] |
| ; CHECK-NEXT: [[VAR_TMP16]] = add nsw i32 [[VAR_TMP14]], -1 |
| ; CHECK-NEXT: [[VAR_TMP17:%.*]] = sitofp i32 [[VAR_TMP12]] to float |
| ; CHECK-NEXT: store float [[VAR_TMP17]], ptr [[VAR_TMP13]], align 4 |
| ; CHECK-NEXT: [[VAR_TMP18]] = getelementptr inbounds float, ptr [[VAR_TMP13]], i64 1 |
| ; CHECK-NEXT: [[VAR_TMP19]] = add i32 [[VAR_TMP15]], [[ARG2]] |
| ; CHECK-NEXT: [[VAR_TMP20]] = and i32 [[VAR_TMP19]], 65535 |
| ; CHECK-NEXT: [[VAR_TMP21:%.*]] = icmp eq i32 [[VAR_TMP16]], 0 |
| ; CHECK-NEXT: br i1 [[VAR_TMP21]], label %[[VAR_BB22]], label %[[VAR_BB11]], !llvm.loop [[LOOP3:![0-9]+]] |
| ; CHECK: [[VAR_BB22]]: |
| ; CHECK-NEXT: [[VAR_TMP23:%.*]] = phi ptr [ [[VAR_TMP18]], %[[VAR_BB11]] ], [ [[TMP27]], %[[MIDDLE_BLOCK]] ] |
| ; CHECK-NEXT: [[VAR_TMP24:%.*]] = phi i32 [ [[VAR_TMP19]], %[[VAR_BB11]] ], [ [[TMP30]], %[[MIDDLE_BLOCK]] ] |
| ; CHECK-NEXT: [[VAR_TMP25:%.*]] = phi i32 [ [[VAR_TMP20]], %[[VAR_BB11]] ], [ [[TMP40]], %[[MIDDLE_BLOCK]] ] |
| ; CHECK-NEXT: [[VAR_TMP26:%.*]] = ashr i32 [[VAR_TMP24]], 16 |
| ; CHECK-NEXT: store i32 [[VAR_TMP26]], ptr @global, align 4 |
| ; CHECK-NEXT: br label %[[VAR_BB27]] |
| ; CHECK: [[VAR_BB27]]: |
| ; CHECK-NEXT: [[VAR_TMP28:%.*]] = phi i32 [ [[VAR_TMP26]], %[[VAR_BB22]] ], [ [[VAR_TMP8]], %[[VAR_BB7]] ] |
| ; CHECK-NEXT: [[VAR_TMP29:%.*]] = phi ptr [ [[VAR_TMP23]], %[[VAR_BB22]] ], [ [[VAR_TMP4]], %[[VAR_BB7]] ] |
| ; CHECK-NEXT: [[VAR_TMP30:%.*]] = phi i32 [ [[VAR_TMP25]], %[[VAR_BB22]] ], [ [[VAR_TMP5]], %[[VAR_BB7]] ] |
| ; CHECK-NEXT: [[VAR_TMP31:%.*]] = sext i32 [[VAR_TMP28]] to i64 |
| ; CHECK-NEXT: [[VAR_TMP32:%.*]] = getelementptr inbounds float, ptr [[VAR_TMP3]], i64 [[VAR_TMP31]] |
| ; CHECK-NEXT: [[VAR_TMP33:%.*]] = load float, ptr [[VAR_TMP32]], align 4 |
| ; CHECK-NEXT: [[VAR_TMP34:%.*]] = sitofp i32 [[VAR_TMP30]] to float |
| ; CHECK-NEXT: [[VAR_TMP35:%.*]] = load float, ptr @global.2, align 4 |
| ; CHECK-NEXT: [[VAR_TMP36:%.*]] = fmul float [[VAR_TMP35]], [[VAR_TMP34]] |
| ; CHECK-NEXT: [[VAR_TMP37:%.*]] = fadd float [[VAR_TMP33]], [[VAR_TMP36]] |
| ; CHECK-NEXT: store float [[VAR_TMP37]], ptr [[VAR_TMP29]], align 4 |
| ; CHECK-NEXT: ret void |
| ; |
| bb: |
| %tmp = load i32, ptr @global.1, align 4 |
| %tmp3 = getelementptr inbounds float, ptr %arg, i64 190 |
| %tmp4 = getelementptr inbounds float, ptr %arg1, i64 512 |
| %tmp5 = and i32 %tmp, 65535 |
| %tmp6 = icmp ugt i32 %arg2, 65536 |
| br i1 %tmp6, label %bb7, label %bb9 |
| |
| bb7: |
| %tmp8 = load i32, ptr @global, align 4 |
| br label %bb27 |
| |
| bb9: |
| %tmp10 = udiv i32 65536, %arg2 |
| br label %bb11 |
| |
| bb11: |
| %tmp12 = phi i32 [ %tmp20, %bb11 ], [ %tmp5, %bb9 ] |
| %tmp13 = phi ptr [ %tmp18, %bb11 ], [ %tmp4, %bb9 ] |
| %tmp14 = phi i32 [ %tmp16, %bb11 ], [ %tmp10, %bb9 ] |
| %tmp15 = phi i32 [ %tmp19, %bb11 ], [ %tmp, %bb9 ] |
| %tmp16 = add nsw i32 %tmp14, -1 |
| %tmp17 = sitofp i32 %tmp12 to float |
| store float %tmp17, ptr %tmp13, align 4 |
| %tmp18 = getelementptr inbounds float, ptr %tmp13, i64 1 |
| %tmp19 = add i32 %tmp15, %arg2 |
| %tmp20 = and i32 %tmp19, 65535 |
| %tmp21 = icmp eq i32 %tmp16, 0 |
| br i1 %tmp21, label %bb22, label %bb11 |
| |
| bb22: |
| %tmp23 = phi ptr [ %tmp18, %bb11 ] |
| %tmp24 = phi i32 [ %tmp19, %bb11 ] |
| %tmp25 = phi i32 [ %tmp20, %bb11 ] |
| %tmp26 = ashr i32 %tmp24, 16 |
| store i32 %tmp26, ptr @global, align 4 |
| br label %bb27 |
| |
| bb27: |
| %tmp28 = phi i32 [ %tmp26, %bb22 ], [ %tmp8, %bb7 ] |
| %tmp29 = phi ptr [ %tmp23, %bb22 ], [ %tmp4, %bb7 ] |
| %tmp30 = phi i32 [ %tmp25, %bb22 ], [ %tmp5, %bb7 ] |
| %tmp31 = sext i32 %tmp28 to i64 |
| %tmp32 = getelementptr inbounds float, ptr %tmp3, i64 %tmp31 |
| %tmp33 = load float, ptr %tmp32, align 4 |
| %tmp34 = sitofp i32 %tmp30 to float |
| %tmp35 = load float, ptr @global.2, align 4 |
| %tmp36 = fmul float %tmp35, %tmp34 |
| %tmp37 = fadd float %tmp33, %tmp36 |
| store float %tmp37, ptr %tmp29, align 4 |
| ret void |
| } |
