llvm/test/CodeGen/X86/PR71178-register-coalescer-crash.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=x86_64 -- | FileCheck %s

define i32 @h(i1 %arg, i32 %arg1) {
; CHECK-LABEL: h:
; CHECK:       # %bb.0: # %bb
; CHECK-NEXT:    movl $1, %eax
; CHECK-NEXT:    movabsq $9166129423, %rcx # imm = 0x22258090F
; CHECK-NEXT:    xorl %edx, %edx
; CHECK-NEXT:    jmp .LBB0_1
; CHECK-NEXT:    .p2align 4
; CHECK-NEXT:  .LBB0_9: # %bb18
; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT:    xorl %eax, %eax
; CHECK-NEXT:    testb $1, %dil
; CHECK-NEXT:    jne .LBB0_10
; CHECK-NEXT:  .LBB0_1: # %bb4
; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    testq %rdx, %rdx
; CHECK-NEXT:    jne .LBB0_2
; CHECK-NEXT:  # %bb.7: # %bb16
; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT:    testb $1, %dil
; CHECK-NEXT:    jne .LBB0_9
; CHECK-NEXT:  # %bb.8: # %bb17
; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT:    movq %rcx, %rdx
; CHECK-NEXT:    jmp .LBB0_9
; CHECK-NEXT:  .LBB0_2: # %bb9
; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT:    testb $1, %dil
; CHECK-NEXT:    testb $1, %dil
; CHECK-NEXT:    je .LBB0_4
; CHECK-NEXT:  # %bb.3: # %bb13
; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT:    xorl %eax, %eax
; CHECK-NEXT:  .LBB0_4: # %bb14
; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT:    cmpl $1, %esi
; CHECK-NEXT:    je .LBB0_1
; CHECK-NEXT:  # %bb.5: # %bb14
; CHECK-NEXT:    movl %eax, %r8d
; CHECK-NEXT:    testl %esi, %esi
; CHECK-NEXT:    movl %esi, %eax
; CHECK-NEXT:    jne .LBB0_6
; CHECK-NEXT:  .LBB0_10: # %bb22
; CHECK-NEXT:    retq
; CHECK-NEXT:  .LBB0_6: # %bb22.loopexit1
; CHECK-NEXT:    movl %r8d, %eax
; CHECK-NEXT:    retq
bb:
  br label %bb2

bb2:                                              ; preds = %bb14, %bb
  %i = phi i64 [ %i5, %bb14 ], [ 0, %bb ]
  %i3 = phi i32 [ %i15, %bb14 ], [ 1, %bb ]
  br label %bb4

bb4:                                              ; preds = %bb18, %bb2
  %i5 = phi i64 [ %i19, %bb18 ], [ %i, %bb2 ]
  %i6 = phi i64 [ %i20, %bb18 ], [ %i, %bb2 ]
  %i7 = phi i32 [ 0, %bb18 ], [ %i3, %bb2 ]
  %i8 = icmp eq i64 %i6, 0
  br i1 %i8, label %bb16, label %bb9

bb9:                                              ; preds = %bb4
  br i1 %arg, label %bb12, label %bb10

bb10:                                             ; preds = %bb9
  %i11 = sdiv i64 0, 0
  br label %bb12

bb12:                                             ; preds = %bb10, %bb9
  br i1 %arg, label %bb13, label %bb14

bb13:                                             ; preds = %bb12
  br label %bb14

bb14:                                             ; preds = %bb13, %bb12
  %i15 = phi i32 [ 0, %bb13 ], [ %i7, %bb12 ]
  switch i32 %arg1, label %bb22 [
    i32 0, label %bb21
    i32 1, label %bb2
  ]

bb16:                                             ; preds = %bb4
  br i1 %arg, label %bb18, label %bb17

bb17:                                             ; preds = %bb16
  br label %bb18

bb18:                                             ; preds = %bb17, %bb16
  %i19 = phi i64 [ 9166129423, %bb17 ], [ %i5, %bb16 ]
  %i20 = phi i64 [ 9166129423, %bb17 ], [ %i6, %bb16 ]
  br i1 %arg, label %bb22, label %bb4

bb21:                                             ; preds = %bb14
  br label %bb22

bb22:                                             ; preds = %bb21, %bb18, %bb14
  %i23 = phi i32 [ %arg1, %bb21 ], [ %i15, %bb14 ], [ 0, %bb18 ]
  ret i32 %i23
}