| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6 |
| ; RUN: opt -passes=loop-distribute,loop-vectorize -enable-loop-distribute -force-vector-width=4 -force-vector-interleave=1 -S \ |
| ; RUN: %s | FileCheck %s |
| |
| ; This test is to assure LoopAccessInfo invalidation after LoopVectorize |
| ; modifies the IR. |
| define void @reduced(ptr %0, ptr %1, i64 %iv, ptr %2, i64 %iv76, i64 %iv93) { |
| ; CHECK-LABEL: define void @reduced( |
| ; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]], i64 [[IV:%.*]], ptr [[TMP2:%.*]], i64 [[IV76:%.*]], i64 [[IV93:%.*]]) { |
| ; CHECK-NEXT: [[ENTRY:.*]]: |
| ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 3 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[TMP4]] |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[IND_ESCAPE:%.*]] = sub i64 [[N_VEC]], 1 |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label %[[LOOP_2_PREHEADER:.*]], label %[[SCALAR_PH]] |
| ; CHECK: [[SCALAR_PH]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-NEXT: br label %[[LOOP_1:.*]] |
| ; CHECK: [[LOOP_1]]: |
| ; CHECK-NEXT: [[IV761:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT77:%.*]], %[[LOOP_1]] ] |
| ; CHECK-NEXT: [[IV4:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_1]] ] |
| ; CHECK-NEXT: [[IV_NEXT77]] = add i64 [[IV761]], 1 |
| ; CHECK-NEXT: [[ARRAYIDX_I_I50:%.*]] = getelementptr i32, ptr [[TMP0]], i64 [[IV76]] |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV4]], 1 |
| ; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV4]], [[IV]] |
| ; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[LOOP_2_PREHEADER]], label %[[LOOP_1]], !llvm.loop [[LOOP3:![0-9]+]] |
| ; CHECK: [[LOOP_2_PREHEADER]]: |
| ; CHECK-NEXT: [[IV761_LCSSA:%.*]] = phi i64 [ [[IV761]], %[[LOOP_1]] ], [ [[IND_ESCAPE]], %[[MIDDLE_BLOCK]] ] |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK4:%.*]] = icmp ult i64 [[TMP3]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK4]], label %[[SCALAR_PH3:.*]], label %[[VECTOR_MEMCHECK:.*]] |
| ; CHECK: [[VECTOR_MEMCHECK]]: |
| ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[TMP1]], i64 4 |
| ; CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[IV761_LCSSA]], 2 |
| ; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[TMP0]], i64 [[TMP6]] |
| ; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 4 |
| ; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 [[TMP7]] |
| ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[TMP1]], [[SCEVGEP2]] |
| ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SCEVGEP1]], [[SCEVGEP]] |
| ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] |
| ; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH3]], label %[[VECTOR_PH5:.*]] |
| ; CHECK: [[VECTOR_PH5]]: |
| ; CHECK-NEXT: [[TMP8:%.*]] = and i64 [[TMP3]], 3 |
| ; CHECK-NEXT: [[N_VEC6:%.*]] = sub i64 [[TMP3]], [[TMP8]] |
| ; CHECK-NEXT: br label %[[VECTOR_BODY7:.*]] |
| ; CHECK: [[VECTOR_BODY7]]: |
| ; CHECK-NEXT: [[INDEX8:%.*]] = phi i64 [ 0, %[[VECTOR_PH5]] ], [ [[INDEX_NEXT9:%.*]], %[[VECTOR_BODY7]] ] |
| ; CHECK-NEXT: [[INDEX_NEXT9]] = add nuw i64 [[INDEX8]], 4 |
| ; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT9]], [[N_VEC6]] |
| ; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK10:.*]], label %[[VECTOR_BODY7]], !llvm.loop [[LOOP4:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK10]]: |
| ; CHECK-NEXT: store i32 0, ptr [[TMP1]], align 4, !alias.scope [[META5:![0-9]+]], !noalias [[META8:![0-9]+]] |
| ; CHECK-NEXT: [[CMP_N11:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC6]] |
| ; CHECK-NEXT: br i1 [[CMP_N11]], label %[[LOOP_3_LR_PH:.*]], label %[[SCALAR_PH3]] |
| ; CHECK: [[SCALAR_PH3]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL12:%.*]] = phi i64 [ [[N_VEC6]], %[[MIDDLE_BLOCK10]] ], [ 0, %[[LOOP_2_PREHEADER]] ], [ 0, %[[VECTOR_MEMCHECK]] ] |
| ; CHECK-NEXT: br label %[[LOOP_2:.*]] |
| ; CHECK: [[LOOP_3_LR_PH]]: |
| ; CHECK-NEXT: [[IDXPROM_I_I61:%.*]] = and i64 [[IV761_LCSSA]], 1 |
| ; CHECK-NEXT: [[ARRAYIDX_I_I62:%.*]] = getelementptr i32, ptr [[TMP0]], i64 [[IDXPROM_I_I61]] |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK20:%.*]] = icmp ult i64 [[TMP3]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK20]], label %[[SCALAR_PH18:.*]], label %[[VECTOR_MEMCHECK20:.*]] |
| ; CHECK: [[VECTOR_MEMCHECK20]]: |
| ; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr i8, ptr [[TMP1]], i64 4 |
| ; CHECK-NEXT: [[TMP10:%.*]] = shl nuw nsw i64 [[IDXPROM_I_I61]], 2 |
| ; CHECK-NEXT: [[TMP11:%.*]] = add nuw nsw i64 [[TMP10]], 4 |
| ; CHECK-NEXT: [[SCEVGEP15:%.*]] = getelementptr i8, ptr [[TMP0]], i64 [[TMP11]] |
| ; CHECK-NEXT: [[BOUND016:%.*]] = icmp ult ptr [[TMP1]], [[SCEVGEP15]] |
| ; CHECK-NEXT: [[BOUND117:%.*]] = icmp ult ptr [[ARRAYIDX_I_I62]], [[SCEVGEP14]] |
| ; CHECK-NEXT: [[FOUND_CONFLICT18:%.*]] = and i1 [[BOUND016]], [[BOUND117]] |
| ; CHECK-NEXT: br i1 [[FOUND_CONFLICT18]], label %[[SCALAR_PH18]], label %[[VECTOR_PH24:.*]] |
| ; CHECK: [[VECTOR_PH24]]: |
| ; CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP3]], 3 |
| ; CHECK-NEXT: [[N_VEC25:%.*]] = sub i64 [[TMP3]], [[TMP17]] |
| ; CHECK-NEXT: br label %[[VECTOR_BODY26:.*]] |
| ; CHECK: [[VECTOR_BODY26]]: |
| ; CHECK-NEXT: [[INDEX27:%.*]] = phi i64 [ 0, %[[VECTOR_PH24]] ], [ [[INDEX_NEXT28:%.*]], %[[VECTOR_BODY26]] ] |
| ; CHECK-NEXT: [[INDEX_NEXT28]] = add nuw i64 [[INDEX27]], 4 |
| ; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT28]], [[N_VEC25]] |
| ; CHECK-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK29:.*]], label %[[VECTOR_BODY26]], !llvm.loop [[LOOP10:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK29]]: |
| ; CHECK-NEXT: store i32 0, ptr [[TMP1]], align 4, !alias.scope [[META11:![0-9]+]], !noalias [[META14:![0-9]+]] |
| ; CHECK-NEXT: [[CMP_N30:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC25]] |
| ; CHECK-NEXT: br i1 [[CMP_N30]], label %[[LOOP_CLEANUP:.*]], label %[[SCALAR_PH18]] |
| ; CHECK: [[SCALAR_PH18]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL31:%.*]] = phi i64 [ [[N_VEC25]], %[[MIDDLE_BLOCK29]] ], [ 0, %[[LOOP_3_LR_PH]] ], [ 0, %[[VECTOR_MEMCHECK20]] ] |
| ; CHECK-NEXT: br label %[[LOOP_3:.*]] |
| ; CHECK: [[LOOP_2]]: |
| ; CHECK-NEXT: [[IV846:%.*]] = phi i64 [ [[IV_NEXT85:%.*]], %[[LOOP_2]] ], [ [[BC_RESUME_VAL12]], %[[SCALAR_PH3]] ] |
| ; CHECK-NEXT: [[IV_NEXT87:%.*]] = add i64 0, 0 |
| ; CHECK-NEXT: [[ARRAYIDX_I_I56:%.*]] = getelementptr i32, ptr [[TMP0]], i64 [[IV761_LCSSA]] |
| ; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX_I_I56]], align 4 |
| ; CHECK-NEXT: store i32 0, ptr [[TMP1]], align 4 |
| ; CHECK-NEXT: [[IV_NEXT85]] = add i64 [[IV846]], 1 |
| ; CHECK-NEXT: [[EXITCOND92_NOT:%.*]] = icmp eq i64 [[IV846]], [[IV]] |
| ; CHECK-NEXT: br i1 [[EXITCOND92_NOT]], label %[[LOOP_3_LR_PH]], label %[[LOOP_2]], !llvm.loop [[LOOP16:![0-9]+]] |
| ; CHECK: [[LOOP_3]]: |
| ; CHECK-NEXT: [[IV932:%.*]] = phi i64 [ [[BC_RESUME_VAL31]], %[[SCALAR_PH18]] ], [ [[IV_NEXT94:%.*]], %[[LOOP_3]] ] |
| ; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX_I_I62]], align 4 |
| ; CHECK-NEXT: [[ARRAYIDX_I_I653:%.*]] = getelementptr i32, ptr [[TMP2]], i64 [[IV93]] |
| ; CHECK-NEXT: store i32 0, ptr [[TMP1]], align 4 |
| ; CHECK-NEXT: [[IV_NEXT94]] = add i64 [[IV932]], 1 |
| ; CHECK-NEXT: [[EXITCOND97_NOT:%.*]] = icmp eq i64 [[IV932]], [[IV]] |
| ; CHECK-NEXT: br i1 [[EXITCOND97_NOT]], label %[[LOOP_CLEANUP]], label %[[LOOP_3]], !llvm.loop [[LOOP17:![0-9]+]] |
| ; CHECK: [[LOOP_CLEANUP]]: |
| ; CHECK-NEXT: ret void |
| ; |
| entry: |
| br label %loop.1 |
| |
| loop.1: |
| %iv761 = phi i64 [ 0, %entry ], [ %iv.next77, %loop.1 ] |
| %iv4 = phi i64 [ 0, %entry ], [ %iv.next, %loop.1 ] |
| %iv.next77 = add i64 %iv761, 1 |
| %arrayidx.i.i50 = getelementptr i32, ptr %0, i64 %iv76 |
| %iv.next = add i64 %iv4, 1 |
| %exitcond.not = icmp eq i64 %iv4, %iv |
| br i1 %exitcond.not, label %loop.2.preheader, label %loop.1 |
| |
| loop.2.preheader: |
| br label %loop.2 |
| |
| loop.3.lr.ph: |
| %idxprom.i.i61 = and i64 %iv761, 1 |
| %arrayidx.i.i62 = getelementptr i32, ptr %0, i64 %idxprom.i.i61 |
| br label %loop.3 |
| |
| loop.2: |
| %iv846 = phi i64 [ %iv.next85, %loop.2 ], [ 0, %loop.2.preheader ] |
| %iv.next87 = add i64 0, 0 |
| %arrayidx.i.i56 = getelementptr i32, ptr %0, i64 %iv761 |
| %3 = load i32, ptr %arrayidx.i.i56, align 4 |
| store i32 0, ptr %1, align 4 |
| %iv.next85 = add i64 %iv846, 1 |
| %exitcond92.not = icmp eq i64 %iv846, %iv |
| br i1 %exitcond92.not, label %loop.3.lr.ph, label %loop.2 |
| |
| loop.3: |
| %iv932 = phi i64 [ 0, %loop.3.lr.ph ], [ %iv.next94, %loop.3 ] |
| %4 = load i32, ptr %arrayidx.i.i62, align 4 |
| %arrayidx.i.i653 = getelementptr i32, ptr %2, i64 %iv93 |
| store i32 0, ptr %1, align 4 |
| %iv.next94 = add i64 %iv932, 1 |
| %exitcond97.not = icmp eq i64 %iv932, %iv |
| br i1 %exitcond97.not, label %loop.cleanup, label %loop.3 |
| |
| loop.cleanup: |
| ret void |
| } |
