llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -mtriple=amdgpu12.50 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1250
; RUN: opt -mtriple=amdgpu12.00 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1200
; RUN: opt -mtriple=amdgpu11.00 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1100

define amdgpu_kernel void @prefetch_two_streams_80B(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b, i64 %n) {
; GFX1250-LABEL: define amdgpu_kernel void @prefetch_two_streams_80B(
; GFX1250-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
; GFX1250-NEXT:  [[ENTRY:.*]]:
; GFX1250-NEXT:    br label %[[FOR_BODY:.*]]
; GFX1250:       [[FOR_BODY]]:
; GFX1250-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
; GFX1250-NEXT:    [[TMP0:%.*]] = shl i64 [[IV]], 2
; GFX1250-NEXT:    [[TMP1:%.*]] = add i64 [[TMP0]], 28
; GFX1250-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
; GFX1250-NEXT:    [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
; GFX1250-NEXT:    call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
; GFX1250-NEXT:    [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
; GFX1250-NEXT:    [[IV_OFF:%.*]] = add i64 [[IV]], 20
; GFX1250-NEXT:    [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
; GFX1250-NEXT:    [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
; GFX1250-NEXT:    [[SUM:%.*]] = add i32 [[V0]], [[V1]]
; GFX1250-NEXT:    [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
; GFX1250-NEXT:    store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
; GFX1250-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; GFX1250-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; GFX1250-NEXT:    br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
; GFX1250:       [[FOR_END]]:
; GFX1250-NEXT:    ret void
;
; GFX1200-LABEL: define amdgpu_kernel void @prefetch_two_streams_80B(
; GFX1200-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
; GFX1200-NEXT:  [[ENTRY:.*]]:
; GFX1200-NEXT:    br label %[[FOR_BODY:.*]]
; GFX1200:       [[FOR_BODY]]:
; GFX1200-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
; GFX1200-NEXT:    [[TMP0:%.*]] = shl i64 [[IV]], 2
; GFX1200-NEXT:    [[TMP1:%.*]] = add i64 [[TMP0]], 28
; GFX1200-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
; GFX1200-NEXT:    [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
; GFX1200-NEXT:    call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
; GFX1200-NEXT:    [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
; GFX1200-NEXT:    [[IV_OFF:%.*]] = add i64 [[IV]], 20
; GFX1200-NEXT:    [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
; GFX1200-NEXT:    [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
; GFX1200-NEXT:    [[SUM:%.*]] = add i32 [[V0]], [[V1]]
; GFX1200-NEXT:    [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
; GFX1200-NEXT:    store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
; GFX1200-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; GFX1200-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; GFX1200-NEXT:    br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
; GFX1200:       [[FOR_END]]:
; GFX1200-NEXT:    ret void
;
; GFX1100-LABEL: define amdgpu_kernel void @prefetch_two_streams_80B(
; GFX1100-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
; GFX1100-NEXT:  [[ENTRY:.*]]:
; GFX1100-NEXT:    br label %[[FOR_BODY:.*]]
; GFX1100:       [[FOR_BODY]]:
; GFX1100-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
; GFX1100-NEXT:    [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
; GFX1100-NEXT:    [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
; GFX1100-NEXT:    [[IV_OFF:%.*]] = add i64 [[IV]], 20
; GFX1100-NEXT:    [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
; GFX1100-NEXT:    [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
; GFX1100-NEXT:    [[SUM:%.*]] = add i32 [[V0]], [[V1]]
; GFX1100-NEXT:    [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
; GFX1100-NEXT:    store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
; GFX1100-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; GFX1100-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; GFX1100-NEXT:    br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
; GFX1100:       [[FOR_END]]:
; GFX1100-NEXT:    ret void
;
entry:
  br label %for.body

for.body:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
  %idx0 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 %iv
  %v0 = load i32, ptr addrspace(1) %idx0, align 4
  %iv.off = add i64 %iv, 20
  %idx1 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 %iv.off
  %v1 = load i32, ptr addrspace(1) %idx1, align 4
  %sum = add i32 %v0, %v1
  %sidx = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %iv
  store i32 %sum, ptr addrspace(1) %sidx, align 4
  %iv.next = add nuw nsw i64 %iv, 1
  %ec = icmp eq i64 %iv.next, %n
  br i1 %ec, label %for.end, label %for.body

for.end:
  ret void
}

define amdgpu_kernel void @prefetch_two_streams_160B(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b, i64 %n) {
; GFX1250-LABEL: define amdgpu_kernel void @prefetch_two_streams_160B(
; GFX1250-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
; GFX1250-NEXT:  [[ENTRY:.*]]:
; GFX1250-NEXT:    br label %[[FOR_BODY:.*]]
; GFX1250:       [[FOR_BODY]]:
; GFX1250-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
; GFX1250-NEXT:    [[TMP0:%.*]] = shl i64 [[IV]], 2
; GFX1250-NEXT:    [[TMP1:%.*]] = add i64 [[TMP0]], 188
; GFX1250-NEXT:    [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
; GFX1250-NEXT:    [[TMP2:%.*]] = shl i64 [[IV]], 2
; GFX1250-NEXT:    [[TMP3:%.*]] = add i64 [[TMP2]], 28
; GFX1250-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP3]]
; GFX1250-NEXT:    [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
; GFX1250-NEXT:    call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
; GFX1250-NEXT:    [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
; GFX1250-NEXT:    [[IV_OFF:%.*]] = add i64 [[IV]], 40
; GFX1250-NEXT:    [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
; GFX1250-NEXT:    call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP1]], i32 0, i32 3, i32 1)
; GFX1250-NEXT:    [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
; GFX1250-NEXT:    [[SUM:%.*]] = add i32 [[V0]], [[V1]]
; GFX1250-NEXT:    [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
; GFX1250-NEXT:    store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
; GFX1250-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; GFX1250-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; GFX1250-NEXT:    br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
; GFX1250:       [[FOR_END]]:
; GFX1250-NEXT:    ret void
;
; GFX1200-LABEL: define amdgpu_kernel void @prefetch_two_streams_160B(
; GFX1200-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
; GFX1200-NEXT:  [[ENTRY:.*]]:
; GFX1200-NEXT:    br label %[[FOR_BODY:.*]]
; GFX1200:       [[FOR_BODY]]:
; GFX1200-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
; GFX1200-NEXT:    [[TMP0:%.*]] = shl i64 [[IV]], 2
; GFX1200-NEXT:    [[TMP1:%.*]] = add i64 [[TMP0]], 188
; GFX1200-NEXT:    [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
; GFX1200-NEXT:    [[TMP2:%.*]] = shl i64 [[IV]], 2
; GFX1200-NEXT:    [[TMP3:%.*]] = add i64 [[TMP2]], 28
; GFX1200-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP3]]
; GFX1200-NEXT:    [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
; GFX1200-NEXT:    call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
; GFX1200-NEXT:    [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
; GFX1200-NEXT:    [[IV_OFF:%.*]] = add i64 [[IV]], 40
; GFX1200-NEXT:    [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
; GFX1200-NEXT:    call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP1]], i32 0, i32 3, i32 1)
; GFX1200-NEXT:    [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
; GFX1200-NEXT:    [[SUM:%.*]] = add i32 [[V0]], [[V1]]
; GFX1200-NEXT:    [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
; GFX1200-NEXT:    store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
; GFX1200-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; GFX1200-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; GFX1200-NEXT:    br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
; GFX1200:       [[FOR_END]]:
; GFX1200-NEXT:    ret void
;
; GFX1100-LABEL: define amdgpu_kernel void @prefetch_two_streams_160B(
; GFX1100-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
; GFX1100-NEXT:  [[ENTRY:.*]]:
; GFX1100-NEXT:    br label %[[FOR_BODY:.*]]
; GFX1100:       [[FOR_BODY]]:
; GFX1100-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
; GFX1100-NEXT:    [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
; GFX1100-NEXT:    [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
; GFX1100-NEXT:    [[IV_OFF:%.*]] = add i64 [[IV]], 40
; GFX1100-NEXT:    [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
; GFX1100-NEXT:    [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
; GFX1100-NEXT:    [[SUM:%.*]] = add i32 [[V0]], [[V1]]
; GFX1100-NEXT:    [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
; GFX1100-NEXT:    store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
; GFX1100-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; GFX1100-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; GFX1100-NEXT:    br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
; GFX1100:       [[FOR_END]]:
; GFX1100-NEXT:    ret void
;
entry:
  br label %for.body

for.body:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
  %idx0 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 %iv
  %v0 = load i32, ptr addrspace(1) %idx0, align 4
  %iv.off = add i64 %iv, 40
  %idx1 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 %iv.off
  %v1 = load i32, ptr addrspace(1) %idx1, align 4
  %sum = add i32 %v0, %v1
  %sidx = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %iv
  store i32 %sum, ptr addrspace(1) %sidx, align 4
  %iv.next = add nuw nsw i64 %iv, 1
  %ec = icmp eq i64 %iv.next, %n
  br i1 %ec, label %for.end, label %for.body

for.end:
  ret void
}

define amdgpu_kernel void @prefetch_two_streams_320B(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b, i64 %n) {
; GFX1250-LABEL: define amdgpu_kernel void @prefetch_two_streams_320B(
; GFX1250-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
; GFX1250-NEXT:  [[ENTRY:.*]]:
; GFX1250-NEXT:    br label %[[FOR_BODY:.*]]
; GFX1250:       [[FOR_BODY]]:
; GFX1250-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
; GFX1250-NEXT:    [[TMP0:%.*]] = shl i64 [[IV]], 2
; GFX1250-NEXT:    [[TMP1:%.*]] = add i64 [[TMP0]], 348
; GFX1250-NEXT:    [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
; GFX1250-NEXT:    [[TMP2:%.*]] = shl i64 [[IV]], 2
; GFX1250-NEXT:    [[TMP3:%.*]] = add i64 [[TMP2]], 28
; GFX1250-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP3]]
; GFX1250-NEXT:    [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
; GFX1250-NEXT:    call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
; GFX1250-NEXT:    [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
; GFX1250-NEXT:    [[IV_OFF:%.*]] = add i64 [[IV]], 80
; GFX1250-NEXT:    [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
; GFX1250-NEXT:    call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP1]], i32 0, i32 3, i32 1)
; GFX1250-NEXT:    [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
; GFX1250-NEXT:    [[SUM:%.*]] = add i32 [[V0]], [[V1]]
; GFX1250-NEXT:    [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
; GFX1250-NEXT:    store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
; GFX1250-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; GFX1250-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; GFX1250-NEXT:    br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
; GFX1250:       [[FOR_END]]:
; GFX1250-NEXT:    ret void
;
; GFX1200-LABEL: define amdgpu_kernel void @prefetch_two_streams_320B(
; GFX1200-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
; GFX1200-NEXT:  [[ENTRY:.*]]:
; GFX1200-NEXT:    br label %[[FOR_BODY:.*]]
; GFX1200:       [[FOR_BODY]]:
; GFX1200-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
; GFX1200-NEXT:    [[TMP0:%.*]] = shl i64 [[IV]], 2
; GFX1200-NEXT:    [[TMP1:%.*]] = add i64 [[TMP0]], 348
; GFX1200-NEXT:    [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
; GFX1200-NEXT:    [[TMP2:%.*]] = shl i64 [[IV]], 2
; GFX1200-NEXT:    [[TMP3:%.*]] = add i64 [[TMP2]], 28
; GFX1200-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP3]]
; GFX1200-NEXT:    [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
; GFX1200-NEXT:    call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
; GFX1200-NEXT:    [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
; GFX1200-NEXT:    [[IV_OFF:%.*]] = add i64 [[IV]], 80
; GFX1200-NEXT:    [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
; GFX1200-NEXT:    call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP1]], i32 0, i32 3, i32 1)
; GFX1200-NEXT:    [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
; GFX1200-NEXT:    [[SUM:%.*]] = add i32 [[V0]], [[V1]]
; GFX1200-NEXT:    [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
; GFX1200-NEXT:    store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
; GFX1200-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; GFX1200-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; GFX1200-NEXT:    br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
; GFX1200:       [[FOR_END]]:
; GFX1200-NEXT:    ret void
;
; GFX1100-LABEL: define amdgpu_kernel void @prefetch_two_streams_320B(
; GFX1100-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
; GFX1100-NEXT:  [[ENTRY:.*]]:
; GFX1100-NEXT:    br label %[[FOR_BODY:.*]]
; GFX1100:       [[FOR_BODY]]:
; GFX1100-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
; GFX1100-NEXT:    [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
; GFX1100-NEXT:    [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
; GFX1100-NEXT:    [[IV_OFF:%.*]] = add i64 [[IV]], 80
; GFX1100-NEXT:    [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
; GFX1100-NEXT:    [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
; GFX1100-NEXT:    [[SUM:%.*]] = add i32 [[V0]], [[V1]]
; GFX1100-NEXT:    [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
; GFX1100-NEXT:    store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
; GFX1100-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; GFX1100-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; GFX1100-NEXT:    br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
; GFX1100:       [[FOR_END]]:
; GFX1100-NEXT:    ret void
;
entry:
  br label %for.body

for.body:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
  %idx0 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 %iv
  %v0 = load i32, ptr addrspace(1) %idx0, align 4
  %iv.off = add i64 %iv, 80
  %idx1 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 %iv.off
  %v1 = load i32, ptr addrspace(1) %idx1, align 4
  %sum = add i32 %v0, %v1
  %sidx = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %iv
  store i32 %sum, ptr addrspace(1) %sidx, align 4
  %iv.next = add nuw nsw i64 %iv, 1
  %ec = icmp eq i64 %iv.next, %n
  br i1 %ec, label %for.end, label %for.body

for.end:
  ret void
}