| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=riscv64 -mattr=experimental-zbr -verify-machineinstrs < %s \ |
| ; RUN: | FileCheck %s -check-prefix=RV64ZBR |
| |
| declare i64 @llvm.riscv.crc32.b.i64(i64) |
| |
| define i64 @crc32b(i64 %a) nounwind { |
| ; RV64ZBR-LABEL: crc32b: |
| ; RV64ZBR: # %bb.0: |
| ; RV64ZBR-NEXT: crc32.b a0, a0 |
| ; RV64ZBR-NEXT: ret |
| %tmp = call i64 @llvm.riscv.crc32.b.i64(i64 %a) |
| ret i64 %tmp |
| } |
| |
| declare i64 @llvm.riscv.crc32.h.i64(i64) |
| |
| define i64 @crc32h(i64 %a) nounwind { |
| ; RV64ZBR-LABEL: crc32h: |
| ; RV64ZBR: # %bb.0: |
| ; RV64ZBR-NEXT: crc32.h a0, a0 |
| ; RV64ZBR-NEXT: ret |
| %tmp = call i64 @llvm.riscv.crc32.h.i64(i64 %a) |
| ret i64 %tmp |
| } |
| |
| declare i64 @llvm.riscv.crc32.w.i64(i64) |
| |
| define i64 @crc32w(i64 %a) nounwind { |
| ; RV64ZBR-LABEL: crc32w: |
| ; RV64ZBR: # %bb.0: |
| ; RV64ZBR-NEXT: crc32.w a0, a0 |
| ; RV64ZBR-NEXT: ret |
| %tmp = call i64 @llvm.riscv.crc32.w.i64(i64 %a) |
| ret i64 %tmp |
| } |
| |
| declare i64 @llvm.riscv.crc32c.b.i64(i64) |
| |
| define i64 @crc32cb(i64 %a) nounwind { |
| ; RV64ZBR-LABEL: crc32cb: |
| ; RV64ZBR: # %bb.0: |
| ; RV64ZBR-NEXT: crc32c.b a0, a0 |
| ; RV64ZBR-NEXT: ret |
| %tmp = call i64 @llvm.riscv.crc32c.b.i64(i64 %a) |
| ret i64 %tmp |
| } |
| |
| declare i64 @llvm.riscv.crc32c.h.i64(i64) |
| |
| define i64 @crc32ch(i64 %a) nounwind { |
| ; RV64ZBR-LABEL: crc32ch: |
| ; RV64ZBR: # %bb.0: |
| ; RV64ZBR-NEXT: crc32c.h a0, a0 |
| ; RV64ZBR-NEXT: ret |
| %tmp = call i64 @llvm.riscv.crc32c.h.i64(i64 %a) |
| ret i64 %tmp |
| } |
| |
| declare i64 @llvm.riscv.crc32c.w.i64(i64) |
| |
| define i64 @crc32cw(i64 %a) nounwind { |
| ; RV64ZBR-LABEL: crc32cw: |
| ; RV64ZBR: # %bb.0: |
| ; RV64ZBR-NEXT: crc32c.w a0, a0 |
| ; RV64ZBR-NEXT: ret |
| %tmp = call i64 @llvm.riscv.crc32c.w.i64(i64 %a) |
| ret i64 %tmp |
| } |
| |
| declare i64 @llvm.riscv.crc32.d.i64(i64) |
| |
| define i64 @crc32d(i64 %a) nounwind { |
| ; RV64ZBR-LABEL: crc32d: |
| ; RV64ZBR: # %bb.0: |
| ; RV64ZBR-NEXT: crc32.d a0, a0 |
| ; RV64ZBR-NEXT: ret |
| %tmp = call i64 @llvm.riscv.crc32.d.i64(i64 %a) |
| ret i64 %tmp |
| } |
| |
| declare i64 @llvm.riscv.crc32c.d.i64(i64) |
| |
| define i64 @crc32cd(i64 %a) nounwind { |
| ; RV64ZBR-LABEL: crc32cd: |
| ; RV64ZBR: # %bb.0: |
| ; RV64ZBR-NEXT: crc32c.d a0, a0 |
| ; RV64ZBR-NEXT: ret |
| %tmp = call i64 @llvm.riscv.crc32c.d.i64(i64 %a) |
| ret i64 %tmp |
| } |