| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \ |
| ; RUN: | FileCheck %s -check-prefix=RV64ZBB |
| |
| declare i32 @llvm.riscv.orc.b.i32(i32) |
| |
| define signext i32 @orcb32(i32 signext %a) nounwind { |
| ; RV64ZBB-LABEL: orcb32: |
| ; RV64ZBB: # %bb.0: |
| ; RV64ZBB-NEXT: orc.b a0, a0 |
| ; RV64ZBB-NEXT: sext.w a0, a0 |
| ; RV64ZBB-NEXT: ret |
| %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a) |
| ret i32 %tmp |
| } |
| |
| declare i64 @llvm.riscv.orc.b.i64(i64) |
| |
| define i64 @orcb64(i64 %a) nounwind { |
| ; RV64ZBB-LABEL: orcb64: |
| ; RV64ZBB: # %bb.0: |
| ; RV64ZBB-NEXT: orc.b a0, a0 |
| ; RV64ZBB-NEXT: ret |
| %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a) |
| ret i64 %tmp |
| } |