llvm/test/Transforms/SLPVectorizer/AMDGPU/transform-node-gather-struct.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S --passes=slp-vectorizer -mtriple=amdgpu-amd-amdhsa < %s | FileCheck %s

define void @test() {
; CHECK-LABEL: define void @test() {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    br label %[[LAND_RHS_I_I_I1756:.*]]
; CHECK:       [[LAND_RHS_I_I_I1756]]:
; CHECK-NEXT:    [[VALUE_SROA_8_026_I_I_I1760:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[TMP4:%.*]], %[[LAND_RHS_I_I_I1756]] ]
; CHECK-NEXT:    [[VALUE_SROA_12_025_I_I_I1761:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[TMP3:%.*]], %[[LAND_RHS_I_I_I1756]] ]
; CHECK-NEXT:    [[SHR_1_I_I_I_I1784:%.*]] = lshr i32 [[VALUE_SROA_8_026_I_I_I1760]], 0
; CHECK-NEXT:    [[ADD3_1_I_I_I_I1799:%.*]] = or i32 0, [[SHR_1_I_I_I_I1784]]
; CHECK-NEXT:    [[SHR_2_I_I_I_I1786:%.*]] = lshr i32 [[VALUE_SROA_12_025_I_I_I1761]], 0
; CHECK-NEXT:    [[ADD3_2_I_I_I_I1801:%.*]] = or i32 [[ADD3_1_I_I_I_I1799]], [[SHR_2_I_I_I_I1786]]
; CHECK-NEXT:    [[SHR_5_I_I_I_I1792:%.*]] = lshr i32 0, 0
; CHECK-NEXT:    [[ADD3_5_I_I_I_I1807:%.*]] = or i32 [[ADD3_2_I_I_I_I1801]], [[SHR_5_I_I_I_I1792]]
; CHECK-NEXT:    [[CMP4_I_I_I_I_I1815:%.*]] = icmp eq i32 [[ADD3_5_I_I_I_I1807]], 0
; CHECK-NEXT:    [[TMP0:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 0, i32 0)
; CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { i32, i1 } [[TMP0]], 1
; CHECK-NEXT:    [[OR_I40_2_I_I_I_I1917:%.*]] = zext i1 [[TMP1]] to i32
; CHECK-NEXT:    [[TMP2:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 0, i32 [[OR_I40_2_I_I_I_I1917]])
; CHECK-NEXT:    [[TMP3]] = extractvalue { i32, i1 } [[TMP2]], 0
; CHECK-NEXT:    [[TMP4]] = extractvalue { i32, i1 } [[TMP0]], 0
; CHECK-NEXT:    br label %[[LAND_RHS_I_I_I1756]]
;
entry:
  br label %land.rhs.i.i.i1756

land.rhs.i.i.i1756:
  %value.sroa.8.026.i.i.i1760 = phi i32 [ 0, %entry ], [ %4, %land.rhs.i.i.i1756 ]
  %value.sroa.12.025.i.i.i1761 = phi i32 [ 0, %entry ], [ %3, %land.rhs.i.i.i1756 ]
  %shr.1.i.i.i.i1784 = lshr i32 %value.sroa.8.026.i.i.i1760, 0
  %add3.1.i.i.i.i1799 = or i32 0, %shr.1.i.i.i.i1784
  %shr.2.i.i.i.i1786 = lshr i32 %value.sroa.12.025.i.i.i1761, 0
  %add3.2.i.i.i.i1801 = or i32 %add3.1.i.i.i.i1799, %shr.2.i.i.i.i1786
  %shr.5.i.i.i.i1792 = lshr i32 0, 0
  %add3.5.i.i.i.i1807 = or i32 %add3.2.i.i.i.i1801, %shr.5.i.i.i.i1792
  %cmp4.i.i.i.i.i1815 = icmp eq i32 %add3.5.i.i.i.i1807, 0
  %0 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 0, i32 0)
  %1 = extractvalue { i32, i1 } %0, 1
  %or.i40.2.i.i.i.i1917 = zext i1 %1 to i32
  %2 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 0, i32 %or.i40.2.i.i.i.i1917)
  %3 = extractvalue { i32, i1 } %2, 0
  %4 = extractvalue { i32, i1 } %0, 0
  br label %land.rhs.i.i.i1756
}

declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)