llvm/test/Transforms/LoopVectorize/scev-exit-phi-invalidation.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt  -passes='loop(loop-deletion),loop-vectorize' -force-vector-width=4  -force-vector-interleave=1 -S %s | FileCheck %s

; Note: loop-deletion is needed to populate SCEV block dispositions.

target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"

define void @test_pr63368(i1 %c, ptr %A) {
; CHECK-LABEL: define void @test_pr63368(
; CHECK-SAME: i1 [[C:%.*]], ptr [[A:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]
; CHECK:       [[VECTOR_PH]]:
; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK:       [[VECTOR_BODY]]:
; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100
; CHECK-NEXT:    br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK:       [[MIDDLE_BLOCK]]:
; CHECK-NEXT:    br label %[[EXIT_1:.*]]
; CHECK:       [[EXIT_1]]:
; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP0]], i32 -1)
; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[TMP2]], 2
; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP3]], 4
; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK:       [[VECTOR_SCEVCHECK]]:
; CHECK-NEXT:    [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP0]], i32 -1)
; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[SMAX]], 1
; CHECK-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
; CHECK-NEXT:    [[TMP6:%.*]] = add i8 1, [[TMP5]]
; CHECK-NEXT:    [[TMP7:%.*]] = icmp slt i8 [[TMP6]], 1
; CHECK-NEXT:    [[TMP8:%.*]] = icmp ugt i32 [[TMP4]], 255
; CHECK-NEXT:    [[TMP9:%.*]] = or i1 [[TMP7]], [[TMP8]]
; CHECK-NEXT:    br i1 [[TMP9]], label %[[SCALAR_PH]], label %[[VECTOR_PH1:.*]]
; CHECK:       [[VECTOR_PH1]]:
; CHECK-NEXT:    [[N_MOD_VF:%.*]] = and i32 [[TMP3]], 3
; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[TMP3]], [[N_MOD_VF]]
; CHECK-NEXT:    [[TMP10:%.*]] = trunc i32 [[N_VEC]] to i8
; CHECK-NEXT:    br label %[[VECTOR_BODY2:.*]]
; CHECK:       [[VECTOR_BODY2]]:
; CHECK-NEXT:    [[INDEX3:%.*]] = phi i32 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT4:%.*]], %[[VECTOR_BODY2]] ]
; CHECK-NEXT:    [[TMP11:%.*]] = trunc i32 [[INDEX3]] to i8
; CHECK-NEXT:    [[TMP12:%.*]] = add i8 [[TMP11]], 1
; CHECK-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[A]], i8 [[TMP12]]
; CHECK-NEXT:    store <4 x i8> zeroinitializer, ptr [[TMP13]], align 1
; CHECK-NEXT:    [[INDEX_NEXT4]] = add nuw i32 [[INDEX3]], 4
; CHECK-NEXT:    [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT4]], [[N_VEC]]
; CHECK-NEXT:    br i1 [[TMP14]], label %[[MIDDLE_BLOCK5:.*]], label %[[VECTOR_BODY2]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK:       [[MIDDLE_BLOCK5]]:
; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[TMP3]], [[N_VEC]]
; CHECK-NEXT:    br i1 [[CMP_N]], label %[[EXIT_2:.*]], label %[[SCALAR_PH]]
; CHECK:       [[SCALAR_PH]]:
; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i8 [ [[TMP10]], %[[MIDDLE_BLOCK5]] ], [ 0, %[[EXIT_1]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
; CHECK-NEXT:    br label %[[LOOP_2:.*]]
; CHECK:       [[LOOP_2]]:
; CHECK-NEXT:    [[IV_2:%.*]] = phi i8 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP_2]] ]
; CHECK-NEXT:    [[IV_2_NEXT]] = add i8 [[IV_2]], 1
; CHECK-NEXT:    [[GEP_A:%.*]] = getelementptr i8, ptr [[A]], i8 [[IV_2_NEXT]]
; CHECK-NEXT:    store i8 0, ptr [[GEP_A]], align 1
; CHECK-NEXT:    [[IV_2_SEXT:%.*]] = sext i8 [[IV_2]] to i32
; CHECK-NEXT:    [[EC_2:%.*]] = icmp sge i32 [[TMP0]], [[IV_2_SEXT]]
; CHECK-NEXT:    br i1 [[EC_2]], label %[[LOOP_2]], label %[[EXIT_2]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK:       [[EXIT_2]]:
; CHECK-NEXT:    ret void
;

entry:
  br label %loop.1.header

loop.1.header:
  %iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop.1.latch ]
  %l = load i32, ptr %A
  br i1 %c, label %loop.1.latch, label %loop.1.latch

loop.1.latch:
  %l.lcssa = phi i32 [ %l, %loop.1.header ], [ %l, %loop.1.header ]
  %iv.1.next = add nuw nsw i32 %iv.1, 1
  %ec.1 = icmp eq i32 %iv.1.next, 100
  br i1 %ec.1, label %exit.1, label %loop.1.header

exit.1:
  %l.lcssa.lcssa = phi i32 [ %l.lcssa, %loop.1.latch ]
  br label %loop.2

loop.2:
  %iv.2 = phi i8 [ 0, %exit.1 ], [ %iv.2.next, %loop.2 ]
  %iv.2.next = add i8 %iv.2, 1
  %gep.A = getelementptr i8, ptr %A, i8 %iv.2.next
  store i8 0, ptr %gep.A
  %iv.2.sext = sext i8 %iv.2 to i32
  %ec.2 = icmp sge i32 %l.lcssa.lcssa, %iv.2.sext
  br i1 %ec.2, label %loop.2, label %exit.2

exit.2:
  ret void
}