| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6 |
| ; RUN: opt -passes=loop-vectorize -S < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE |
| ; RUN: opt -passes=loop-vectorize -S < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE |
| ; RUN: opt -passes=loop-vectorize -S < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefix=AVX2 |
| ; RUN: opt -passes=loop-vectorize -S < %s -mtriple=x86_64-- -mattr=+avx512f | FileCheck %s --check-prefix=AVX512F |
| ; RUN: opt -passes=loop-vectorize -S < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512dq | FileCheck %s --check-prefix=AVX512DQ |
| ; RUN: opt -passes=loop-vectorize -S < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512dq,+avx512vl,+prefer-256-bit | FileCheck %s --check-prefix=AVX512DQ256 |
| |
| ; Division of i64 by a loop-invariant constant becomes a magic multiply-high |
| ; sequence, so these loops should vectorize exactly where that sequence is |
| ; formed: MULHU (unsigned) needs AVX2. The signed cases still scalarize their |
| ; multiply everywhere here, so vectorizing them is a measured regression and |
| ; the cost model must decline. |
| ; |
| ; The last RUN line matters on its own: Intel AVX512 CPUs set |
| ; prefer-256-bit, so they read the v4i64 entries rather than the v8i64 |
| ; ones the plain -mattr runs above exercise. |
| |
| define void @udiv_by_const(ptr noalias %o, ptr noalias %i, i64 %n) { |
| ; |
| ; |
| ; SSE-LABEL: define void @udiv_by_const( |
| ; SSE-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; SSE-NEXT: [[ENTRY:.*]]: |
| ; SSE-NEXT: br label %[[LOOP:.*]] |
| ; SSE: [[LOOP]]: |
| ; SSE-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; SSE-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; SSE-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; SSE-NEXT: [[D:%.*]] = udiv i64 [[V]], 1000000007 |
| ; SSE-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; SSE-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; SSE-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; SSE-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; SSE-NEXT: br i1 [[C]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; SSE: [[EXIT]]: |
| ; SSE-NEXT: ret void |
| ; |
| ; AVX2-LABEL: define void @udiv_by_const( |
| ; AVX2-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; AVX2-NEXT: [[ITER_CHECK:.*]]: |
| ; AVX2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 |
| ; AVX2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]] |
| ; AVX2: [[VECTOR_MAIN_LOOP_ITER_CHECK]]: |
| ; AVX2-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N]], 16 |
| ; AVX2-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; AVX2: [[VECTOR_PH]]: |
| ; AVX2-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 15 |
| ; AVX2-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] |
| ; AVX2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; AVX2: [[VECTOR_BODY]]: |
| ; AVX2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; AVX2-NEXT: [[TMP0:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX]] |
| ; AVX2-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr [[TMP0]], i64 4 |
| ; AVX2-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[TMP0]], i64 8 |
| ; AVX2-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[TMP0]], i64 12 |
| ; AVX2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP0]], align 8 |
| ; AVX2-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i64>, ptr [[TMP1]], align 8 |
| ; AVX2-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8 |
| ; AVX2-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8 |
| ; AVX2-NEXT: [[TMP4:%.*]] = udiv <4 x i64> [[WIDE_LOAD]], splat (i64 1000000007) |
| ; AVX2-NEXT: [[TMP5:%.*]] = udiv <4 x i64> [[WIDE_LOAD2]], splat (i64 1000000007) |
| ; AVX2-NEXT: [[TMP6:%.*]] = udiv <4 x i64> [[WIDE_LOAD3]], splat (i64 1000000007) |
| ; AVX2-NEXT: [[TMP7:%.*]] = udiv <4 x i64> [[WIDE_LOAD4]], splat (i64 1000000007) |
| ; AVX2-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX]] |
| ; AVX2-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP8]], i64 4 |
| ; AVX2-NEXT: [[TMP10:%.*]] = getelementptr i64, ptr [[TMP8]], i64 8 |
| ; AVX2-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[TMP8]], i64 12 |
| ; AVX2-NEXT: store <4 x i64> [[TMP4]], ptr [[TMP8]], align 8 |
| ; AVX2-NEXT: store <4 x i64> [[TMP5]], ptr [[TMP9]], align 8 |
| ; AVX2-NEXT: store <4 x i64> [[TMP6]], ptr [[TMP10]], align 8 |
| ; AVX2-NEXT: store <4 x i64> [[TMP7]], ptr [[TMP11]], align 8 |
| ; AVX2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 |
| ; AVX2-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; AVX2-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; AVX2: [[MIDDLE_BLOCK]]: |
| ; AVX2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] |
| ; AVX2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] |
| ; AVX2: [[VEC_EPILOG_ITER_CHECK]]: |
| ; AVX2-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 4 |
| ; AVX2-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]] |
| ; AVX2: [[VEC_EPILOG_PH]]: |
| ; AVX2-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; AVX2-NEXT: [[N_MOD_VF5:%.*]] = and i64 [[N]], 3 |
| ; AVX2-NEXT: [[N_VEC6:%.*]] = sub i64 [[N]], [[N_MOD_VF5]] |
| ; AVX2-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]] |
| ; AVX2: [[VEC_EPILOG_VECTOR_BODY]]: |
| ; AVX2-NEXT: [[INDEX7:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT9:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; AVX2-NEXT: [[TMP13:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX7]] |
| ; AVX2-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i64>, ptr [[TMP13]], align 8 |
| ; AVX2-NEXT: [[TMP14:%.*]] = udiv <4 x i64> [[WIDE_LOAD8]], splat (i64 1000000007) |
| ; AVX2-NEXT: [[TMP15:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX7]] |
| ; AVX2-NEXT: store <4 x i64> [[TMP14]], ptr [[TMP15]], align 8 |
| ; AVX2-NEXT: [[INDEX_NEXT9]] = add nuw i64 [[INDEX7]], 4 |
| ; AVX2-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT9]], [[N_VEC6]] |
| ; AVX2-NEXT: br i1 [[TMP16]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] |
| ; AVX2: [[VEC_EPILOG_MIDDLE_BLOCK]]: |
| ; AVX2-NEXT: [[CMP_N10:%.*]] = icmp eq i64 [[N]], [[N_VEC6]] |
| ; AVX2-NEXT: br i1 [[CMP_N10]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] |
| ; AVX2: [[VEC_EPILOG_SCALAR_PH]]: |
| ; AVX2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC6]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ] |
| ; AVX2-NEXT: br label %[[LOOP:.*]] |
| ; AVX2: [[LOOP]]: |
| ; AVX2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; AVX2-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX2-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; AVX2-NEXT: [[D:%.*]] = udiv i64 [[V]], 1000000007 |
| ; AVX2-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX2-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX2-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; AVX2-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX2-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] |
| ; AVX2: [[EXIT]]: |
| ; AVX2-NEXT: ret void |
| ; |
| ; AVX512F-LABEL: define void @udiv_by_const( |
| ; AVX512F-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; AVX512F-NEXT: [[ITER_CHECK:.*]]: |
| ; AVX512F-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8 |
| ; AVX512F-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]] |
| ; AVX512F: [[VECTOR_MAIN_LOOP_ITER_CHECK]]: |
| ; AVX512F-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N]], 32 |
| ; AVX512F-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; AVX512F: [[VECTOR_PH]]: |
| ; AVX512F-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 31 |
| ; AVX512F-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] |
| ; AVX512F-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; AVX512F: [[VECTOR_BODY]]: |
| ; AVX512F-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; AVX512F-NEXT: [[TMP0:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX]] |
| ; AVX512F-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr [[TMP0]], i64 8 |
| ; AVX512F-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[TMP0]], i64 16 |
| ; AVX512F-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[TMP0]], i64 24 |
| ; AVX512F-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i64>, ptr [[TMP0]], align 8 |
| ; AVX512F-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i64>, ptr [[TMP1]], align 8 |
| ; AVX512F-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i64>, ptr [[TMP2]], align 8 |
| ; AVX512F-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i64>, ptr [[TMP3]], align 8 |
| ; AVX512F-NEXT: [[TMP4:%.*]] = udiv <8 x i64> [[WIDE_LOAD]], splat (i64 1000000007) |
| ; AVX512F-NEXT: [[TMP5:%.*]] = udiv <8 x i64> [[WIDE_LOAD2]], splat (i64 1000000007) |
| ; AVX512F-NEXT: [[TMP6:%.*]] = udiv <8 x i64> [[WIDE_LOAD3]], splat (i64 1000000007) |
| ; AVX512F-NEXT: [[TMP7:%.*]] = udiv <8 x i64> [[WIDE_LOAD4]], splat (i64 1000000007) |
| ; AVX512F-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX]] |
| ; AVX512F-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP8]], i64 8 |
| ; AVX512F-NEXT: [[TMP10:%.*]] = getelementptr i64, ptr [[TMP8]], i64 16 |
| ; AVX512F-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[TMP8]], i64 24 |
| ; AVX512F-NEXT: store <8 x i64> [[TMP4]], ptr [[TMP8]], align 8 |
| ; AVX512F-NEXT: store <8 x i64> [[TMP5]], ptr [[TMP9]], align 8 |
| ; AVX512F-NEXT: store <8 x i64> [[TMP6]], ptr [[TMP10]], align 8 |
| ; AVX512F-NEXT: store <8 x i64> [[TMP7]], ptr [[TMP11]], align 8 |
| ; AVX512F-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 |
| ; AVX512F-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; AVX512F-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; AVX512F: [[MIDDLE_BLOCK]]: |
| ; AVX512F-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] |
| ; AVX512F-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] |
| ; AVX512F: [[VEC_EPILOG_ITER_CHECK]]: |
| ; AVX512F-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 8 |
| ; AVX512F-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]] |
| ; AVX512F: [[VEC_EPILOG_PH]]: |
| ; AVX512F-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; AVX512F-NEXT: [[N_MOD_VF5:%.*]] = and i64 [[N]], 7 |
| ; AVX512F-NEXT: [[N_VEC6:%.*]] = sub i64 [[N]], [[N_MOD_VF5]] |
| ; AVX512F-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]] |
| ; AVX512F: [[VEC_EPILOG_VECTOR_BODY]]: |
| ; AVX512F-NEXT: [[INDEX7:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT9:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; AVX512F-NEXT: [[TMP13:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX7]] |
| ; AVX512F-NEXT: [[WIDE_LOAD8:%.*]] = load <8 x i64>, ptr [[TMP13]], align 8 |
| ; AVX512F-NEXT: [[TMP14:%.*]] = udiv <8 x i64> [[WIDE_LOAD8]], splat (i64 1000000007) |
| ; AVX512F-NEXT: [[TMP15:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX7]] |
| ; AVX512F-NEXT: store <8 x i64> [[TMP14]], ptr [[TMP15]], align 8 |
| ; AVX512F-NEXT: [[INDEX_NEXT9]] = add nuw i64 [[INDEX7]], 8 |
| ; AVX512F-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT9]], [[N_VEC6]] |
| ; AVX512F-NEXT: br i1 [[TMP16]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] |
| ; AVX512F: [[VEC_EPILOG_MIDDLE_BLOCK]]: |
| ; AVX512F-NEXT: [[CMP_N10:%.*]] = icmp eq i64 [[N]], [[N_VEC6]] |
| ; AVX512F-NEXT: br i1 [[CMP_N10]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] |
| ; AVX512F: [[VEC_EPILOG_SCALAR_PH]]: |
| ; AVX512F-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC6]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ] |
| ; AVX512F-NEXT: br label %[[LOOP:.*]] |
| ; AVX512F: [[LOOP]]: |
| ; AVX512F-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; AVX512F-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX512F-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; AVX512F-NEXT: [[D:%.*]] = udiv i64 [[V]], 1000000007 |
| ; AVX512F-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX512F-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX512F-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; AVX512F-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX512F-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] |
| ; AVX512F: [[EXIT]]: |
| ; AVX512F-NEXT: ret void |
| ; |
| ; AVX512DQ-LABEL: define void @udiv_by_const( |
| ; AVX512DQ-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; AVX512DQ-NEXT: [[ITER_CHECK:.*]]: |
| ; AVX512DQ-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8 |
| ; AVX512DQ-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]] |
| ; AVX512DQ: [[VECTOR_MAIN_LOOP_ITER_CHECK]]: |
| ; AVX512DQ-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N]], 32 |
| ; AVX512DQ-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; AVX512DQ: [[VECTOR_PH]]: |
| ; AVX512DQ-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 31 |
| ; AVX512DQ-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] |
| ; AVX512DQ-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; AVX512DQ: [[VECTOR_BODY]]: |
| ; AVX512DQ-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; AVX512DQ-NEXT: [[TMP0:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX]] |
| ; AVX512DQ-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr [[TMP0]], i64 8 |
| ; AVX512DQ-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[TMP0]], i64 16 |
| ; AVX512DQ-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[TMP0]], i64 24 |
| ; AVX512DQ-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i64>, ptr [[TMP0]], align 8 |
| ; AVX512DQ-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i64>, ptr [[TMP1]], align 8 |
| ; AVX512DQ-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i64>, ptr [[TMP2]], align 8 |
| ; AVX512DQ-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i64>, ptr [[TMP3]], align 8 |
| ; AVX512DQ-NEXT: [[TMP4:%.*]] = udiv <8 x i64> [[WIDE_LOAD]], splat (i64 1000000007) |
| ; AVX512DQ-NEXT: [[TMP5:%.*]] = udiv <8 x i64> [[WIDE_LOAD2]], splat (i64 1000000007) |
| ; AVX512DQ-NEXT: [[TMP6:%.*]] = udiv <8 x i64> [[WIDE_LOAD3]], splat (i64 1000000007) |
| ; AVX512DQ-NEXT: [[TMP7:%.*]] = udiv <8 x i64> [[WIDE_LOAD4]], splat (i64 1000000007) |
| ; AVX512DQ-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX]] |
| ; AVX512DQ-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP8]], i64 8 |
| ; AVX512DQ-NEXT: [[TMP10:%.*]] = getelementptr i64, ptr [[TMP8]], i64 16 |
| ; AVX512DQ-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[TMP8]], i64 24 |
| ; AVX512DQ-NEXT: store <8 x i64> [[TMP4]], ptr [[TMP8]], align 8 |
| ; AVX512DQ-NEXT: store <8 x i64> [[TMP5]], ptr [[TMP9]], align 8 |
| ; AVX512DQ-NEXT: store <8 x i64> [[TMP6]], ptr [[TMP10]], align 8 |
| ; AVX512DQ-NEXT: store <8 x i64> [[TMP7]], ptr [[TMP11]], align 8 |
| ; AVX512DQ-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 |
| ; AVX512DQ-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; AVX512DQ-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; AVX512DQ: [[MIDDLE_BLOCK]]: |
| ; AVX512DQ-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] |
| ; AVX512DQ-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] |
| ; AVX512DQ: [[VEC_EPILOG_ITER_CHECK]]: |
| ; AVX512DQ-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 8 |
| ; AVX512DQ-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]] |
| ; AVX512DQ: [[VEC_EPILOG_PH]]: |
| ; AVX512DQ-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; AVX512DQ-NEXT: [[N_MOD_VF5:%.*]] = and i64 [[N]], 7 |
| ; AVX512DQ-NEXT: [[N_VEC6:%.*]] = sub i64 [[N]], [[N_MOD_VF5]] |
| ; AVX512DQ-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]] |
| ; AVX512DQ: [[VEC_EPILOG_VECTOR_BODY]]: |
| ; AVX512DQ-NEXT: [[INDEX7:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT9:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; AVX512DQ-NEXT: [[TMP13:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX7]] |
| ; AVX512DQ-NEXT: [[WIDE_LOAD8:%.*]] = load <8 x i64>, ptr [[TMP13]], align 8 |
| ; AVX512DQ-NEXT: [[TMP14:%.*]] = udiv <8 x i64> [[WIDE_LOAD8]], splat (i64 1000000007) |
| ; AVX512DQ-NEXT: [[TMP15:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX7]] |
| ; AVX512DQ-NEXT: store <8 x i64> [[TMP14]], ptr [[TMP15]], align 8 |
| ; AVX512DQ-NEXT: [[INDEX_NEXT9]] = add nuw i64 [[INDEX7]], 8 |
| ; AVX512DQ-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT9]], [[N_VEC6]] |
| ; AVX512DQ-NEXT: br i1 [[TMP16]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] |
| ; AVX512DQ: [[VEC_EPILOG_MIDDLE_BLOCK]]: |
| ; AVX512DQ-NEXT: [[CMP_N10:%.*]] = icmp eq i64 [[N]], [[N_VEC6]] |
| ; AVX512DQ-NEXT: br i1 [[CMP_N10]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] |
| ; AVX512DQ: [[VEC_EPILOG_SCALAR_PH]]: |
| ; AVX512DQ-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC6]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ] |
| ; AVX512DQ-NEXT: br label %[[LOOP:.*]] |
| ; AVX512DQ: [[LOOP]]: |
| ; AVX512DQ-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; AVX512DQ-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX512DQ-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; AVX512DQ-NEXT: [[D:%.*]] = udiv i64 [[V]], 1000000007 |
| ; AVX512DQ-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX512DQ-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX512DQ-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; AVX512DQ-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX512DQ-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] |
| ; AVX512DQ: [[EXIT]]: |
| ; AVX512DQ-NEXT: ret void |
| ; |
| ; AVX512DQ256-LABEL: define void @udiv_by_const( |
| ; AVX512DQ256-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; AVX512DQ256-NEXT: [[ITER_CHECK:.*]]: |
| ; AVX512DQ256-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 |
| ; AVX512DQ256-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]] |
| ; AVX512DQ256: [[VECTOR_MAIN_LOOP_ITER_CHECK]]: |
| ; AVX512DQ256-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N]], 16 |
| ; AVX512DQ256-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; AVX512DQ256: [[VECTOR_PH]]: |
| ; AVX512DQ256-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 15 |
| ; AVX512DQ256-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] |
| ; AVX512DQ256-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; AVX512DQ256: [[VECTOR_BODY]]: |
| ; AVX512DQ256-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; AVX512DQ256-NEXT: [[TMP0:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX]] |
| ; AVX512DQ256-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr [[TMP0]], i64 4 |
| ; AVX512DQ256-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[TMP0]], i64 8 |
| ; AVX512DQ256-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[TMP0]], i64 12 |
| ; AVX512DQ256-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP0]], align 8 |
| ; AVX512DQ256-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i64>, ptr [[TMP1]], align 8 |
| ; AVX512DQ256-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8 |
| ; AVX512DQ256-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8 |
| ; AVX512DQ256-NEXT: [[TMP4:%.*]] = udiv <4 x i64> [[WIDE_LOAD]], splat (i64 1000000007) |
| ; AVX512DQ256-NEXT: [[TMP5:%.*]] = udiv <4 x i64> [[WIDE_LOAD2]], splat (i64 1000000007) |
| ; AVX512DQ256-NEXT: [[TMP6:%.*]] = udiv <4 x i64> [[WIDE_LOAD3]], splat (i64 1000000007) |
| ; AVX512DQ256-NEXT: [[TMP7:%.*]] = udiv <4 x i64> [[WIDE_LOAD4]], splat (i64 1000000007) |
| ; AVX512DQ256-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX]] |
| ; AVX512DQ256-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP8]], i64 4 |
| ; AVX512DQ256-NEXT: [[TMP10:%.*]] = getelementptr i64, ptr [[TMP8]], i64 8 |
| ; AVX512DQ256-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[TMP8]], i64 12 |
| ; AVX512DQ256-NEXT: store <4 x i64> [[TMP4]], ptr [[TMP8]], align 8 |
| ; AVX512DQ256-NEXT: store <4 x i64> [[TMP5]], ptr [[TMP9]], align 8 |
| ; AVX512DQ256-NEXT: store <4 x i64> [[TMP6]], ptr [[TMP10]], align 8 |
| ; AVX512DQ256-NEXT: store <4 x i64> [[TMP7]], ptr [[TMP11]], align 8 |
| ; AVX512DQ256-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 |
| ; AVX512DQ256-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; AVX512DQ256-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; AVX512DQ256: [[MIDDLE_BLOCK]]: |
| ; AVX512DQ256-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] |
| ; AVX512DQ256-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] |
| ; AVX512DQ256: [[VEC_EPILOG_ITER_CHECK]]: |
| ; AVX512DQ256-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 4 |
| ; AVX512DQ256-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]] |
| ; AVX512DQ256: [[VEC_EPILOG_PH]]: |
| ; AVX512DQ256-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; AVX512DQ256-NEXT: [[N_MOD_VF5:%.*]] = and i64 [[N]], 3 |
| ; AVX512DQ256-NEXT: [[N_VEC6:%.*]] = sub i64 [[N]], [[N_MOD_VF5]] |
| ; AVX512DQ256-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]] |
| ; AVX512DQ256: [[VEC_EPILOG_VECTOR_BODY]]: |
| ; AVX512DQ256-NEXT: [[INDEX7:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT9:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; AVX512DQ256-NEXT: [[TMP13:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX7]] |
| ; AVX512DQ256-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i64>, ptr [[TMP13]], align 8 |
| ; AVX512DQ256-NEXT: [[TMP14:%.*]] = udiv <4 x i64> [[WIDE_LOAD8]], splat (i64 1000000007) |
| ; AVX512DQ256-NEXT: [[TMP15:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX7]] |
| ; AVX512DQ256-NEXT: store <4 x i64> [[TMP14]], ptr [[TMP15]], align 8 |
| ; AVX512DQ256-NEXT: [[INDEX_NEXT9]] = add nuw i64 [[INDEX7]], 4 |
| ; AVX512DQ256-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT9]], [[N_VEC6]] |
| ; AVX512DQ256-NEXT: br i1 [[TMP16]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] |
| ; AVX512DQ256: [[VEC_EPILOG_MIDDLE_BLOCK]]: |
| ; AVX512DQ256-NEXT: [[CMP_N10:%.*]] = icmp eq i64 [[N]], [[N_VEC6]] |
| ; AVX512DQ256-NEXT: br i1 [[CMP_N10]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] |
| ; AVX512DQ256: [[VEC_EPILOG_SCALAR_PH]]: |
| ; AVX512DQ256-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC6]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ] |
| ; AVX512DQ256-NEXT: br label %[[LOOP:.*]] |
| ; AVX512DQ256: [[LOOP]]: |
| ; AVX512DQ256-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; AVX512DQ256-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX512DQ256-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; AVX512DQ256-NEXT: [[D:%.*]] = udiv i64 [[V]], 1000000007 |
| ; AVX512DQ256-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX512DQ256-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX512DQ256-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; AVX512DQ256-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX512DQ256-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] |
| ; AVX512DQ256: [[EXIT]]: |
| ; AVX512DQ256-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| loop: |
| %iv = phi i64 [0, %entry], [%iv.n, %loop] |
| %p = getelementptr i64, ptr %i, i64 %iv |
| %v = load i64, ptr %p |
| %d = udiv i64 %v, 1000000007 |
| %q = getelementptr i64, ptr %o, i64 %iv |
| store i64 %d, ptr %q |
| %iv.n = add i64 %iv, 1 |
| %c = icmp eq i64 %iv.n, %n |
| br i1 %c, label %exit, label %loop |
| exit: |
| ret void |
| } |
| |
| define void @urem_by_const(ptr noalias %o, ptr noalias %i, i64 %n) { |
| ; |
| ; |
| ; SSE-LABEL: define void @urem_by_const( |
| ; SSE-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; SSE-NEXT: [[ENTRY:.*]]: |
| ; SSE-NEXT: br label %[[LOOP:.*]] |
| ; SSE: [[LOOP]]: |
| ; SSE-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; SSE-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; SSE-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; SSE-NEXT: [[D:%.*]] = urem i64 [[V]], 1000000007 |
| ; SSE-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; SSE-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; SSE-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; SSE-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; SSE-NEXT: br i1 [[C]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; SSE: [[EXIT]]: |
| ; SSE-NEXT: ret void |
| ; |
| ; AVX2-LABEL: define void @urem_by_const( |
| ; AVX2-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; AVX2-NEXT: [[ENTRY:.*]]: |
| ; AVX2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 |
| ; AVX2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; AVX2: [[VECTOR_PH]]: |
| ; AVX2-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 3 |
| ; AVX2-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] |
| ; AVX2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; AVX2: [[VECTOR_BODY]]: |
| ; AVX2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; AVX2-NEXT: [[TMP0:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX]] |
| ; AVX2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP0]], align 8 |
| ; AVX2-NEXT: [[TMP1:%.*]] = urem <4 x i64> [[WIDE_LOAD]], splat (i64 1000000007) |
| ; AVX2-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX]] |
| ; AVX2-NEXT: store <4 x i64> [[TMP1]], ptr [[TMP2]], align 8 |
| ; AVX2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; AVX2-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; AVX2-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] |
| ; AVX2: [[MIDDLE_BLOCK]]: |
| ; AVX2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] |
| ; AVX2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; AVX2: [[SCALAR_PH]]: |
| ; AVX2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; AVX2-NEXT: br label %[[LOOP:.*]] |
| ; AVX2: [[LOOP]]: |
| ; AVX2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; AVX2-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX2-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; AVX2-NEXT: [[D:%.*]] = urem i64 [[V]], 1000000007 |
| ; AVX2-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX2-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX2-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; AVX2-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX2-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] |
| ; AVX2: [[EXIT]]: |
| ; AVX2-NEXT: ret void |
| ; |
| ; AVX512F-LABEL: define void @urem_by_const( |
| ; AVX512F-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; AVX512F-NEXT: [[ENTRY:.*]]: |
| ; AVX512F-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8 |
| ; AVX512F-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; AVX512F: [[VECTOR_PH]]: |
| ; AVX512F-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 7 |
| ; AVX512F-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] |
| ; AVX512F-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; AVX512F: [[VECTOR_BODY]]: |
| ; AVX512F-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; AVX512F-NEXT: [[TMP0:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX]] |
| ; AVX512F-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i64>, ptr [[TMP0]], align 8 |
| ; AVX512F-NEXT: [[TMP1:%.*]] = urem <8 x i64> [[WIDE_LOAD]], splat (i64 1000000007) |
| ; AVX512F-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX]] |
| ; AVX512F-NEXT: store <8 x i64> [[TMP1]], ptr [[TMP2]], align 8 |
| ; AVX512F-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 |
| ; AVX512F-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; AVX512F-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] |
| ; AVX512F: [[MIDDLE_BLOCK]]: |
| ; AVX512F-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] |
| ; AVX512F-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; AVX512F: [[SCALAR_PH]]: |
| ; AVX512F-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; AVX512F-NEXT: br label %[[LOOP:.*]] |
| ; AVX512F: [[LOOP]]: |
| ; AVX512F-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; AVX512F-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX512F-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; AVX512F-NEXT: [[D:%.*]] = urem i64 [[V]], 1000000007 |
| ; AVX512F-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX512F-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX512F-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; AVX512F-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX512F-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] |
| ; AVX512F: [[EXIT]]: |
| ; AVX512F-NEXT: ret void |
| ; |
| ; AVX512DQ-LABEL: define void @urem_by_const( |
| ; AVX512DQ-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; AVX512DQ-NEXT: [[ENTRY:.*]]: |
| ; AVX512DQ-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8 |
| ; AVX512DQ-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; AVX512DQ: [[VECTOR_PH]]: |
| ; AVX512DQ-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 7 |
| ; AVX512DQ-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] |
| ; AVX512DQ-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; AVX512DQ: [[VECTOR_BODY]]: |
| ; AVX512DQ-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; AVX512DQ-NEXT: [[TMP0:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX]] |
| ; AVX512DQ-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i64>, ptr [[TMP0]], align 8 |
| ; AVX512DQ-NEXT: [[TMP1:%.*]] = urem <8 x i64> [[WIDE_LOAD]], splat (i64 1000000007) |
| ; AVX512DQ-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX]] |
| ; AVX512DQ-NEXT: store <8 x i64> [[TMP1]], ptr [[TMP2]], align 8 |
| ; AVX512DQ-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 |
| ; AVX512DQ-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; AVX512DQ-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] |
| ; AVX512DQ: [[MIDDLE_BLOCK]]: |
| ; AVX512DQ-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] |
| ; AVX512DQ-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; AVX512DQ: [[SCALAR_PH]]: |
| ; AVX512DQ-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; AVX512DQ-NEXT: br label %[[LOOP:.*]] |
| ; AVX512DQ: [[LOOP]]: |
| ; AVX512DQ-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; AVX512DQ-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX512DQ-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; AVX512DQ-NEXT: [[D:%.*]] = urem i64 [[V]], 1000000007 |
| ; AVX512DQ-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX512DQ-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX512DQ-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; AVX512DQ-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX512DQ-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] |
| ; AVX512DQ: [[EXIT]]: |
| ; AVX512DQ-NEXT: ret void |
| ; |
| ; AVX512DQ256-LABEL: define void @urem_by_const( |
| ; AVX512DQ256-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; AVX512DQ256-NEXT: [[ENTRY:.*]]: |
| ; AVX512DQ256-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 |
| ; AVX512DQ256-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; AVX512DQ256: [[VECTOR_PH]]: |
| ; AVX512DQ256-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 3 |
| ; AVX512DQ256-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] |
| ; AVX512DQ256-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; AVX512DQ256: [[VECTOR_BODY]]: |
| ; AVX512DQ256-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; AVX512DQ256-NEXT: [[TMP0:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX]] |
| ; AVX512DQ256-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP0]], align 8 |
| ; AVX512DQ256-NEXT: [[TMP1:%.*]] = urem <4 x i64> [[WIDE_LOAD]], splat (i64 1000000007) |
| ; AVX512DQ256-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX]] |
| ; AVX512DQ256-NEXT: store <4 x i64> [[TMP1]], ptr [[TMP2]], align 8 |
| ; AVX512DQ256-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; AVX512DQ256-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; AVX512DQ256-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] |
| ; AVX512DQ256: [[MIDDLE_BLOCK]]: |
| ; AVX512DQ256-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] |
| ; AVX512DQ256-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; AVX512DQ256: [[SCALAR_PH]]: |
| ; AVX512DQ256-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; AVX512DQ256-NEXT: br label %[[LOOP:.*]] |
| ; AVX512DQ256: [[LOOP]]: |
| ; AVX512DQ256-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; AVX512DQ256-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX512DQ256-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; AVX512DQ256-NEXT: [[D:%.*]] = urem i64 [[V]], 1000000007 |
| ; AVX512DQ256-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX512DQ256-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX512DQ256-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; AVX512DQ256-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX512DQ256-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] |
| ; AVX512DQ256: [[EXIT]]: |
| ; AVX512DQ256-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| loop: |
| %iv = phi i64 [0, %entry], [%iv.n, %loop] |
| %p = getelementptr i64, ptr %i, i64 %iv |
| %v = load i64, ptr %p |
| %d = urem i64 %v, 1000000007 |
| %q = getelementptr i64, ptr %o, i64 %iv |
| store i64 %d, ptr %q |
| %iv.n = add i64 %iv, 1 |
| %c = icmp eq i64 %iv.n, %n |
| br i1 %c, label %exit, label %loop |
| exit: |
| ret void |
| } |
| |
| define void @sdiv_by_const(ptr noalias %o, ptr noalias %i, i64 %n) { |
| ; |
| ; |
| ; SSE-LABEL: define void @sdiv_by_const( |
| ; SSE-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; SSE-NEXT: [[ENTRY:.*]]: |
| ; SSE-NEXT: br label %[[LOOP:.*]] |
| ; SSE: [[LOOP]]: |
| ; SSE-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; SSE-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; SSE-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; SSE-NEXT: [[D:%.*]] = sdiv i64 [[V]], 1000000007 |
| ; SSE-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; SSE-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; SSE-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; SSE-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; SSE-NEXT: br i1 [[C]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; SSE: [[EXIT]]: |
| ; SSE-NEXT: ret void |
| ; |
| ; AVX2-LABEL: define void @sdiv_by_const( |
| ; AVX2-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; AVX2-NEXT: [[ENTRY:.*]]: |
| ; AVX2-NEXT: br label %[[LOOP:.*]] |
| ; AVX2: [[LOOP]]: |
| ; AVX2-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; AVX2-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX2-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; AVX2-NEXT: [[D:%.*]] = sdiv i64 [[V]], 1000000007 |
| ; AVX2-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX2-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX2-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; AVX2-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX2-NEXT: br i1 [[C]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; AVX2: [[EXIT]]: |
| ; AVX2-NEXT: ret void |
| ; |
| ; AVX512F-LABEL: define void @sdiv_by_const( |
| ; AVX512F-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; AVX512F-NEXT: [[ENTRY:.*]]: |
| ; AVX512F-NEXT: br label %[[LOOP:.*]] |
| ; AVX512F: [[LOOP]]: |
| ; AVX512F-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; AVX512F-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX512F-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; AVX512F-NEXT: [[D:%.*]] = sdiv i64 [[V]], 1000000007 |
| ; AVX512F-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX512F-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX512F-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; AVX512F-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX512F-NEXT: br i1 [[C]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; AVX512F: [[EXIT]]: |
| ; AVX512F-NEXT: ret void |
| ; |
| ; AVX512DQ-LABEL: define void @sdiv_by_const( |
| ; AVX512DQ-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; AVX512DQ-NEXT: [[ENTRY:.*]]: |
| ; AVX512DQ-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8 |
| ; AVX512DQ-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]] |
| ; AVX512DQ: [[VECTOR_MAIN_LOOP_ITER_CHECK]]: |
| ; AVX512DQ-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N]], 32 |
| ; AVX512DQ-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; AVX512DQ: [[VECTOR_PH]]: |
| ; AVX512DQ-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 31 |
| ; AVX512DQ-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] |
| ; AVX512DQ-NEXT: br label %[[LOOP:.*]] |
| ; AVX512DQ: [[LOOP]]: |
| ; AVX512DQ-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP]] ] |
| ; AVX512DQ-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX512DQ-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr [[P]], i64 8 |
| ; AVX512DQ-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[P]], i64 16 |
| ; AVX512DQ-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[P]], i64 24 |
| ; AVX512DQ-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i64>, ptr [[P]], align 8 |
| ; AVX512DQ-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i64>, ptr [[TMP1]], align 8 |
| ; AVX512DQ-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i64>, ptr [[TMP2]], align 8 |
| ; AVX512DQ-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i64>, ptr [[TMP3]], align 8 |
| ; AVX512DQ-NEXT: [[TMP4:%.*]] = sdiv <8 x i64> [[WIDE_LOAD]], splat (i64 1000000007) |
| ; AVX512DQ-NEXT: [[TMP5:%.*]] = sdiv <8 x i64> [[WIDE_LOAD2]], splat (i64 1000000007) |
| ; AVX512DQ-NEXT: [[TMP6:%.*]] = sdiv <8 x i64> [[WIDE_LOAD3]], splat (i64 1000000007) |
| ; AVX512DQ-NEXT: [[TMP7:%.*]] = sdiv <8 x i64> [[WIDE_LOAD4]], splat (i64 1000000007) |
| ; AVX512DQ-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX512DQ-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP8]], i64 8 |
| ; AVX512DQ-NEXT: [[TMP10:%.*]] = getelementptr i64, ptr [[TMP8]], i64 16 |
| ; AVX512DQ-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[TMP8]], i64 24 |
| ; AVX512DQ-NEXT: store <8 x i64> [[TMP4]], ptr [[TMP8]], align 8 |
| ; AVX512DQ-NEXT: store <8 x i64> [[TMP5]], ptr [[TMP9]], align 8 |
| ; AVX512DQ-NEXT: store <8 x i64> [[TMP6]], ptr [[TMP10]], align 8 |
| ; AVX512DQ-NEXT: store <8 x i64> [[TMP7]], ptr [[TMP11]], align 8 |
| ; AVX512DQ-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 32 |
| ; AVX512DQ-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; AVX512DQ-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]] |
| ; AVX512DQ: [[MIDDLE_BLOCK]]: |
| ; AVX512DQ-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] |
| ; AVX512DQ-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] |
| ; AVX512DQ: [[VEC_EPILOG_ITER_CHECK]]: |
| ; AVX512DQ-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 8 |
| ; AVX512DQ-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3]] |
| ; AVX512DQ: [[VEC_EPILOG_PH]]: |
| ; AVX512DQ-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; AVX512DQ-NEXT: [[N_MOD_VF5:%.*]] = and i64 [[N]], 7 |
| ; AVX512DQ-NEXT: [[N_VEC6:%.*]] = sub i64 [[N]], [[N_MOD_VF5]] |
| ; AVX512DQ-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]] |
| ; AVX512DQ: [[VEC_EPILOG_VECTOR_BODY]]: |
| ; AVX512DQ-NEXT: [[INDEX7:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT9:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; AVX512DQ-NEXT: [[TMP13:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX7]] |
| ; AVX512DQ-NEXT: [[WIDE_LOAD8:%.*]] = load <8 x i64>, ptr [[TMP13]], align 8 |
| ; AVX512DQ-NEXT: [[TMP14:%.*]] = sdiv <8 x i64> [[WIDE_LOAD8]], splat (i64 1000000007) |
| ; AVX512DQ-NEXT: [[TMP15:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX7]] |
| ; AVX512DQ-NEXT: store <8 x i64> [[TMP14]], ptr [[TMP15]], align 8 |
| ; AVX512DQ-NEXT: [[INDEX_NEXT9]] = add nuw i64 [[INDEX7]], 8 |
| ; AVX512DQ-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT9]], [[N_VEC6]] |
| ; AVX512DQ-NEXT: br i1 [[TMP16]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] |
| ; AVX512DQ: [[VEC_EPILOG_MIDDLE_BLOCK]]: |
| ; AVX512DQ-NEXT: [[CMP_N10:%.*]] = icmp eq i64 [[N]], [[N_VEC6]] |
| ; AVX512DQ-NEXT: br i1 [[CMP_N10]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] |
| ; AVX512DQ: [[VEC_EPILOG_SCALAR_PH]]: |
| ; AVX512DQ-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC6]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ENTRY]] ] |
| ; AVX512DQ-NEXT: br label %[[LOOP1:.*]] |
| ; AVX512DQ: [[LOOP1]]: |
| ; AVX512DQ-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_N:%.*]], %[[LOOP1]] ] |
| ; AVX512DQ-NEXT: [[P1:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV1]] |
| ; AVX512DQ-NEXT: [[V:%.*]] = load i64, ptr [[P1]], align 8 |
| ; AVX512DQ-NEXT: [[D:%.*]] = sdiv i64 [[V]], 1000000007 |
| ; AVX512DQ-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV1]] |
| ; AVX512DQ-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX512DQ-NEXT: [[IV_N]] = add i64 [[IV1]], 1 |
| ; AVX512DQ-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX512DQ-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP1]], !llvm.loop [[LOOP10:![0-9]+]] |
| ; AVX512DQ: [[EXIT]]: |
| ; AVX512DQ-NEXT: ret void |
| ; |
| ; AVX512DQ256-LABEL: define void @sdiv_by_const( |
| ; AVX512DQ256-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; AVX512DQ256-NEXT: [[ENTRY:.*]]: |
| ; AVX512DQ256-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 |
| ; AVX512DQ256-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]] |
| ; AVX512DQ256: [[VECTOR_MAIN_LOOP_ITER_CHECK]]: |
| ; AVX512DQ256-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N]], 16 |
| ; AVX512DQ256-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; AVX512DQ256: [[VECTOR_PH]]: |
| ; AVX512DQ256-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 15 |
| ; AVX512DQ256-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] |
| ; AVX512DQ256-NEXT: br label %[[LOOP:.*]] |
| ; AVX512DQ256: [[LOOP]]: |
| ; AVX512DQ256-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP]] ] |
| ; AVX512DQ256-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX512DQ256-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr [[P]], i64 4 |
| ; AVX512DQ256-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[P]], i64 8 |
| ; AVX512DQ256-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[P]], i64 12 |
| ; AVX512DQ256-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[P]], align 8 |
| ; AVX512DQ256-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i64>, ptr [[TMP1]], align 8 |
| ; AVX512DQ256-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8 |
| ; AVX512DQ256-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8 |
| ; AVX512DQ256-NEXT: [[TMP4:%.*]] = sdiv <4 x i64> [[WIDE_LOAD]], splat (i64 1000000007) |
| ; AVX512DQ256-NEXT: [[TMP5:%.*]] = sdiv <4 x i64> [[WIDE_LOAD2]], splat (i64 1000000007) |
| ; AVX512DQ256-NEXT: [[TMP6:%.*]] = sdiv <4 x i64> [[WIDE_LOAD3]], splat (i64 1000000007) |
| ; AVX512DQ256-NEXT: [[TMP7:%.*]] = sdiv <4 x i64> [[WIDE_LOAD4]], splat (i64 1000000007) |
| ; AVX512DQ256-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX512DQ256-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP8]], i64 4 |
| ; AVX512DQ256-NEXT: [[TMP10:%.*]] = getelementptr i64, ptr [[TMP8]], i64 8 |
| ; AVX512DQ256-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[TMP8]], i64 12 |
| ; AVX512DQ256-NEXT: store <4 x i64> [[TMP4]], ptr [[TMP8]], align 8 |
| ; AVX512DQ256-NEXT: store <4 x i64> [[TMP5]], ptr [[TMP9]], align 8 |
| ; AVX512DQ256-NEXT: store <4 x i64> [[TMP6]], ptr [[TMP10]], align 8 |
| ; AVX512DQ256-NEXT: store <4 x i64> [[TMP7]], ptr [[TMP11]], align 8 |
| ; AVX512DQ256-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 16 |
| ; AVX512DQ256-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; AVX512DQ256-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]] |
| ; AVX512DQ256: [[MIDDLE_BLOCK]]: |
| ; AVX512DQ256-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] |
| ; AVX512DQ256-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] |
| ; AVX512DQ256: [[VEC_EPILOG_ITER_CHECK]]: |
| ; AVX512DQ256-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 4 |
| ; AVX512DQ256-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3]] |
| ; AVX512DQ256: [[VEC_EPILOG_PH]]: |
| ; AVX512DQ256-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; AVX512DQ256-NEXT: [[N_MOD_VF5:%.*]] = and i64 [[N]], 3 |
| ; AVX512DQ256-NEXT: [[N_VEC6:%.*]] = sub i64 [[N]], [[N_MOD_VF5]] |
| ; AVX512DQ256-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]] |
| ; AVX512DQ256: [[VEC_EPILOG_VECTOR_BODY]]: |
| ; AVX512DQ256-NEXT: [[INDEX7:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT9:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; AVX512DQ256-NEXT: [[TMP13:%.*]] = getelementptr i64, ptr [[I]], i64 [[INDEX7]] |
| ; AVX512DQ256-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i64>, ptr [[TMP13]], align 8 |
| ; AVX512DQ256-NEXT: [[TMP14:%.*]] = sdiv <4 x i64> [[WIDE_LOAD8]], splat (i64 1000000007) |
| ; AVX512DQ256-NEXT: [[TMP15:%.*]] = getelementptr i64, ptr [[O]], i64 [[INDEX7]] |
| ; AVX512DQ256-NEXT: store <4 x i64> [[TMP14]], ptr [[TMP15]], align 8 |
| ; AVX512DQ256-NEXT: [[INDEX_NEXT9]] = add nuw i64 [[INDEX7]], 4 |
| ; AVX512DQ256-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT9]], [[N_VEC6]] |
| ; AVX512DQ256-NEXT: br i1 [[TMP16]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] |
| ; AVX512DQ256: [[VEC_EPILOG_MIDDLE_BLOCK]]: |
| ; AVX512DQ256-NEXT: [[CMP_N10:%.*]] = icmp eq i64 [[N]], [[N_VEC6]] |
| ; AVX512DQ256-NEXT: br i1 [[CMP_N10]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] |
| ; AVX512DQ256: [[VEC_EPILOG_SCALAR_PH]]: |
| ; AVX512DQ256-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC6]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ENTRY]] ] |
| ; AVX512DQ256-NEXT: br label %[[LOOP1:.*]] |
| ; AVX512DQ256: [[LOOP1]]: |
| ; AVX512DQ256-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_N:%.*]], %[[LOOP1]] ] |
| ; AVX512DQ256-NEXT: [[P1:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV1]] |
| ; AVX512DQ256-NEXT: [[V:%.*]] = load i64, ptr [[P1]], align 8 |
| ; AVX512DQ256-NEXT: [[D:%.*]] = sdiv i64 [[V]], 1000000007 |
| ; AVX512DQ256-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV1]] |
| ; AVX512DQ256-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX512DQ256-NEXT: [[IV_N]] = add i64 [[IV1]], 1 |
| ; AVX512DQ256-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX512DQ256-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP1]], !llvm.loop [[LOOP10:![0-9]+]] |
| ; AVX512DQ256: [[EXIT]]: |
| ; AVX512DQ256-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| loop: |
| %iv = phi i64 [0, %entry], [%iv.n, %loop] |
| %p = getelementptr i64, ptr %i, i64 %iv |
| %v = load i64, ptr %p |
| %d = sdiv i64 %v, 1000000007 |
| %q = getelementptr i64, ptr %o, i64 %iv |
| store i64 %d, ptr %q |
| %iv.n = add i64 %iv, 1 |
| %c = icmp eq i64 %iv.n, %n |
| br i1 %c, label %exit, label %loop |
| exit: |
| ret void |
| } |
| |
| define void @srem_by_const(ptr noalias %o, ptr noalias %i, i64 %n) { |
| ; |
| ; |
| ; SSE-LABEL: define void @srem_by_const( |
| ; SSE-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; SSE-NEXT: [[ENTRY:.*]]: |
| ; SSE-NEXT: br label %[[LOOP:.*]] |
| ; SSE: [[LOOP]]: |
| ; SSE-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; SSE-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; SSE-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; SSE-NEXT: [[D:%.*]] = srem i64 [[V]], 1000000007 |
| ; SSE-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; SSE-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; SSE-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; SSE-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; SSE-NEXT: br i1 [[C]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; SSE: [[EXIT]]: |
| ; SSE-NEXT: ret void |
| ; |
| ; AVX2-LABEL: define void @srem_by_const( |
| ; AVX2-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; AVX2-NEXT: [[ENTRY:.*]]: |
| ; AVX2-NEXT: br label %[[LOOP:.*]] |
| ; AVX2: [[LOOP]]: |
| ; AVX2-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; AVX2-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX2-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; AVX2-NEXT: [[D:%.*]] = srem i64 [[V]], 1000000007 |
| ; AVX2-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX2-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX2-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; AVX2-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX2-NEXT: br i1 [[C]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; AVX2: [[EXIT]]: |
| ; AVX2-NEXT: ret void |
| ; |
| ; AVX512F-LABEL: define void @srem_by_const( |
| ; AVX512F-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; AVX512F-NEXT: [[ENTRY:.*]]: |
| ; AVX512F-NEXT: br label %[[LOOP:.*]] |
| ; AVX512F: [[LOOP]]: |
| ; AVX512F-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_N:%.*]], %[[LOOP]] ] |
| ; AVX512F-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX512F-NEXT: [[V:%.*]] = load i64, ptr [[P]], align 8 |
| ; AVX512F-NEXT: [[D:%.*]] = srem i64 [[V]], 1000000007 |
| ; AVX512F-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX512F-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX512F-NEXT: [[IV_N]] = add i64 [[IV]], 1 |
| ; AVX512F-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX512F-NEXT: br i1 [[C]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; AVX512F: [[EXIT]]: |
| ; AVX512F-NEXT: ret void |
| ; |
| ; AVX512DQ-LABEL: define void @srem_by_const( |
| ; AVX512DQ-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; AVX512DQ-NEXT: [[ENTRY:.*]]: |
| ; AVX512DQ-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8 |
| ; AVX512DQ-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; AVX512DQ: [[VECTOR_PH]]: |
| ; AVX512DQ-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 7 |
| ; AVX512DQ-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] |
| ; AVX512DQ-NEXT: br label %[[LOOP:.*]] |
| ; AVX512DQ: [[LOOP]]: |
| ; AVX512DQ-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP]] ] |
| ; AVX512DQ-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX512DQ-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i64>, ptr [[P]], align 8 |
| ; AVX512DQ-NEXT: [[TMP1:%.*]] = srem <8 x i64> [[WIDE_LOAD]], splat (i64 1000000007) |
| ; AVX512DQ-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX512DQ-NEXT: store <8 x i64> [[TMP1]], ptr [[TMP2]], align 8 |
| ; AVX512DQ-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 8 |
| ; AVX512DQ-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; AVX512DQ-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]] |
| ; AVX512DQ: [[MIDDLE_BLOCK]]: |
| ; AVX512DQ-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] |
| ; AVX512DQ-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; AVX512DQ: [[SCALAR_PH]]: |
| ; AVX512DQ-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; AVX512DQ-NEXT: br label %[[LOOP1:.*]] |
| ; AVX512DQ: [[LOOP1]]: |
| ; AVX512DQ-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_N:%.*]], %[[LOOP1]] ] |
| ; AVX512DQ-NEXT: [[P1:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV1]] |
| ; AVX512DQ-NEXT: [[V:%.*]] = load i64, ptr [[P1]], align 8 |
| ; AVX512DQ-NEXT: [[D:%.*]] = srem i64 [[V]], 1000000007 |
| ; AVX512DQ-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV1]] |
| ; AVX512DQ-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX512DQ-NEXT: [[IV_N]] = add i64 [[IV1]], 1 |
| ; AVX512DQ-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX512DQ-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP1]], !llvm.loop [[LOOP12:![0-9]+]] |
| ; AVX512DQ: [[EXIT]]: |
| ; AVX512DQ-NEXT: ret void |
| ; |
| ; AVX512DQ256-LABEL: define void @srem_by_const( |
| ; AVX512DQ256-SAME: ptr noalias [[O:%.*]], ptr noalias [[I:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { |
| ; AVX512DQ256-NEXT: [[ENTRY:.*]]: |
| ; AVX512DQ256-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 |
| ; AVX512DQ256-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; AVX512DQ256: [[VECTOR_PH]]: |
| ; AVX512DQ256-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 3 |
| ; AVX512DQ256-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] |
| ; AVX512DQ256-NEXT: br label %[[LOOP:.*]] |
| ; AVX512DQ256: [[LOOP]]: |
| ; AVX512DQ256-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP]] ] |
| ; AVX512DQ256-NEXT: [[P:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV]] |
| ; AVX512DQ256-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[P]], align 8 |
| ; AVX512DQ256-NEXT: [[TMP1:%.*]] = srem <4 x i64> [[WIDE_LOAD]], splat (i64 1000000007) |
| ; AVX512DQ256-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV]] |
| ; AVX512DQ256-NEXT: store <4 x i64> [[TMP1]], ptr [[TMP2]], align 8 |
| ; AVX512DQ256-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 |
| ; AVX512DQ256-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; AVX512DQ256-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]] |
| ; AVX512DQ256: [[MIDDLE_BLOCK]]: |
| ; AVX512DQ256-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] |
| ; AVX512DQ256-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; AVX512DQ256: [[SCALAR_PH]]: |
| ; AVX512DQ256-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; AVX512DQ256-NEXT: br label %[[LOOP1:.*]] |
| ; AVX512DQ256: [[LOOP1]]: |
| ; AVX512DQ256-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_N:%.*]], %[[LOOP1]] ] |
| ; AVX512DQ256-NEXT: [[P1:%.*]] = getelementptr i64, ptr [[I]], i64 [[IV1]] |
| ; AVX512DQ256-NEXT: [[V:%.*]] = load i64, ptr [[P1]], align 8 |
| ; AVX512DQ256-NEXT: [[D:%.*]] = srem i64 [[V]], 1000000007 |
| ; AVX512DQ256-NEXT: [[Q:%.*]] = getelementptr i64, ptr [[O]], i64 [[IV1]] |
| ; AVX512DQ256-NEXT: store i64 [[D]], ptr [[Q]], align 8 |
| ; AVX512DQ256-NEXT: [[IV_N]] = add i64 [[IV1]], 1 |
| ; AVX512DQ256-NEXT: [[C:%.*]] = icmp eq i64 [[IV_N]], [[N]] |
| ; AVX512DQ256-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP1]], !llvm.loop [[LOOP12:![0-9]+]] |
| ; AVX512DQ256: [[EXIT]]: |
| ; AVX512DQ256-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| loop: |
| %iv = phi i64 [0, %entry], [%iv.n, %loop] |
| %p = getelementptr i64, ptr %i, i64 %iv |
| %v = load i64, ptr %p |
| %d = srem i64 %v, 1000000007 |
| %q = getelementptr i64, ptr %o, i64 %iv |
| store i64 %d, ptr %q |
| %iv.n = add i64 %iv, 1 |
| %c = icmp eq i64 %iv.n, %n |
| br i1 %c, label %exit, label %loop |
| exit: |
| ret void |
| } |
| |
