| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 |
| ; RUN: opt -p loop-vectorize -S %s | FileCheck %s |
| |
| target datalayout = "e-m:e-Fn32-i64:64-n32:64-S128-v256:256:256-v512:512:512" |
| target triple = "powerpc64le-unknown-linux-gnu" |
| |
| define i1 @select_exit_cond(ptr %start, ptr %end, i64 %N) { |
| ; CHECK-LABEL: define i1 @select_exit_cond( |
| ; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: [[ITER_CHECK:.*]]: |
| ; CHECK-NEXT: [[START2:%.*]] = ptrtoaddr ptr [[START]] to i64 |
| ; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64 |
| ; CHECK-NEXT: [[TMP0:%.*]] = freeze i64 [[N]] |
| ; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[END1]], i64 [[START2]]) |
| ; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[UMAX]], [[START2]] |
| ; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP0]], i64 [[TMP1]]) |
| ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[UMIN]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 2 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]] |
| ; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]: |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK3:%.*]] = icmp ult i64 [[TMP2]], 24 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK3]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 24 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] |
| ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[N_VEC]] |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP51:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP52:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI5:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP53:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI6:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP54:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI7:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP55:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI8:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP56:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI9:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP57:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI10:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP58:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI11:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP59:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI12:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP60:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI13:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP61:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI14:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP62:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[STEP_ADD:%.*]] = add nuw <2 x i64> [[VEC_IND]], splat (i64 2) |
| ; CHECK-NEXT: [[STEP_ADD_2:%.*]] = add nuw <2 x i64> [[STEP_ADD]], splat (i64 2) |
| ; CHECK-NEXT: [[STEP_ADD_3:%.*]] = add nuw <2 x i64> [[STEP_ADD_2]], splat (i64 2) |
| ; CHECK-NEXT: [[STEP_ADD_4:%.*]] = add nuw <2 x i64> [[STEP_ADD_3]], splat (i64 2) |
| ; CHECK-NEXT: [[STEP_ADD_5:%.*]] = add nuw <2 x i64> [[STEP_ADD_4]], splat (i64 2) |
| ; CHECK-NEXT: [[STEP_ADD_6:%.*]] = add nuw <2 x i64> [[STEP_ADD_5]], splat (i64 2) |
| ; CHECK-NEXT: [[STEP_ADD_7:%.*]] = add nuw <2 x i64> [[STEP_ADD_6]], splat (i64 2) |
| ; CHECK-NEXT: [[STEP_ADD_8:%.*]] = add nuw <2 x i64> [[STEP_ADD_7]], splat (i64 2) |
| ; CHECK-NEXT: [[STEP_ADD_9:%.*]] = add nuw <2 x i64> [[STEP_ADD_8]], splat (i64 2) |
| ; CHECK-NEXT: [[STEP_ADD_10:%.*]] = add nuw <2 x i64> [[STEP_ADD_9]], splat (i64 2) |
| ; CHECK-NEXT: [[STEP_ADD_11:%.*]] = add nuw <2 x i64> [[STEP_ADD_10]], splat (i64 2) |
| ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[INDEX]] |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 2 |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 4 |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 6 |
| ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 8 |
| ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 10 |
| ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 12 |
| ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 14 |
| ; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 16 |
| ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 18 |
| ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 20 |
| ; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 22 |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[NEXT_GEP]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD15:%.*]] = load <2 x i8>, ptr [[TMP4]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD16:%.*]] = load <2 x i8>, ptr [[TMP5]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD17:%.*]] = load <2 x i8>, ptr [[TMP6]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD18:%.*]] = load <2 x i8>, ptr [[TMP7]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD19:%.*]] = load <2 x i8>, ptr [[TMP8]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD20:%.*]] = load <2 x i8>, ptr [[TMP9]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD21:%.*]] = load <2 x i8>, ptr [[TMP10]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD22:%.*]] = load <2 x i8>, ptr [[TMP11]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD23:%.*]] = load <2 x i8>, ptr [[TMP12]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD24:%.*]] = load <2 x i8>, ptr [[TMP13]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD25:%.*]] = load <2 x i8>, ptr [[TMP14]], align 1 |
| ; CHECK-NEXT: [[TMP15:%.*]] = zext <2 x i8> [[WIDE_LOAD]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP16:%.*]] = zext <2 x i8> [[WIDE_LOAD15]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP17:%.*]] = zext <2 x i8> [[WIDE_LOAD16]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP18:%.*]] = zext <2 x i8> [[WIDE_LOAD17]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP19:%.*]] = zext <2 x i8> [[WIDE_LOAD18]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP20:%.*]] = zext <2 x i8> [[WIDE_LOAD19]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP21:%.*]] = zext <2 x i8> [[WIDE_LOAD20]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP22:%.*]] = zext <2 x i8> [[WIDE_LOAD21]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP23:%.*]] = zext <2 x i8> [[WIDE_LOAD22]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP24:%.*]] = zext <2 x i8> [[WIDE_LOAD23]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP25:%.*]] = zext <2 x i8> [[WIDE_LOAD24]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP26:%.*]] = zext <2 x i8> [[WIDE_LOAD25]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP27:%.*]] = shl <2 x i64> [[VEC_IND]], splat (i64 1) |
| ; CHECK-NEXT: [[TMP28:%.*]] = shl <2 x i64> [[STEP_ADD]], splat (i64 1) |
| ; CHECK-NEXT: [[TMP29:%.*]] = shl <2 x i64> [[STEP_ADD_2]], splat (i64 1) |
| ; CHECK-NEXT: [[TMP30:%.*]] = shl <2 x i64> [[STEP_ADD_3]], splat (i64 1) |
| ; CHECK-NEXT: [[TMP31:%.*]] = shl <2 x i64> [[STEP_ADD_4]], splat (i64 1) |
| ; CHECK-NEXT: [[TMP32:%.*]] = shl <2 x i64> [[STEP_ADD_5]], splat (i64 1) |
| ; CHECK-NEXT: [[TMP33:%.*]] = shl <2 x i64> [[STEP_ADD_6]], splat (i64 1) |
| ; CHECK-NEXT: [[TMP34:%.*]] = shl <2 x i64> [[STEP_ADD_7]], splat (i64 1) |
| ; CHECK-NEXT: [[TMP35:%.*]] = shl <2 x i64> [[STEP_ADD_8]], splat (i64 1) |
| ; CHECK-NEXT: [[TMP36:%.*]] = shl <2 x i64> [[STEP_ADD_9]], splat (i64 1) |
| ; CHECK-NEXT: [[TMP37:%.*]] = shl <2 x i64> [[STEP_ADD_10]], splat (i64 1) |
| ; CHECK-NEXT: [[TMP38:%.*]] = shl <2 x i64> [[STEP_ADD_11]], splat (i64 1) |
| ; CHECK-NEXT: [[TMP39:%.*]] = shl <2 x i64> [[TMP15]], [[TMP27]] |
| ; CHECK-NEXT: [[TMP40:%.*]] = shl <2 x i64> [[TMP16]], [[TMP28]] |
| ; CHECK-NEXT: [[TMP41:%.*]] = shl <2 x i64> [[TMP17]], [[TMP29]] |
| ; CHECK-NEXT: [[TMP42:%.*]] = shl <2 x i64> [[TMP18]], [[TMP30]] |
| ; CHECK-NEXT: [[TMP43:%.*]] = shl <2 x i64> [[TMP19]], [[TMP31]] |
| ; CHECK-NEXT: [[TMP44:%.*]] = shl <2 x i64> [[TMP20]], [[TMP32]] |
| ; CHECK-NEXT: [[TMP45:%.*]] = shl <2 x i64> [[TMP21]], [[TMP33]] |
| ; CHECK-NEXT: [[TMP46:%.*]] = shl <2 x i64> [[TMP22]], [[TMP34]] |
| ; CHECK-NEXT: [[TMP47:%.*]] = shl <2 x i64> [[TMP23]], [[TMP35]] |
| ; CHECK-NEXT: [[TMP48:%.*]] = shl <2 x i64> [[TMP24]], [[TMP36]] |
| ; CHECK-NEXT: [[TMP49:%.*]] = shl <2 x i64> [[TMP25]], [[TMP37]] |
| ; CHECK-NEXT: [[TMP50:%.*]] = shl <2 x i64> [[TMP26]], [[TMP38]] |
| ; CHECK-NEXT: [[TMP51]] = or <2 x i64> [[TMP39]], [[VEC_PHI]] |
| ; CHECK-NEXT: [[TMP52]] = or <2 x i64> [[TMP40]], [[VEC_PHI4]] |
| ; CHECK-NEXT: [[TMP53]] = or <2 x i64> [[TMP41]], [[VEC_PHI5]] |
| ; CHECK-NEXT: [[TMP54]] = or <2 x i64> [[TMP42]], [[VEC_PHI6]] |
| ; CHECK-NEXT: [[TMP55]] = or <2 x i64> [[TMP43]], [[VEC_PHI7]] |
| ; CHECK-NEXT: [[TMP56]] = or <2 x i64> [[TMP44]], [[VEC_PHI8]] |
| ; CHECK-NEXT: [[TMP57]] = or <2 x i64> [[TMP45]], [[VEC_PHI9]] |
| ; CHECK-NEXT: [[TMP58]] = or <2 x i64> [[TMP46]], [[VEC_PHI10]] |
| ; CHECK-NEXT: [[TMP59]] = or <2 x i64> [[TMP47]], [[VEC_PHI11]] |
| ; CHECK-NEXT: [[TMP60]] = or <2 x i64> [[TMP48]], [[VEC_PHI12]] |
| ; CHECK-NEXT: [[TMP61]] = or <2 x i64> [[TMP49]], [[VEC_PHI13]] |
| ; CHECK-NEXT: [[TMP62]] = or <2 x i64> [[TMP50]], [[VEC_PHI14]] |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 24 |
| ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[STEP_ADD_11]], splat (i64 2) |
| ; CHECK-NEXT: [[TMP63:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP63]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[BIN_RDX:%.*]] = or <2 x i64> [[TMP52]], [[TMP51]] |
| ; CHECK-NEXT: [[BIN_RDX26:%.*]] = or <2 x i64> [[TMP53]], [[BIN_RDX]] |
| ; CHECK-NEXT: [[BIN_RDX27:%.*]] = or <2 x i64> [[TMP54]], [[BIN_RDX26]] |
| ; CHECK-NEXT: [[BIN_RDX28:%.*]] = or <2 x i64> [[TMP55]], [[BIN_RDX27]] |
| ; CHECK-NEXT: [[BIN_RDX29:%.*]] = or <2 x i64> [[TMP56]], [[BIN_RDX28]] |
| ; CHECK-NEXT: [[BIN_RDX30:%.*]] = or <2 x i64> [[TMP57]], [[BIN_RDX29]] |
| ; CHECK-NEXT: [[BIN_RDX31:%.*]] = or <2 x i64> [[TMP58]], [[BIN_RDX30]] |
| ; CHECK-NEXT: [[BIN_RDX32:%.*]] = or <2 x i64> [[TMP59]], [[BIN_RDX31]] |
| ; CHECK-NEXT: [[BIN_RDX33:%.*]] = or <2 x i64> [[TMP60]], [[BIN_RDX32]] |
| ; CHECK-NEXT: [[BIN_RDX34:%.*]] = or <2 x i64> [[TMP61]], [[BIN_RDX33]] |
| ; CHECK-NEXT: [[BIN_RDX35:%.*]] = or <2 x i64> [[TMP62]], [[BIN_RDX34]] |
| ; CHECK-NEXT: [[TMP64:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[BIN_RDX35]]) |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] |
| ; CHECK: [[VEC_EPILOG_ITER_CHECK]]: |
| ; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 2 |
| ; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]] |
| ; CHECK: [[VEC_EPILOG_PH]]: |
| ; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP64]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; CHECK-NEXT: [[TMP65:%.*]] = and i64 [[TMP2]], 1 |
| ; CHECK-NEXT: [[N_VEC36:%.*]] = sub i64 [[TMP2]], [[TMP65]] |
| ; CHECK-NEXT: [[TMP66:%.*]] = getelementptr i8, ptr [[START]], i64 [[N_VEC36]] |
| ; CHECK-NEXT: [[TMP67:%.*]] = insertelement <2 x i64> zeroinitializer, i64 [[BC_MERGE_RDX]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[VEC_EPILOG_RESUME_VAL]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[INDUCTION:%.*]] = add <2 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1> |
| ; CHECK-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]] |
| ; CHECK: [[VEC_EPILOG_VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX37:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT42:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND38:%.*]] = phi <2 x i64> [ [[INDUCTION]], %[[VEC_EPILOG_PH]] ], [ [[VEC_IND_NEXT43:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI39:%.*]] = phi <2 x i64> [ [[TMP67]], %[[VEC_EPILOG_PH]] ], [ [[TMP71:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[NEXT_GEP40:%.*]] = getelementptr i8, ptr [[START]], i64 [[INDEX37]] |
| ; CHECK-NEXT: [[WIDE_LOAD41:%.*]] = load <2 x i8>, ptr [[NEXT_GEP40]], align 1 |
| ; CHECK-NEXT: [[TMP68:%.*]] = zext <2 x i8> [[WIDE_LOAD41]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP69:%.*]] = shl <2 x i64> [[VEC_IND38]], splat (i64 1) |
| ; CHECK-NEXT: [[TMP70:%.*]] = shl <2 x i64> [[TMP68]], [[TMP69]] |
| ; CHECK-NEXT: [[TMP71]] = or <2 x i64> [[TMP70]], [[VEC_PHI39]] |
| ; CHECK-NEXT: [[INDEX_NEXT42]] = add nuw i64 [[INDEX37]], 2 |
| ; CHECK-NEXT: [[VEC_IND_NEXT43]] = add <2 x i64> [[VEC_IND38]], splat (i64 2) |
| ; CHECK-NEXT: [[TMP72:%.*]] = icmp eq i64 [[INDEX_NEXT42]], [[N_VEC36]] |
| ; CHECK-NEXT: br i1 [[TMP72]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] |
| ; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[TMP73:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP71]]) |
| ; CHECK-NEXT: [[CMP_N44:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC36]] |
| ; CHECK-NEXT: br i1 [[CMP_N44]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] |
| ; CHECK: [[VEC_EPILOG_SCALAR_PH]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL45:%.*]] = phi i64 [ [[N_VEC36]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ] |
| ; CHECK-NEXT: [[BC_MERGE_RDX46:%.*]] = phi i64 [ [[TMP73]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP64]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL47:%.*]] = phi ptr [ [[TMP66]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP3]], %[[VEC_EPILOG_ITER_CHECK]] ], [ [[START]], %[[ITER_CHECK]] ] |
| ; CHECK-NEXT: br label %[[LOOP:.*]] |
| ; CHECK: [[LOOP]]: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL45]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[RED:%.*]] = phi i64 [ [[BC_MERGE_RDX46]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[RED_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL47]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[TMP74:%.*]] = load i8, ptr [[PTR_IV]], align 1 |
| ; CHECK-NEXT: [[CONV3:%.*]] = zext i8 [[TMP74]] to i64 |
| ; CHECK-NEXT: [[MUL:%.*]] = shl i64 [[IV]], 1 |
| ; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[CONV3]], [[MUL]] |
| ; CHECK-NEXT: [[RED_NEXT]] = or i64 [[SHL]], [[RED]] |
| ; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 1 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[CMP_I166_I:%.*]] = icmp ult ptr [[PTR_IV]], [[END]] |
| ; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i64 [[IV]], [[N]] |
| ; CHECK-NEXT: [[AND:%.*]] = select i1 [[CMP_I166_I]], i1 [[CMP2]], i1 false |
| ; CHECK-NEXT: br i1 [[AND]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP5:![0-9]+]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i64 [ [[RED_NEXT]], %[[LOOP]] ], [ [[TMP64]], %[[MIDDLE_BLOCK]] ], [ [[TMP73]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ] |
| ; CHECK-NEXT: [[RES:%.*]] = icmp eq i64 [[RED_NEXT_LCSSA]], 0 |
| ; CHECK-NEXT: ret i1 [[RES]] |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %red = phi i64 [ 0, %entry ], [ %red.next, %loop ] |
| %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop ] |
| %1 = load i8, ptr %ptr.iv, align 1 |
| %conv3 = zext i8 %1 to i64 |
| %mul = shl i64 %iv, 1 |
| %shl = shl i64 %conv3, %mul |
| %red.next = or i64 %shl, %red |
| %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 1 |
| %iv.next = add i64 %iv, 1 |
| %cmp.i166.i = icmp ult ptr %ptr.iv, %end |
| %cmp2 = icmp ne i64 %iv, %N |
| %and = select i1 %cmp.i166.i, i1 %cmp2, i1 false |
| br i1 %and, label %loop, label %exit |
| |
| exit: |
| %res = icmp eq i64 %red.next, 0 |
| ret i1 %res |
| } |
| ;. |
| ; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} |
| ; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} |
| ; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} |
| ; CHECK: [[PROF3]] = !{!"branch_weights", i32 2, i32 22} |
| ; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} |
| ;. |
