| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6 |
| ; RUN: opt -p loop-vectorize -mtriple=arm64-apple-macosx -S %s | FileCheck %s |
| |
| target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" |
| |
| define i32 @multi_exit_iv_uniform(i32 %a, i64 %N, ptr %dst) { |
| ; CHECK-LABEL: define i32 @multi_exit_iv_uniform( |
| ; CHECK-SAME: i32 [[A:%.*]], i64 [[N:%.*]], ptr [[DST:%.*]]) { |
| ; CHECK-NEXT: [[ENTRY:.*]]: |
| ; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[N]], i64 2147483648) |
| ; CHECK-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[UMIN]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP0]], 16 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP0]], 15 |
| ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i64 16, i64 [[N_MOD_VF]] |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP2]] |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i32> [[BROADCAST_SPLAT]] to <4 x i64> |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[DST]], i64 [[INDEX]] |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[TMP4]], i64 4 |
| ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP4]], i64 8 |
| ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i64, ptr [[TMP4]], i64 12 |
| ; CHECK-NEXT: store <4 x i64> [[TMP3]], ptr [[TMP4]], align 8 |
| ; CHECK-NEXT: store <4 x i64> [[TMP3]], ptr [[TMP5]], align 8 |
| ; CHECK-NEXT: store <4 x i64> [[TMP3]], ptr [[TMP9]], align 8 |
| ; CHECK-NEXT: store <4 x i64> [[TMP3]], ptr [[TMP12]], align 8 |
| ; CHECK-NEXT: [[TMP6]] = add <4 x i32> [[VEC_PHI]], splat (i32 -1) |
| ; CHECK-NEXT: [[TMP7]] = add <4 x i32> [[VEC_PHI1]], splat (i32 -1) |
| ; CHECK-NEXT: [[TMP10]] = add <4 x i32> [[VEC_PHI2]], splat (i32 -1) |
| ; CHECK-NEXT: [[TMP11]] = add <4 x i32> [[VEC_PHI3]], splat (i32 -1) |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 |
| ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP7]], [[TMP6]] |
| ; CHECK-NEXT: [[BIN_RDX4:%.*]] = add <4 x i32> [[TMP10]], [[BIN_RDX]] |
| ; CHECK-NEXT: [[BIN_RDX5:%.*]] = add <4 x i32> [[TMP11]], [[BIN_RDX4]] |
| ; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX5]]) |
| ; CHECK-NEXT: br label %[[SCALAR_PH]] |
| ; CHECK: [[SCALAR_PH]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP13]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-NEXT: br label %[[LOOP_HEADER:.*]] |
| ; CHECK: [[LOOP_HEADER]]: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ] |
| ; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP_LATCH]] ] |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp eq i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_1]], label %[[EXIT_1:.*]], label %[[LOOP_LATCH]] |
| ; CHECK: [[LOOP_LATCH]]: |
| ; CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IV]] |
| ; CHECK-NEXT: [[CONV7:%.*]] = zext i32 [[A]] to i64 |
| ; CHECK-NEXT: store i64 [[CONV7]], ptr [[ARRAYIDX_I]], align 8 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], -1 |
| ; CHECK-NEXT: [[C_2:%.*]] = icmp eq i64 [[IV]], 2147483648 |
| ; CHECK-NEXT: br i1 [[C_2]], label %[[EXIT_2:.*]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] |
| ; CHECK: [[EXIT_1]]: |
| ; CHECK-NEXT: ret i32 10 |
| ; CHECK: [[EXIT_2]]: |
| ; CHECK-NEXT: [[IV_2_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_2_NEXT]], %[[LOOP_LATCH]] ] |
| ; CHECK-NEXT: ret i32 [[IV_2_NEXT_LCSSA]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop.latch ] |
| %c.1 = icmp eq i64 %iv, %N |
| br i1 %c.1, label %exit.1, label %loop.latch |
| |
| loop.latch: |
| %arrayidx.i = getelementptr i64, ptr %dst, i64 %iv |
| %conv7 = zext i32 %a to i64 |
| store i64 %conv7, ptr %arrayidx.i, align 8 |
| %iv.next = add i64 %iv, 1 |
| %iv.2.next = add i32 %iv.2, -1 |
| %c.2 = icmp eq i64 %iv, 2147483648 |
| br i1 %c.2, label %exit.2, label %loop.header |
| |
| exit.1: |
| ret i32 10 |
| |
| exit.2: |
| ret i32 %iv.2.next |
| } |
| |
| define i64 @pointer_induction_only(ptr %start, ptr %end) { |
| ; CHECK-LABEL: define i64 @pointer_induction_only( |
| ; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) { |
| ; CHECK-NEXT: [[ENTRY:.*]]: |
| ; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64 |
| ; CHECK-NEXT: [[START2:%.*]] = ptrtoaddr ptr [[START]] to i64 |
| ; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]] |
| ; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 2 |
| ; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 8 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP2]], 7 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] |
| ; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[N_VEC]], 2 |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP3]] |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[INDEX]], 2 |
| ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 4 |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 1 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 |
| ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i32> [[WIDE_LOAD]] to <4 x i64> |
| ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP8]], i64 2 |
| ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[TMP8]], i64 3 |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; CHECK: [[SCALAR_PH]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ] |
| ; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-NEXT: br label %[[LOOP:.*]] |
| ; CHECK: [[LOOP]]: |
| ; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[RECUR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[RECUR_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[IV]], align 1 |
| ; CHECK-NEXT: [[RECUR_NEXT]] = zext i32 [[L]] to i64 |
| ; CHECK-NEXT: [[IV_NEXT]] = getelementptr inbounds i8, ptr [[IV]], i64 4 |
| ; CHECK-NEXT: [[C:%.*]] = icmp eq ptr [[IV]], [[END]] |
| ; CHECK-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: [[RECUR_LCSSA:%.*]] = phi i64 [ [[RECUR]], %[[LOOP]] ], [ [[VECTOR_RECUR_EXTRACT_FOR_PHI]], %[[MIDDLE_BLOCK]] ] |
| ; CHECK-NEXT: ret i64 [[RECUR_LCSSA]] |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi ptr [ %start, %entry ], [ %iv.next, %loop ] |
| %recur = phi i64 [ 0, %entry ], [ %recur.next, %loop ] |
| %l = load i32, ptr %iv, align 1 |
| %recur.next = zext i32 %l to i64 |
| %iv.next = getelementptr inbounds i8, ptr %iv, i64 4 |
| %c = icmp eq ptr %iv, %end |
| br i1 %c, label %exit, label %loop |
| |
| exit: |
| ret i64 %recur |
| } |
| |
| |
| define i64 @int_and_pointer_iv(ptr %start, i32 %N) { |
| ; CHECK-LABEL: define i64 @int_and_pointer_iv( |
| ; CHECK-SAME: ptr [[START:%.*]], i32 [[N:%.*]]) { |
| ; CHECK-NEXT: [[ENTRY:.*:]] |
| ; CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[INDEX]], 2 |
| ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP0]] |
| ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 4 |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 |
| ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000 |
| ; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i32> [[WIDE_LOAD]] to <4 x i64> |
| ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP3]], i64 2 |
| ; CHECK-NEXT: br label %[[EXIT:.*]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret i64 [[VECTOR_RECUR_EXTRACT_FOR_PHI]] |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] |
| %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop ] |
| %recur = phi i64 [ 0, %entry ], [ %recur.next, %loop ] |
| %l = load i32, ptr %ptr.iv, align 4 |
| %recur.next = zext i32 %l to i64 |
| %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 4 |
| %iv.next = add i32 %iv, 1 |
| %tobool.not = icmp eq i32 %iv.next, 1000 |
| br i1 %tobool.not, label %exit, label %loop |
| |
| exit: |
| ret i64 %recur |
| } |
| |
| define void @wide_truncated_iv(ptr %dst) { |
| ; CHECK-LABEL: define void @wide_truncated_iv( |
| ; CHECK-SAME: ptr [[DST:%.*]]) { |
| ; CHECK-NEXT: [[ITER_CHECK:.*]]: |
| ; CHECK-NEXT: br i1 false, label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]] |
| ; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]: |
| ; CHECK-NEXT: br i1 false, label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <16 x i8> [ <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[STEP_ADD:%.*]] = add <16 x i8> [[VEC_IND]], splat (i8 16) |
| ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX]] |
| ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i64 16 |
| ; CHECK-NEXT: store <16 x i8> [[VEC_IND]], ptr [[TMP0]], align 1 |
| ; CHECK-NEXT: store <16 x i8> [[STEP_ADD]], ptr [[TMP1]], align 1 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 |
| ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <16 x i8> [[STEP_ADD]], splat (i8 16) |
| ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 192 |
| ; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br i1 false, label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] |
| ; CHECK: [[VEC_EPILOG_ITER_CHECK]]: |
| ; CHECK-NEXT: br i1 false, label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF8:![0-9]+]] |
| ; CHECK: [[VEC_EPILOG_PH]]: |
| ; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ 192, %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[VEC_EPILOG_RESUME_VAL]] to i8 |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i8> poison, i8 [[TMP3]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i8> [[BROADCAST_SPLATINSERT]], <8 x i8> poison, <8 x i32> zeroinitializer |
| ; CHECK-NEXT: [[INDUCTION:%.*]] = add <8 x i8> [[BROADCAST_SPLAT]], <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7> |
| ; CHECK-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]] |
| ; CHECK: [[VEC_EPILOG_VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX1:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT3:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND2:%.*]] = phi <8 x i8> [ [[INDUCTION]], %[[VEC_EPILOG_PH]] ], [ [[VEC_IND_NEXT4:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX1]] |
| ; CHECK-NEXT: store <8 x i8> [[VEC_IND2]], ptr [[TMP4]], align 1 |
| ; CHECK-NEXT: [[INDEX_NEXT3]] = add nuw i64 [[INDEX1]], 8 |
| ; CHECK-NEXT: [[VEC_IND_NEXT4]] = add <8 x i8> [[VEC_IND2]], splat (i8 8) |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT3]], 200 |
| ; CHECK-NEXT: br i1 [[TMP5]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] |
| ; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br i1 false, label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] |
| ; CHECK: [[VEC_EPILOG_SCALAR_PH]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 200, %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 192, %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ] |
| ; CHECK-NEXT: br label %[[LOOP:.*]] |
| ; CHECK: [[LOOP]]: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[TRUNC_IV:%.*]] = trunc i64 [[IV]] to i8 |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] |
| ; CHECK-NEXT: store i8 [[TRUNC_IV]], ptr [[GEP]], align 1 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[IV]], 200 |
| ; CHECK-NEXT: br i1 [[C]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %trunc.iv = trunc i64 %iv to i8 |
| %gep = getelementptr i8, ptr %dst, i64 %iv |
| store i8 %trunc.iv, ptr %gep, align 1 |
| %iv.next = add i64 %iv, 1 |
| %c = icmp eq i64 %iv, 200 |
| br i1 %c, label %exit, label %loop |
| |
| exit: |
| ret void |
| } |
| |
| define i64 @test_ptr_ivs_and_widened_ivs(ptr %src, i32 %N) { |
| ; CHECK-LABEL: define i64 @test_ptr_ivs_and_widened_ivs( |
| ; CHECK-SAME: ptr [[SRC:%.*]], i32 [[N:%.*]]) { |
| ; CHECK-NEXT: [[ENTRY:.*]]: |
| ; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1 |
| ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 |
| ; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 8 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP2]], 7 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] |
| ; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[N_VEC]], 2 |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP3]] |
| ; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[N_VEC]] to i32 |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4) |
| ; CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[INDEX]], 2 |
| ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP6]] |
| ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 4 |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 |
| ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) |
| ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[TMP9:%.*]] = xor <4 x i32> [[WIDE_LOAD]], splat (i32 1) |
| ; CHECK-NEXT: [[TMP10:%.*]] = zext <4 x i32> [[TMP9]] to <4 x i64> |
| ; CHECK-NEXT: [[TMP11:%.*]] = zext <4 x i32> [[STEP_ADD]] to <4 x i64> |
| ; CHECK-NEXT: [[TMP12:%.*]] = shl <4 x i64> [[TMP10]], [[TMP11]] |
| ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP12]], i64 2 |
| ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[TMP12]], i64 3 |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; CHECK: [[SCALAR_PH]]: |
| ; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ [[SRC]], %[[ENTRY]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-NEXT: br label %[[LOOP:.*]] |
| ; CHECK: [[LOOP]]: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[SHL:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[PTR_IV]], align 4 |
| ; CHECK-NEXT: [[NOT:%.*]] = xor i32 [[L]], 1 |
| ; CHECK-NEXT: [[NOT_EXT:%.*]] = zext i32 [[NOT]] to i64 |
| ; CHECK-NEXT: [[IV_EXT:%.*]] = zext i32 [[IV_1]] to i64 |
| ; CHECK-NEXT: [[SHL]] = shl i64 [[NOT_EXT]], [[IV_EXT]] |
| ; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 4 |
| ; CHECK-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1 |
| ; CHECK-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 |
| ; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_2_NEXT]], [[N]] |
| ; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP12:![0-9]+]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: [[P_LCSSA:%.*]] = phi i64 [ [[P]], %[[LOOP]] ], [ [[VECTOR_RECUR_EXTRACT_FOR_PHI]], %[[MIDDLE_BLOCK]] ] |
| ; CHECK-NEXT: ret i64 [[P_LCSSA]] |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %p = phi i64 [ 0, %entry ], [ %shl, %loop ] |
| %ptr.iv = phi ptr [ %src, %entry ], [ %ptr.iv.next, %loop ] |
| %iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop ] |
| %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ] |
| %l = load i32, ptr %ptr.iv, align 4 |
| %not = xor i32 %l, 1 |
| %not.ext = zext i32 %not to i64 |
| %iv.ext = zext i32 %iv.1 to i64 |
| %shl = shl i64 %not.ext , %iv.ext |
| %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 4 |
| %iv.1.next = add i32 %iv.1, 1 |
| %iv.2.next = add i32 %iv.2, 1 |
| %ec = icmp eq i32 %iv.2.next, %N |
| br i1 %ec, label %exit, label %loop |
| |
| exit: |
| ret i64 %p |
| } |
| |
| define void @zext_iv_increment(ptr %dst, i64 %N) { |
| ; CHECK-LABEL: define void @zext_iv_increment( |
| ; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: [[ENTRY:.*]]: |
| ; CHECK-NEXT: [[UMAX1:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX1]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]] |
| ; CHECK: [[VECTOR_SCEVCHECK]]: |
| ; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[N]], i64 1) |
| ; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32 |
| ; CHECK-NEXT: [[TMP2:%.*]] = add i32 1, [[TMP1]] |
| ; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 1 |
| ; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i64 [[TMP0]], 4294967295 |
| ; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP3]], [[TMP4]] |
| ; CHECK-NEXT: br i1 [[TMP5]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[UMAX1]], 3 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX1]], [[N_MOD_VF]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[N_VEC]] to i32 |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 1 |
| ; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 2 |
| ; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 3 |
| ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr { i32, i32, i32 }, ptr [[DST]], i64 [[INDEX]], i32 2 |
| ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr { i32, i32, i32 }, ptr [[DST]], i64 [[TMP7]], i32 2 |
| ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr { i32, i32, i32 }, ptr [[DST]], i64 [[TMP11]], i32 2 |
| ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr { i32, i32, i32 }, ptr [[DST]], i64 [[TMP14]], i32 2 |
| ; CHECK-NEXT: store i32 0, ptr [[TMP8]], align 8 |
| ; CHECK-NEXT: store i32 0, ptr [[TMP9]], align 8 |
| ; CHECK-NEXT: store i32 0, ptr [[TMP12]], align 8 |
| ; CHECK-NEXT: store i32 0, ptr [[TMP13]], align 8 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX1]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; CHECK: [[SCALAR_PH]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ] |
| ; CHECK-NEXT: br label %[[LOOP:.*]] |
| ; CHECK: [[LOOP]]: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[IV_WIDE:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IV_NEXT_EXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[PATCH_INDEX:%.*]] = getelementptr { i32, i32, i32 }, ptr [[DST]], i64 [[IV_WIDE]], i32 2 |
| ; CHECK-NEXT: store i32 0, ptr [[PATCH_INDEX]], align 8 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 |
| ; CHECK-NEXT: [[IV_NEXT_EXT]] = zext i32 [[IV_NEXT]] to i64 |
| ; CHECK-NEXT: [[EC:%.*]] = icmp ult i64 [[IV_NEXT_EXT]], [[N]] |
| ; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP14:![0-9]+]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] |
| %iv.wide = phi i64 [ 0, %entry ], [ %iv.next.ext, %loop ] |
| %patch_index = getelementptr { i32, i32, i32 }, ptr %dst, i64 %iv.wide, i32 2 |
| store i32 0, ptr %patch_index, align 8 |
| %iv.next = add i32 %iv, 1 |
| %iv.next.ext = zext i32 %iv.next to i64 |
| %ec = icmp ult i64 %iv.next.ext, %N |
| br i1 %ec, label %loop, label %exit |
| |
| exit: |
| ret void |
| } |
| |
| define i32 @load_from_pointer_induction(ptr %start, ptr %end) { |
| ; CHECK-LABEL: define i32 @load_from_pointer_induction( |
| ; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) { |
| ; CHECK-NEXT: [[ENTRY:.*]]: |
| ; CHECK-NEXT: [[END1:%.*]] = ptrtoaddr ptr [[END]] to i64 |
| ; CHECK-NEXT: [[START2:%.*]] = ptrtoaddr ptr [[START]] to i64 |
| ; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.umax.i64(i64 [[END1]], i64 [[START2]]) |
| ; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[TMP0]], 1 |
| ; CHECK-NEXT: [[TMP20:%.*]] = sub i64 [[TMP21]], [[START2]] |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP20]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP20]], 3 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP20]], [[N_MOD_VF]] |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[START]], i64 [[N_VEC]] |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI5:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 1 |
| ; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 2 |
| ; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 3 |
| ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[INDEX]] |
| ; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP3]] |
| ; CHECK-NEXT: [[NEXT_GEP7:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP14]] |
| ; CHECK-NEXT: [[NEXT_GEP8:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP15]] |
| ; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[NEXT_GEP]], align 1 |
| ; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[NEXT_GEP4]], align 1 |
| ; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[NEXT_GEP7]], align 1 |
| ; CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[NEXT_GEP8]], align 1 |
| ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP4]], 1 |
| ; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP5]], 1 |
| ; CHECK-NEXT: [[TMP12:%.*]] = and i32 [[TMP18]], 1 |
| ; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP19]], 1 |
| ; CHECK-NEXT: [[TMP8]] = or i32 [[VEC_PHI]], [[TMP6]] |
| ; CHECK-NEXT: [[TMP9]] = or i32 [[VEC_PHI3]], [[TMP7]] |
| ; CHECK-NEXT: [[TMP16]] = or i32 [[VEC_PHI4]], [[TMP12]] |
| ; CHECK-NEXT: [[TMP17]] = or i32 [[VEC_PHI5]], [[TMP13]] |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[BIN_RDX:%.*]] = or i32 [[TMP9]], [[TMP8]] |
| ; CHECK-NEXT: [[BIN_RDX9:%.*]] = or i32 [[TMP16]], [[BIN_RDX]] |
| ; CHECK-NEXT: [[BIN_RDX10:%.*]] = or i32 [[TMP17]], [[BIN_RDX9]] |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP20]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; CHECK: [[SCALAR_PH]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ] |
| ; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[BIN_RDX10]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-NEXT: br label %[[LOOP:.*]] |
| ; CHECK: [[LOOP]]: |
| ; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[RDX_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[IV]], align 1 |
| ; CHECK-NEXT: [[TMP11:%.*]] = and i32 [[L]], 1 |
| ; CHECK-NEXT: [[RDX_NEXT]] = or i32 [[RDX]], [[TMP11]] |
| ; CHECK-NEXT: [[IV_NEXT]] = getelementptr i8, ptr [[IV]], i64 1 |
| ; CHECK-NEXT: [[EC:%.*]] = icmp ult ptr [[IV]], [[END]] |
| ; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP16:![0-9]+]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: [[RDX_NEXT_LCSSA:%.*]] = phi i32 [ [[RDX_NEXT]], %[[LOOP]] ], [ [[BIN_RDX10]], %[[MIDDLE_BLOCK]] ] |
| ; CHECK-NEXT: ret i32 [[RDX_NEXT_LCSSA]] |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi ptr [ %start, %entry ], [ %iv.next, %loop ] |
| %rdx = phi i32 [ 0, %entry ], [ %rdx.next, %loop ] |
| %l = load i32, ptr %iv, align 1 |
| %1 = and i32 %l, 1 |
| %rdx.next = or i32 %rdx, %1 |
| %iv.next = getelementptr i8, ptr %iv, i64 1 |
| %ec = icmp ult ptr %iv, %end |
| br i1 %ec, label %loop, label %exit |
| |
| exit: |
| ret i32 %rdx.next |
| } |
| |
| ; Test that sext(sub nsw) used in address computation is handled correctly |
| ; in VPlan cost model (must match SCEV's handling). |
| define void@sext_sub_nsw_for_address(ptr %base, i64 %n, ptr %src) #0 { |
| ; |
| ; CHECK-LABEL: define void @sext_sub_nsw_for_address( |
| ; CHECK-SAME: ptr [[BASE:%.*]], i64 [[N:%.*]], ptr [[SRC:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; CHECK-NEXT: [[ITER_CHECK:.*]]: |
| ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 |
| ; CHECK-NEXT: [[SMIN15:%.*]] = call i64 @llvm.smin.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[SMIN15]] |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 2 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]] |
| ; CHECK: [[VECTOR_SCEVCHECK]]: |
| ; CHECK-NEXT: [[SMIN:%.*]] = call i64 @llvm.smin.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[N]], [[SMIN]] |
| ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 -8 |
| ; CHECK-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[TMP2]]) |
| ; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0 |
| ; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1 |
| ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[MUL_RESULT]] |
| ; CHECK-NEXT: [[TMP4:%.*]] = icmp ult ptr [[TMP3]], [[SCEVGEP]] |
| ; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP4]], [[MUL_OVERFLOW]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[MUL_RESULT]] |
| ; CHECK-NEXT: [[TMP7:%.*]] = icmp ult ptr [[TMP6]], [[SRC]] |
| ; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]] |
| ; CHECK-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP2]] to i32 |
| ; CHECK-NEXT: [[MUL4:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP9]]) |
| ; CHECK-NEXT: [[MUL_RESULT5:%.*]] = extractvalue { i32, i1 } [[MUL4]], 0 |
| ; CHECK-NEXT: [[MUL_OVERFLOW6:%.*]] = extractvalue { i32, i1 } [[MUL4]], 1 |
| ; CHECK-NEXT: [[TMP10:%.*]] = icmp slt i32 [[MUL_RESULT5]], 0 |
| ; CHECK-NEXT: [[TMP11:%.*]] = or i1 [[TMP10]], [[MUL_OVERFLOW6]] |
| ; CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i64 [[TMP2]], 4294967295 |
| ; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]] |
| ; CHECK-NEXT: [[TMP14:%.*]] = sub i64 0, [[MUL_RESULT]] |
| ; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP14]] |
| ; CHECK-NEXT: [[TMP16:%.*]] = icmp ugt ptr [[TMP15]], [[BASE]] |
| ; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP16]], [[MUL_OVERFLOW]] |
| ; CHECK-NEXT: [[TMP18:%.*]] = or i1 [[TMP5]], [[TMP8]] |
| ; CHECK-NEXT: [[TMP19:%.*]] = or i1 [[TMP18]], [[TMP13]] |
| ; CHECK-NEXT: [[TMP20:%.*]] = or i1 [[TMP19]], [[TMP17]] |
| ; CHECK-NEXT: br i1 [[TMP20]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]] |
| ; CHECK: [[VECTOR_MEMCHECK]]: |
| ; CHECK-NEXT: [[SCEVGEP10:%.*]] = getelementptr i8, ptr [[SRC]], i64 -8 |
| ; CHECK-NEXT: [[TMP21:%.*]] = shl i64 [[N]], 4 |
| ; CHECK-NEXT: [[TMP22:%.*]] = add i64 [[TMP21]], 8 |
| ; CHECK-NEXT: [[SMIN11:%.*]] = call i64 @llvm.smin.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP23:%.*]] = shl i64 [[SMIN11]], 4 |
| ; CHECK-NEXT: [[TMP24:%.*]] = sub i64 [[TMP22]], [[TMP23]] |
| ; CHECK-NEXT: [[SCEVGEP12:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP24]] |
| ; CHECK-NEXT: [[TMP25:%.*]] = sub i64 [[TMP23]], [[TMP21]] |
| ; CHECK-NEXT: [[SCEVGEP13:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP25]] |
| ; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr i8, ptr [[BASE]], i64 8 |
| ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[SCEVGEP10]], [[SCEVGEP14]] |
| ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SCEVGEP13]], [[SCEVGEP12]] |
| ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] |
| ; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]] |
| ; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]: |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK16:%.*]] = icmp ult i64 [[TMP1]], 8 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK16]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP1]], 7 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]] |
| ; CHECK-NEXT: [[TMP26:%.*]] = shl i64 [[N_VEC]], 1 |
| ; CHECK-NEXT: [[TMP27:%.*]] = sub i64 [[N]], [[N_VEC]] |
| ; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[N_VEC]] to i32 |
| ; CHECK-NEXT: [[TMP29:%.*]] = shl i32 [[TMP28]], 1 |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ <i32 0, i32 2>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[STEP_ADD:%.*]] = add <2 x i32> [[VEC_IND]], splat (i32 4) |
| ; CHECK-NEXT: [[STEP_ADD_2:%.*]] = add <2 x i32> [[STEP_ADD]], splat (i32 4) |
| ; CHECK-NEXT: [[STEP_ADD_3:%.*]] = add <2 x i32> [[STEP_ADD_2]], splat (i32 4) |
| ; CHECK-NEXT: [[TMP30:%.*]] = shl i64 [[INDEX]], 1 |
| ; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP30]], 4 |
| ; CHECK-NEXT: [[TMP32:%.*]] = add i64 [[TMP30]], 8 |
| ; CHECK-NEXT: [[TMP33:%.*]] = add i64 [[TMP30]], 12 |
| ; CHECK-NEXT: [[TMP34:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP30]] |
| ; CHECK-NEXT: [[TMP35:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP31]] |
| ; CHECK-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP32]] |
| ; CHECK-NEXT: [[TMP37:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP33]] |
| ; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[TMP34]], i64 -8 |
| ; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i8, ptr [[TMP35]], i64 -8 |
| ; CHECK-NEXT: [[TMP40:%.*]] = getelementptr i8, ptr [[TMP36]], i64 -8 |
| ; CHECK-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr [[TMP37]], i64 -8 |
| ; CHECK-NEXT: [[TMP42:%.*]] = sub nsw <2 x i32> zeroinitializer, [[VEC_IND]] |
| ; CHECK-NEXT: [[TMP43:%.*]] = sub nsw <2 x i32> zeroinitializer, [[STEP_ADD]] |
| ; CHECK-NEXT: [[TMP44:%.*]] = sub nsw <2 x i32> zeroinitializer, [[STEP_ADD_2]] |
| ; CHECK-NEXT: [[TMP45:%.*]] = sub nsw <2 x i32> zeroinitializer, [[STEP_ADD_3]] |
| ; CHECK-NEXT: [[TMP46:%.*]] = sext <2 x i32> [[TMP42]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP49:%.*]] = sext <2 x i32> [[TMP43]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP52:%.*]] = sext <2 x i32> [[TMP44]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP55:%.*]] = sext <2 x i32> [[TMP45]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP47:%.*]] = extractelement <2 x i64> [[TMP46]], i64 0 |
| ; CHECK-NEXT: [[TMP58:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP47]] |
| ; CHECK-NEXT: [[TMP48:%.*]] = extractelement <2 x i64> [[TMP46]], i64 1 |
| ; CHECK-NEXT: [[TMP59:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP48]] |
| ; CHECK-NEXT: [[TMP50:%.*]] = extractelement <2 x i64> [[TMP49]], i64 0 |
| ; CHECK-NEXT: [[TMP60:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP50]] |
| ; CHECK-NEXT: [[TMP51:%.*]] = extractelement <2 x i64> [[TMP49]], i64 1 |
| ; CHECK-NEXT: [[TMP61:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP51]] |
| ; CHECK-NEXT: [[TMP53:%.*]] = extractelement <2 x i64> [[TMP52]], i64 0 |
| ; CHECK-NEXT: [[TMP62:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP53]] |
| ; CHECK-NEXT: [[TMP54:%.*]] = extractelement <2 x i64> [[TMP52]], i64 1 |
| ; CHECK-NEXT: [[TMP63:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP54]] |
| ; CHECK-NEXT: [[TMP56:%.*]] = extractelement <2 x i64> [[TMP55]], i64 0 |
| ; CHECK-NEXT: [[TMP64:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP56]] |
| ; CHECK-NEXT: [[TMP57:%.*]] = extractelement <2 x i64> [[TMP55]], i64 1 |
| ; CHECK-NEXT: [[TMP65:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP57]] |
| ; CHECK-NEXT: [[TMP66:%.*]] = load double, ptr [[TMP58]], align 8, !alias.scope [[META17:![0-9]+]] |
| ; CHECK-NEXT: [[TMP67:%.*]] = load double, ptr [[TMP59]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP68:%.*]] = insertelement <2 x double> poison, double [[TMP66]], i64 0 |
| ; CHECK-NEXT: [[TMP69:%.*]] = insertelement <2 x double> [[TMP68]], double [[TMP67]], i64 1 |
| ; CHECK-NEXT: [[TMP70:%.*]] = load double, ptr [[TMP60]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP71:%.*]] = load double, ptr [[TMP61]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP72:%.*]] = insertelement <2 x double> poison, double [[TMP70]], i64 0 |
| ; CHECK-NEXT: [[TMP73:%.*]] = insertelement <2 x double> [[TMP72]], double [[TMP71]], i64 1 |
| ; CHECK-NEXT: [[TMP74:%.*]] = load double, ptr [[TMP62]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP75:%.*]] = load double, ptr [[TMP63]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP76:%.*]] = insertelement <2 x double> poison, double [[TMP74]], i64 0 |
| ; CHECK-NEXT: [[TMP77:%.*]] = insertelement <2 x double> [[TMP76]], double [[TMP75]], i64 1 |
| ; CHECK-NEXT: [[TMP78:%.*]] = load double, ptr [[TMP64]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP79:%.*]] = load double, ptr [[TMP65]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP80:%.*]] = insertelement <2 x double> poison, double [[TMP78]], i64 0 |
| ; CHECK-NEXT: [[TMP81:%.*]] = insertelement <2 x double> [[TMP80]], double [[TMP79]], i64 1 |
| ; CHECK-NEXT: [[TMP82:%.*]] = shufflevector <2 x double> zeroinitializer, <2 x double> [[TMP69]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> |
| ; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP82]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> |
| ; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP38]], align 8, !alias.scope [[META20:![0-9]+]], !noalias [[META17]] |
| ; CHECK-NEXT: [[TMP83:%.*]] = shufflevector <2 x double> zeroinitializer, <2 x double> [[TMP73]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> |
| ; CHECK-NEXT: [[INTERLEAVED_VEC17:%.*]] = shufflevector <4 x double> [[TMP83]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> |
| ; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC17]], ptr [[TMP39]], align 8, !alias.scope [[META20]], !noalias [[META17]] |
| ; CHECK-NEXT: [[TMP84:%.*]] = shufflevector <2 x double> zeroinitializer, <2 x double> [[TMP77]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> |
| ; CHECK-NEXT: [[INTERLEAVED_VEC18:%.*]] = shufflevector <4 x double> [[TMP84]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> |
| ; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC18]], ptr [[TMP40]], align 8, !alias.scope [[META20]], !noalias [[META17]] |
| ; CHECK-NEXT: [[TMP85:%.*]] = shufflevector <2 x double> zeroinitializer, <2 x double> [[TMP81]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> |
| ; CHECK-NEXT: [[INTERLEAVED_VEC19:%.*]] = shufflevector <4 x double> [[TMP85]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> |
| ; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC19]], ptr [[TMP41]], align 8, !alias.scope [[META20]], !noalias [[META17]] |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 |
| ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[STEP_ADD_3]], splat (i32 4) |
| ; CHECK-NEXT: [[TMP86:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP86]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] |
| ; CHECK: [[VEC_EPILOG_ITER_CHECK]]: |
| ; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 2 |
| ; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF23:![0-9]+]] |
| ; CHECK: [[VEC_EPILOG_PH]]: |
| ; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL21:%.*]] = phi i32 [ [[TMP29]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; CHECK-NEXT: [[N_MOD_VF22:%.*]] = and i64 [[TMP1]], 1 |
| ; CHECK-NEXT: [[N_VEC23:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF22]] |
| ; CHECK-NEXT: [[TMP87:%.*]] = shl i64 [[N_VEC23]], 1 |
| ; CHECK-NEXT: [[TMP88:%.*]] = sub i64 [[N]], [[N_VEC23]] |
| ; CHECK-NEXT: [[TMP89:%.*]] = trunc i64 [[N_VEC23]] to i32 |
| ; CHECK-NEXT: [[TMP90:%.*]] = shl i32 [[TMP89]], 1 |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[BC_RESUME_VAL21]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[INDUCTION:%.*]] = add <2 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 2> |
| ; CHECK-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]] |
| ; CHECK: [[VEC_EPILOG_VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX24:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT27:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND25:%.*]] = phi <2 x i32> [ [[INDUCTION]], %[[VEC_EPILOG_PH]] ], [ [[VEC_IND_NEXT28:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP91:%.*]] = shl i64 [[INDEX24]], 1 |
| ; CHECK-NEXT: [[TMP92:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP91]] |
| ; CHECK-NEXT: [[TMP93:%.*]] = getelementptr i8, ptr [[TMP92]], i64 -8 |
| ; CHECK-NEXT: [[TMP94:%.*]] = sub nsw <2 x i32> zeroinitializer, [[VEC_IND25]] |
| ; CHECK-NEXT: [[TMP95:%.*]] = sext <2 x i32> [[TMP94]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP96:%.*]] = extractelement <2 x i64> [[TMP95]], i64 0 |
| ; CHECK-NEXT: [[TMP98:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP96]] |
| ; CHECK-NEXT: [[TMP97:%.*]] = extractelement <2 x i64> [[TMP95]], i64 1 |
| ; CHECK-NEXT: [[TMP99:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP97]] |
| ; CHECK-NEXT: [[TMP100:%.*]] = load double, ptr [[TMP98]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP101:%.*]] = load double, ptr [[TMP99]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP102:%.*]] = insertelement <2 x double> poison, double [[TMP100]], i64 0 |
| ; CHECK-NEXT: [[TMP103:%.*]] = insertelement <2 x double> [[TMP102]], double [[TMP101]], i64 1 |
| ; CHECK-NEXT: [[TMP104:%.*]] = shufflevector <2 x double> zeroinitializer, <2 x double> [[TMP103]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> |
| ; CHECK-NEXT: [[INTERLEAVED_VEC26:%.*]] = shufflevector <4 x double> [[TMP104]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> |
| ; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC26]], ptr [[TMP93]], align 8, !alias.scope [[META20]], !noalias [[META17]] |
| ; CHECK-NEXT: [[INDEX_NEXT27]] = add nuw i64 [[INDEX24]], 2 |
| ; CHECK-NEXT: [[VEC_IND_NEXT28]] = add <2 x i32> [[VEC_IND25]], splat (i32 4) |
| ; CHECK-NEXT: [[TMP105:%.*]] = icmp eq i64 [[INDEX_NEXT27]], [[N_VEC23]] |
| ; CHECK-NEXT: br i1 [[TMP105]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP24:![0-9]+]] |
| ; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[CMP_N29:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC23]] |
| ; CHECK-NEXT: br i1 [[CMP_N29]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] |
| ; CHECK: [[VEC_EPILOG_SCALAR_PH]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL23:%.*]] = phi i64 [ [[TMP87]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP26]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MEMCHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL24:%.*]] = phi i64 [ [[TMP88]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP27]], %[[VEC_EPILOG_ITER_CHECK]] ], [ [[N]], %[[VECTOR_MEMCHECK]] ], [ [[N]], %[[VECTOR_SCEVCHECK]] ], [ [[N]], %[[ITER_CHECK]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL25:%.*]] = phi i32 [ [[TMP90]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP29]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MEMCHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ] |
| ; CHECK-NEXT: br label %[[LOOP:.*]] |
| ; CHECK: [[LOOP]]: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL23]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[COUNT:%.*]] = phi i64 [ [[BC_RESUME_VAL24]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[COUNT_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[IV_I32:%.*]] = phi i32 [ [[BC_RESUME_VAL25]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_I32_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr double, ptr [[SRC]], i64 [[IV]] |
| ; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr i8, ptr [[GEP_1]], i64 -8 |
| ; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_2]], align 8 |
| ; CHECK-NEXT: [[NEG:%.*]] = sub nsw i32 0, [[IV_I32]] |
| ; CHECK-NEXT: [[NEG_EXT:%.*]] = sext i32 [[NEG]] to i64 |
| ; CHECK-NEXT: [[GEP_3:%.*]] = getelementptr double, ptr [[BASE]], i64 [[NEG_EXT]] |
| ; CHECK-NEXT: [[L:%.*]] = load double, ptr [[GEP_3]], align 8 |
| ; CHECK-NEXT: store double [[L]], ptr [[GEP_1]], align 8 |
| ; CHECK-NEXT: [[IV_I32_NEXT]] = add i32 [[IV_I32]], 2 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 2 |
| ; CHECK-NEXT: [[COUNT_NEXT]] = add i64 [[COUNT]], -1 |
| ; CHECK-NEXT: [[EC:%.*]] = icmp sgt i64 [[COUNT]], 0 |
| ; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP25:![0-9]+]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %count = phi i64 [ %n, %entry ], [ %count.next, %loop ] |
| %iv.i32 = phi i32 [ 0, %entry ], [ %iv.i32.next, %loop ] |
| %gep.1 = getelementptr double, ptr %src, i64 %iv |
| %gep.2 = getelementptr i8, ptr %gep.1, i64 -8 |
| store double 0.000000e+00, ptr %gep.2, align 8 |
| %neg = sub nsw i32 0, %iv.i32 |
| %neg.ext = sext i32 %neg to i64 |
| %gep.3 = getelementptr double, ptr %base, i64 %neg.ext |
| %l = load double, ptr %gep.3, align 8 |
| store double %l, ptr %gep.1, align 8 |
| %iv.i32.next = add i32 %iv.i32, 2 |
| %iv.next = add i64 %iv, 2 |
| %count.next = add i64 %count, -1 |
| %ec = icmp sgt i64 %count, 0 |
| br i1 %ec, label %loop, label %exit |
| |
| exit: |
| ret void |
| } |
| |
| define i64 @live_out_extract_from_ptr_iv_increment(i64 %count, ptr %start, ptr noalias %dst) { |
| ; CHECK-LABEL: define i64 @live_out_extract_from_ptr_iv_increment( |
| ; CHECK-SAME: i64 [[COUNT:%.*]], ptr [[START:%.*]], ptr noalias [[DST:%.*]]) { |
| ; CHECK-NEXT: [[ITER_CHECK:.*]]: |
| ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[COUNT]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]] |
| ; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]: |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 16 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP0]], 15 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] |
| ; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[N_VEC]], 3 |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP1]] |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[INDEX]], 3 |
| ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], 3 |
| ; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 6 |
| ; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP3]], 9 |
| ; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP3]], 12 |
| ; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP3]], 15 |
| ; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP3]], 18 |
| ; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP3]], 21 |
| ; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[TMP3]], 24 |
| ; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP3]], 27 |
| ; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP3]], 30 |
| ; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 33 |
| ; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP3]], 36 |
| ; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP3]], 39 |
| ; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[TMP3]], 42 |
| ; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[TMP3]], 45 |
| ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP3]] |
| ; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]] |
| ; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]] |
| ; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]] |
| ; CHECK-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP7]] |
| ; CHECK-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP8]] |
| ; CHECK-NEXT: [[NEXT_GEP7:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP9]] |
| ; CHECK-NEXT: [[NEXT_GEP8:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP10]] |
| ; CHECK-NEXT: [[NEXT_GEP9:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP11]] |
| ; CHECK-NEXT: [[NEXT_GEP10:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP12]] |
| ; CHECK-NEXT: [[NEXT_GEP11:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP13]] |
| ; CHECK-NEXT: [[NEXT_GEP12:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP14]] |
| ; CHECK-NEXT: [[NEXT_GEP13:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP15]] |
| ; CHECK-NEXT: [[NEXT_GEP14:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP16]] |
| ; CHECK-NEXT: [[NEXT_GEP15:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP17]] |
| ; CHECK-NEXT: [[NEXT_GEP16:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP18]] |
| ; CHECK-NEXT: [[TMP19:%.*]] = load i8, ptr [[NEXT_GEP]], align 1 |
| ; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[NEXT_GEP2]], align 1 |
| ; CHECK-NEXT: [[TMP21:%.*]] = load i8, ptr [[NEXT_GEP3]], align 1 |
| ; CHECK-NEXT: [[TMP22:%.*]] = load i8, ptr [[NEXT_GEP4]], align 1 |
| ; CHECK-NEXT: [[TMP23:%.*]] = load i8, ptr [[NEXT_GEP5]], align 1 |
| ; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[NEXT_GEP6]], align 1 |
| ; CHECK-NEXT: [[TMP25:%.*]] = load i8, ptr [[NEXT_GEP7]], align 1 |
| ; CHECK-NEXT: [[TMP26:%.*]] = load i8, ptr [[NEXT_GEP8]], align 1 |
| ; CHECK-NEXT: [[TMP27:%.*]] = load i8, ptr [[NEXT_GEP9]], align 1 |
| ; CHECK-NEXT: [[TMP28:%.*]] = load i8, ptr [[NEXT_GEP10]], align 1 |
| ; CHECK-NEXT: [[TMP29:%.*]] = load i8, ptr [[NEXT_GEP11]], align 1 |
| ; CHECK-NEXT: [[TMP30:%.*]] = load i8, ptr [[NEXT_GEP12]], align 1 |
| ; CHECK-NEXT: [[TMP31:%.*]] = load i8, ptr [[NEXT_GEP13]], align 1 |
| ; CHECK-NEXT: [[TMP32:%.*]] = load i8, ptr [[NEXT_GEP14]], align 1 |
| ; CHECK-NEXT: [[TMP33:%.*]] = load i8, ptr [[NEXT_GEP15]], align 1 |
| ; CHECK-NEXT: [[TMP34:%.*]] = load i8, ptr [[NEXT_GEP16]], align 1 |
| ; CHECK-NEXT: [[TMP35:%.*]] = insertelement <16 x i8> poison, i8 [[TMP19]], i64 0 |
| ; CHECK-NEXT: [[TMP36:%.*]] = insertelement <16 x i8> [[TMP35]], i8 [[TMP20]], i64 1 |
| ; CHECK-NEXT: [[TMP37:%.*]] = insertelement <16 x i8> [[TMP36]], i8 [[TMP21]], i64 2 |
| ; CHECK-NEXT: [[TMP38:%.*]] = insertelement <16 x i8> [[TMP37]], i8 [[TMP22]], i64 3 |
| ; CHECK-NEXT: [[TMP39:%.*]] = insertelement <16 x i8> [[TMP38]], i8 [[TMP23]], i64 4 |
| ; CHECK-NEXT: [[TMP40:%.*]] = insertelement <16 x i8> [[TMP39]], i8 [[TMP24]], i64 5 |
| ; CHECK-NEXT: [[TMP41:%.*]] = insertelement <16 x i8> [[TMP40]], i8 [[TMP25]], i64 6 |
| ; CHECK-NEXT: [[TMP42:%.*]] = insertelement <16 x i8> [[TMP41]], i8 [[TMP26]], i64 7 |
| ; CHECK-NEXT: [[TMP43:%.*]] = insertelement <16 x i8> [[TMP42]], i8 [[TMP27]], i64 8 |
| ; CHECK-NEXT: [[TMP44:%.*]] = insertelement <16 x i8> [[TMP43]], i8 [[TMP28]], i64 9 |
| ; CHECK-NEXT: [[TMP45:%.*]] = insertelement <16 x i8> [[TMP44]], i8 [[TMP29]], i64 10 |
| ; CHECK-NEXT: [[TMP46:%.*]] = insertelement <16 x i8> [[TMP45]], i8 [[TMP30]], i64 11 |
| ; CHECK-NEXT: [[TMP47:%.*]] = insertelement <16 x i8> [[TMP46]], i8 [[TMP31]], i64 12 |
| ; CHECK-NEXT: [[TMP48:%.*]] = insertelement <16 x i8> [[TMP47]], i8 [[TMP32]], i64 13 |
| ; CHECK-NEXT: [[TMP49:%.*]] = insertelement <16 x i8> [[TMP48]], i8 [[TMP33]], i64 14 |
| ; CHECK-NEXT: [[TMP50:%.*]] = insertelement <16 x i8> [[TMP49]], i8 [[TMP34]], i64 15 |
| ; CHECK-NEXT: [[TMP51:%.*]] = zext <16 x i8> [[TMP50]] to <16 x i32> |
| ; CHECK-NEXT: [[TMP52:%.*]] = extractelement <16 x i32> [[TMP51]], i64 15 |
| ; CHECK-NEXT: store i32 [[TMP52]], ptr [[DST]], align 4 |
| ; CHECK-NEXT: [[TMP53:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 3 |
| ; CHECK-NEXT: [[TMP54:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 3 |
| ; CHECK-NEXT: [[TMP55:%.*]] = getelementptr i8, ptr [[NEXT_GEP3]], i64 3 |
| ; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr [[NEXT_GEP4]], i64 3 |
| ; CHECK-NEXT: [[TMP57:%.*]] = getelementptr i8, ptr [[NEXT_GEP5]], i64 3 |
| ; CHECK-NEXT: [[TMP58:%.*]] = getelementptr i8, ptr [[NEXT_GEP6]], i64 3 |
| ; CHECK-NEXT: [[TMP59:%.*]] = getelementptr i8, ptr [[NEXT_GEP7]], i64 3 |
| ; CHECK-NEXT: [[TMP60:%.*]] = getelementptr i8, ptr [[NEXT_GEP8]], i64 3 |
| ; CHECK-NEXT: [[TMP61:%.*]] = getelementptr i8, ptr [[NEXT_GEP9]], i64 3 |
| ; CHECK-NEXT: [[TMP62:%.*]] = getelementptr i8, ptr [[NEXT_GEP10]], i64 3 |
| ; CHECK-NEXT: [[TMP63:%.*]] = getelementptr i8, ptr [[NEXT_GEP11]], i64 3 |
| ; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i8, ptr [[NEXT_GEP12]], i64 3 |
| ; CHECK-NEXT: [[TMP65:%.*]] = getelementptr i8, ptr [[NEXT_GEP13]], i64 3 |
| ; CHECK-NEXT: [[TMP66:%.*]] = getelementptr i8, ptr [[NEXT_GEP14]], i64 3 |
| ; CHECK-NEXT: [[TMP67:%.*]] = getelementptr i8, ptr [[NEXT_GEP15]], i64 3 |
| ; CHECK-NEXT: [[TMP68:%.*]] = getelementptr i8, ptr [[NEXT_GEP16]], i64 3 |
| ; CHECK-NEXT: [[TMP69:%.*]] = insertelement <16 x ptr> poison, ptr [[TMP53]], i64 0 |
| ; CHECK-NEXT: [[TMP70:%.*]] = insertelement <16 x ptr> [[TMP69]], ptr [[TMP54]], i64 1 |
| ; CHECK-NEXT: [[TMP71:%.*]] = insertelement <16 x ptr> [[TMP70]], ptr [[TMP55]], i64 2 |
| ; CHECK-NEXT: [[TMP72:%.*]] = insertelement <16 x ptr> [[TMP71]], ptr [[TMP56]], i64 3 |
| ; CHECK-NEXT: [[TMP73:%.*]] = insertelement <16 x ptr> [[TMP72]], ptr [[TMP57]], i64 4 |
| ; CHECK-NEXT: [[TMP74:%.*]] = insertelement <16 x ptr> [[TMP73]], ptr [[TMP58]], i64 5 |
| ; CHECK-NEXT: [[TMP75:%.*]] = insertelement <16 x ptr> [[TMP74]], ptr [[TMP59]], i64 6 |
| ; CHECK-NEXT: [[TMP76:%.*]] = insertelement <16 x ptr> [[TMP75]], ptr [[TMP60]], i64 7 |
| ; CHECK-NEXT: [[TMP77:%.*]] = insertelement <16 x ptr> [[TMP76]], ptr [[TMP61]], i64 8 |
| ; CHECK-NEXT: [[TMP78:%.*]] = insertelement <16 x ptr> [[TMP77]], ptr [[TMP62]], i64 9 |
| ; CHECK-NEXT: [[TMP79:%.*]] = insertelement <16 x ptr> [[TMP78]], ptr [[TMP63]], i64 10 |
| ; CHECK-NEXT: [[TMP80:%.*]] = insertelement <16 x ptr> [[TMP79]], ptr [[TMP64]], i64 11 |
| ; CHECK-NEXT: [[TMP81:%.*]] = insertelement <16 x ptr> [[TMP80]], ptr [[TMP65]], i64 12 |
| ; CHECK-NEXT: [[TMP82:%.*]] = insertelement <16 x ptr> [[TMP81]], ptr [[TMP66]], i64 13 |
| ; CHECK-NEXT: [[TMP83:%.*]] = insertelement <16 x ptr> [[TMP82]], ptr [[TMP67]], i64 14 |
| ; CHECK-NEXT: [[TMP84:%.*]] = insertelement <16 x ptr> [[TMP83]], ptr [[TMP68]], i64 15 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 |
| ; CHECK-NEXT: [[TMP85:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP85]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP26:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[TMP86:%.*]] = ptrtoint <16 x ptr> [[TMP84]] to <16 x i64> |
| ; CHECK-NEXT: [[TMP87:%.*]] = extractelement <16 x i64> [[TMP86]], i64 15 |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] |
| ; CHECK: [[VEC_EPILOG_ITER_CHECK]]: |
| ; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 8 |
| ; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF27:![0-9]+]] |
| ; CHECK: [[VEC_EPILOG_PH]]: |
| ; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; CHECK-NEXT: [[N_MOD_VF17:%.*]] = and i64 [[TMP0]], 7 |
| ; CHECK-NEXT: [[N_VEC18:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF17]] |
| ; CHECK-NEXT: [[TMP88:%.*]] = mul i64 [[N_VEC18]], 3 |
| ; CHECK-NEXT: [[TMP89:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP88]] |
| ; CHECK-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]] |
| ; CHECK: [[VEC_EPILOG_VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX19:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT28:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP90:%.*]] = mul i64 [[INDEX19]], 3 |
| ; CHECK-NEXT: [[TMP91:%.*]] = add i64 [[TMP90]], 3 |
| ; CHECK-NEXT: [[TMP92:%.*]] = add i64 [[TMP90]], 6 |
| ; CHECK-NEXT: [[TMP93:%.*]] = add i64 [[TMP90]], 9 |
| ; CHECK-NEXT: [[TMP94:%.*]] = add i64 [[TMP90]], 12 |
| ; CHECK-NEXT: [[TMP95:%.*]] = add i64 [[TMP90]], 15 |
| ; CHECK-NEXT: [[TMP96:%.*]] = add i64 [[TMP90]], 18 |
| ; CHECK-NEXT: [[TMP97:%.*]] = add i64 [[TMP90]], 21 |
| ; CHECK-NEXT: [[NEXT_GEP20:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP90]] |
| ; CHECK-NEXT: [[NEXT_GEP21:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP91]] |
| ; CHECK-NEXT: [[NEXT_GEP22:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP92]] |
| ; CHECK-NEXT: [[NEXT_GEP23:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP93]] |
| ; CHECK-NEXT: [[NEXT_GEP24:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP94]] |
| ; CHECK-NEXT: [[NEXT_GEP25:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP95]] |
| ; CHECK-NEXT: [[NEXT_GEP26:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP96]] |
| ; CHECK-NEXT: [[NEXT_GEP27:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP97]] |
| ; CHECK-NEXT: [[TMP98:%.*]] = load i8, ptr [[NEXT_GEP20]], align 1 |
| ; CHECK-NEXT: [[TMP99:%.*]] = load i8, ptr [[NEXT_GEP21]], align 1 |
| ; CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[NEXT_GEP22]], align 1 |
| ; CHECK-NEXT: [[TMP101:%.*]] = load i8, ptr [[NEXT_GEP23]], align 1 |
| ; CHECK-NEXT: [[TMP102:%.*]] = load i8, ptr [[NEXT_GEP24]], align 1 |
| ; CHECK-NEXT: [[TMP103:%.*]] = load i8, ptr [[NEXT_GEP25]], align 1 |
| ; CHECK-NEXT: [[TMP104:%.*]] = load i8, ptr [[NEXT_GEP26]], align 1 |
| ; CHECK-NEXT: [[TMP105:%.*]] = load i8, ptr [[NEXT_GEP27]], align 1 |
| ; CHECK-NEXT: [[TMP106:%.*]] = insertelement <8 x i8> poison, i8 [[TMP98]], i64 0 |
| ; CHECK-NEXT: [[TMP107:%.*]] = insertelement <8 x i8> [[TMP106]], i8 [[TMP99]], i64 1 |
| ; CHECK-NEXT: [[TMP108:%.*]] = insertelement <8 x i8> [[TMP107]], i8 [[TMP100]], i64 2 |
| ; CHECK-NEXT: [[TMP109:%.*]] = insertelement <8 x i8> [[TMP108]], i8 [[TMP101]], i64 3 |
| ; CHECK-NEXT: [[TMP110:%.*]] = insertelement <8 x i8> [[TMP109]], i8 [[TMP102]], i64 4 |
| ; CHECK-NEXT: [[TMP111:%.*]] = insertelement <8 x i8> [[TMP110]], i8 [[TMP103]], i64 5 |
| ; CHECK-NEXT: [[TMP112:%.*]] = insertelement <8 x i8> [[TMP111]], i8 [[TMP104]], i64 6 |
| ; CHECK-NEXT: [[TMP113:%.*]] = insertelement <8 x i8> [[TMP112]], i8 [[TMP105]], i64 7 |
| ; CHECK-NEXT: [[TMP114:%.*]] = zext <8 x i8> [[TMP113]] to <8 x i32> |
| ; CHECK-NEXT: [[TMP115:%.*]] = extractelement <8 x i32> [[TMP114]], i64 7 |
| ; CHECK-NEXT: store i32 [[TMP115]], ptr [[DST]], align 4 |
| ; CHECK-NEXT: [[TMP116:%.*]] = getelementptr i8, ptr [[NEXT_GEP20]], i64 3 |
| ; CHECK-NEXT: [[TMP117:%.*]] = getelementptr i8, ptr [[NEXT_GEP21]], i64 3 |
| ; CHECK-NEXT: [[TMP118:%.*]] = getelementptr i8, ptr [[NEXT_GEP22]], i64 3 |
| ; CHECK-NEXT: [[TMP119:%.*]] = getelementptr i8, ptr [[NEXT_GEP23]], i64 3 |
| ; CHECK-NEXT: [[TMP120:%.*]] = getelementptr i8, ptr [[NEXT_GEP24]], i64 3 |
| ; CHECK-NEXT: [[TMP121:%.*]] = getelementptr i8, ptr [[NEXT_GEP25]], i64 3 |
| ; CHECK-NEXT: [[TMP122:%.*]] = getelementptr i8, ptr [[NEXT_GEP26]], i64 3 |
| ; CHECK-NEXT: [[TMP123:%.*]] = getelementptr i8, ptr [[NEXT_GEP27]], i64 3 |
| ; CHECK-NEXT: [[TMP124:%.*]] = insertelement <8 x ptr> poison, ptr [[TMP116]], i64 0 |
| ; CHECK-NEXT: [[TMP125:%.*]] = insertelement <8 x ptr> [[TMP124]], ptr [[TMP117]], i64 1 |
| ; CHECK-NEXT: [[TMP126:%.*]] = insertelement <8 x ptr> [[TMP125]], ptr [[TMP118]], i64 2 |
| ; CHECK-NEXT: [[TMP127:%.*]] = insertelement <8 x ptr> [[TMP126]], ptr [[TMP119]], i64 3 |
| ; CHECK-NEXT: [[TMP128:%.*]] = insertelement <8 x ptr> [[TMP127]], ptr [[TMP120]], i64 4 |
| ; CHECK-NEXT: [[TMP129:%.*]] = insertelement <8 x ptr> [[TMP128]], ptr [[TMP121]], i64 5 |
| ; CHECK-NEXT: [[TMP130:%.*]] = insertelement <8 x ptr> [[TMP129]], ptr [[TMP122]], i64 6 |
| ; CHECK-NEXT: [[TMP131:%.*]] = insertelement <8 x ptr> [[TMP130]], ptr [[TMP123]], i64 7 |
| ; CHECK-NEXT: [[INDEX_NEXT28]] = add nuw i64 [[INDEX19]], 8 |
| ; CHECK-NEXT: [[TMP132:%.*]] = icmp eq i64 [[INDEX_NEXT28]], [[N_VEC18]] |
| ; CHECK-NEXT: br i1 [[TMP132]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP28:![0-9]+]] |
| ; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[TMP133:%.*]] = ptrtoint <8 x ptr> [[TMP131]] to <8 x i64> |
| ; CHECK-NEXT: [[TMP134:%.*]] = extractelement <8 x i64> [[TMP133]], i64 7 |
| ; CHECK-NEXT: [[CMP_N29:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC18]] |
| ; CHECK-NEXT: br i1 [[CMP_N29]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] |
| ; CHECK: [[VEC_EPILOG_SCALAR_PH]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL29:%.*]] = phi i64 [ [[N_VEC18]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL30:%.*]] = phi ptr [ [[TMP89]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP2]], %[[VEC_EPILOG_ITER_CHECK]] ], [ [[START]], %[[ITER_CHECK]] ] |
| ; CHECK-NEXT: br label %[[LOOP:.*]] |
| ; CHECK: [[LOOP]]: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL29]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL30]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[VAL:%.*]] = load i8, ptr [[PTR_IV]], align 1 |
| ; CHECK-NEXT: [[VAL_EXT:%.*]] = zext i8 [[VAL]] to i32 |
| ; CHECK-NEXT: store i32 [[VAL_EXT]], ptr [[DST]], align 4 |
| ; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 3 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[PTR_INT:%.*]] = ptrtoint ptr [[PTR_IV_NEXT]] to i64 |
| ; CHECK-NEXT: [[EC:%.*]] = icmp ult i64 [[IV]], [[COUNT]] |
| ; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP29:![0-9]+]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: [[PTR_INT_LCSSA:%.*]] = phi i64 [ [[PTR_INT]], %[[LOOP]] ], [ [[TMP87]], %[[MIDDLE_BLOCK]] ], [ [[TMP134]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ] |
| ; CHECK-NEXT: ret i64 [[PTR_INT_LCSSA]] |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop ] |
| %val = load i8, ptr %ptr.iv, align 1 |
| %val.ext = zext i8 %val to i32 |
| store i32 %val.ext, ptr %dst, align 4 |
| %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 3 |
| %iv.next = add i64 %iv, 1 |
| %ptr.int = ptrtoint ptr %ptr.iv.next to i64 |
| %ec = icmp ult i64 %iv, %count |
| br i1 %ec, label %loop, label %exit |
| |
| exit: |
| ret i64 %ptr.int |
| } |
| |
| define i32 @scev_usub_sat_n_2(ptr %ptr, i32 %n) { |
| ; CHECK-LABEL: define i32 @scev_usub_sat_n_2( |
| ; CHECK-SAME: ptr [[PTR:%.*]], i32 [[N:%.*]]) { |
| ; CHECK-NEXT: [[ENTRY:.*]]: |
| ; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[N]], i32 2) |
| ; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[UMAX]] to i64 |
| ; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[WIDE_TRIP_COUNT]], -1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 12 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]] |
| ; CHECK: [[VECTOR_SCEVCHECK]]: |
| ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[N]] to i64 |
| ; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[TMP1]], i64 2) |
| ; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i30 |
| ; CHECK-NEXT: [[TMP4:%.*]] = add i30 1, [[TMP3]] |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i30 [[TMP4]], 1 |
| ; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[TMP2]], 1073741823 |
| ; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]] |
| ; CHECK-NEXT: br i1 [[TMP7]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[TMP8:%.*]] = and i64 [[TMP0]], 7 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP8]] |
| ; CHECK-NEXT: [[TMP9:%.*]] = add i64 1, [[N_VEC]] |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP10:%.*]] = add i64 1, [[INDEX]] |
| ; CHECK-NEXT: [[TMP11:%.*]] = shl i64 [[TMP10]], 2 |
| ; CHECK-NEXT: [[TMP12:%.*]] = and i64 [[TMP11]], 4294967292 |
| ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[TMP12]] |
| ; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP13]], i64 4 |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP14]], align 1 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 |
| ; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP30:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i64 3 |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; CHECK: [[SCALAR_PH]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 1, %[[ENTRY]] ], [ 1, %[[VECTOR_SCEVCHECK]] ] |
| ; CHECK-NEXT: br label %[[LOOP:.*]] |
| ; CHECK: [[LOOP]]: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[IV]], 2 |
| ; CHECK-NEXT: [[AND:%.*]] = and i64 [[SHL]], 4294967292 |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[AND]] |
| ; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr [[GEP]], align 1 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], [[WIDE_TRIP_COUNT]] |
| ; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP31:![0-9]+]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: [[LOAD_LCSSA:%.*]] = phi i32 [ [[LOAD]], %[[LOOP]] ], [ [[TMP16]], %[[MIDDLE_BLOCK]] ] |
| ; CHECK-NEXT: ret i32 [[LOAD_LCSSA]] |
| ; |
| entry: |
| %umax = call i32 @llvm.umax.i32(i32 %n, i32 2) |
| %wide.trip.count = zext i32 %umax to i64 |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 1, %entry ], [ %iv.next, %loop ] |
| %shl = shl i64 %iv, 2 |
| %and = and i64 %shl, 4294967292 |
| %gep = getelementptr i8, ptr %ptr, i64 %and |
| %load = load i32, ptr %gep, align 1 |
| %iv.next = add i64 %iv, 1 |
| %exitcond = icmp eq i64 %iv.next, %wide.trip.count |
| br i1 %exitcond, label %exit, label %loop |
| |
| exit: |
| ret i32 %load |
| } |
| |
| attributes #0 = { "target-cpu"="neoverse-v2" } |
