llvm/test/Transforms/InstCombine/divceil.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S | FileCheck %s

; Optimizes div_ceil idioms:
;   same-type form: add(udiv(X, Y), zext(icmp ne(urem(X, Y), 0)))
;     -> udiv(add nuw(X, Y - 1), Y)
;   zext form: add(zext(udiv(X, Y)), zext(icmp ne(urem(X, Y), 0)))
;     -> zext(udiv(add nuw(X, Y - 1), Y))
; when X + (Y-1) is provably non-wrapping (via range info on both X and Y).

declare void @use(i8)
declare void @use16(i16)

; Variable divisor: both X in [0,100] and Y in [1,10], so max X+(Y-1) = 109 <= 255.
define i8 @divceil_i8_var_divisor(i8 range(i8 0, 101) %x, i8 range(i8 1, 11) %y) {
; CHECK-LABEL: @divceil_i8_var_divisor(
; CHECK-NEXT:    [[ROUND:%.*]] = add nsw i8 [[Y:%.*]], -1
; CHECK-NEXT:    [[RESULT1:%.*]] = add nuw i8 [[RESULT:%.*]], [[ROUND]]
; CHECK-NEXT:    [[RESULT2:%.*]] = udiv i8 [[RESULT1]], [[Y]]
; CHECK-NEXT:    ret i8 [[RESULT2]]
;
  %q = udiv i8 %x, %y
  %r = urem i8 %x, %y
  %cond = icmp ne i8 %r, 0
  %round = zext i1 %cond to i8
  %result = add i8 %q, %round
  ret i8 %result
}

; Variable divisor, commuted add.
define i8 @divceil_i8_var_divisor_commuted(i8 range(i8 0, 101) %x, i8 range(i8 1, 11) %y) {
; CHECK-LABEL: @divceil_i8_var_divisor_commuted(
; CHECK-NEXT:    [[ROUND:%.*]] = add nsw i8 [[Y:%.*]], -1
; CHECK-NEXT:    [[RESULT1:%.*]] = add nuw i8 [[RESULT:%.*]], [[ROUND]]
; CHECK-NEXT:    [[RESULT2:%.*]] = udiv i8 [[RESULT1]], [[Y]]
; CHECK-NEXT:    ret i8 [[RESULT2]]
;
  %q = udiv i8 %x, %y
  %r = urem i8 %x, %y
  %cond = icmp ne i8 %r, 0
  %round = zext i1 %cond to i8
  %result = add i8 %round, %q
  ret i8 %result
}

; Variable divisor with i32: X in [0, 100], Y in [2, 8], max X+(Y-1) = 107 <= UINT32_MAX.
define i32 @divceil_i32_var_divisor(i32 range(i32 0, 101) %x, i32 range(i32 2, 9) %y) {
; CHECK-LABEL: @divceil_i32_var_divisor(
; CHECK-NEXT:    [[ROUND:%.*]] = add nsw i32 [[Y:%.*]], -1
; CHECK-NEXT:    [[RESULT1:%.*]] = add nuw nsw i32 [[RESULT:%.*]], [[ROUND]]
; CHECK-NEXT:    [[RESULT2:%.*]] = udiv i32 [[RESULT1]], [[Y]]
; CHECK-NEXT:    ret i32 [[RESULT2]]
;
  %q = udiv i32 %x, %y
  %r = urem i32 %x, %y
  %cond = icmp ne i32 %r, 0
  %round = zext i1 %cond to i32
  %result = add i32 %q, %round
  ret i32 %result
}

; Negative: Y unbounded -> max Y = 255, max X+(Y-1) = 100+254 overflows i8.
define i8 @divceil_i8_var_divisor_y_unbounded(i8 range(i8 0, 101) %x, i8 %y) {
; CHECK-LABEL: @divceil_i8_var_divisor_y_unbounded(
; CHECK-NEXT:    [[Q:%.*]] = udiv i8 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT:    [[R:%.*]] = urem i8 [[X]], [[Y]]
; CHECK-NEXT:    [[COND:%.*]] = icmp ne i8 [[R]], 0
; CHECK-NEXT:    [[ROUND:%.*]] = zext i1 [[COND]] to i8
; CHECK-NEXT:    [[RESULT:%.*]] = add nuw i8 [[Q]], [[ROUND]]
; CHECK-NEXT:    ret i8 [[RESULT]]
;
  %q = udiv i8 %x, %y
  %r = urem i8 %x, %y
  %cond = icmp ne i8 %r, 0
  %round = zext i1 %cond to i8
  %result = add i8 %q, %round
  ret i8 %result
}

; Negative: X unbounded -> max X+(Y-1) overflows even with bounded Y.
define i8 @divceil_i8_var_divisor_x_unbounded(i8 %x, i8 range(i8 1, 11) %y) {
; CHECK-LABEL: @divceil_i8_var_divisor_x_unbounded(
; CHECK-NEXT:    [[Q:%.*]] = udiv i8 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT:    [[R:%.*]] = urem i8 [[X]], [[Y]]
; CHECK-NEXT:    [[COND:%.*]] = icmp ne i8 [[R]], 0
; CHECK-NEXT:    [[ROUND:%.*]] = zext i1 [[COND]] to i8
; CHECK-NEXT:    [[RESULT:%.*]] = add i8 [[Q]], [[ROUND]]
; CHECK-NEXT:    ret i8 [[RESULT]]
;
  %q = udiv i8 %x, %y
  %r = urem i8 %x, %y
  %cond = icmp ne i8 %r, 0
  %round = zext i1 %cond to i8
  %result = add i8 %q, %round
  ret i8 %result
}

; Zext form: udiv/urem in i8, add in i16.
; X in [0,100], Y in [1,10]: max X+(Y-1) = 109 <= 255.
define i16 @divceil_i8_var_divisor_zext(i8 range(i8 0, 101) %x, i8 range(i8 1, 11) %y) {
; CHECK-LABEL: @divceil_i8_var_divisor_zext(
; CHECK-NEXT:    [[TMP1:%.*]] = add nsw i8 [[Y:%.*]], -1
; CHECK-NEXT:    [[TMP2:%.*]] = add nuw i8 [[X:%.*]], [[TMP1]]
; CHECK-NEXT:    [[TMP3:%.*]] = udiv i8 [[TMP2]], [[Y]]
; CHECK-NEXT:    [[RESULT:%.*]] = zext i8 [[TMP3]] to i16
; CHECK-NEXT:    ret i16 [[RESULT]]
;
  %q = udiv i8 %x, %y
  %r = urem i8 %x, %y
  %cond = icmp ne i8 %r, 0
  %q_ext = zext i8 %q to i16
  %round = zext i1 %cond to i16
  %result = add i16 %q_ext, %round
  ret i16 %result
}

; Zext form, commuted add.
define i16 @divceil_i8_var_divisor_commuted_zext(i8 range(i8 0, 101) %x, i8 range(i8 1, 11) %y) {
; CHECK-LABEL: @divceil_i8_var_divisor_commuted_zext(
; CHECK-NEXT:    [[TMP1:%.*]] = add nsw i8 [[Y:%.*]], -1
; CHECK-NEXT:    [[TMP2:%.*]] = add nuw i8 [[X:%.*]], [[TMP1]]
; CHECK-NEXT:    [[TMP3:%.*]] = udiv i8 [[TMP2]], [[Y]]
; CHECK-NEXT:    [[RESULT:%.*]] = zext i8 [[TMP3]] to i16
; CHECK-NEXT:    ret i16 [[RESULT]]
;
  %q = udiv i8 %x, %y
  %r = urem i8 %x, %y
  %cond = icmp ne i8 %r, 0
  %q_ext = zext i8 %q to i16
  %round = zext i1 %cond to i16
  %result = add i16 %round, %q_ext
  ret i16 %result
}

; Zext form with i16->i32: X in [0, 100], Y in [2, 8].
define i32 @divceil_i16_var_divisor_zext(i16 range(i16 0, 101) %x, i16 range(i16 2, 9) %y) {
; CHECK-LABEL: @divceil_i16_var_divisor_zext(
; CHECK-NEXT:    [[TMP1:%.*]] = add nsw i16 [[Y:%.*]], -1
; CHECK-NEXT:    [[TMP2:%.*]] = add nuw nsw i16 [[X:%.*]], [[TMP1]]
; CHECK-NEXT:    [[TMP3:%.*]] = udiv i16 [[TMP2]], [[Y]]
; CHECK-NEXT:    [[RESULT:%.*]] = zext i16 [[TMP3]] to i32
; CHECK-NEXT:    ret i32 [[RESULT]]
;
  %q = udiv i16 %x, %y
  %r = urem i16 %x, %y
  %cond = icmp ne i16 %r, 0
  %q_ext = zext i16 %q to i32
  %round = zext i1 %cond to i32
  %result = add i32 %q_ext, %round
  ret i32 %result
}

; Zext form negative: Y unbounded -> overflows in i8 type.
define i16 @divceil_i8_var_divisor_y_unbounded_zext(i8 range(i8 0, 101) %x, i8 %y) {
; CHECK-LABEL: @divceil_i8_var_divisor_y_unbounded_zext(
; CHECK-NEXT:    [[Q:%.*]] = udiv i8 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT:    [[R:%.*]] = urem i8 [[X]], [[Y]]
; CHECK-NEXT:    [[COND:%.*]] = icmp ne i8 [[R]], 0
; CHECK-NEXT:    [[Q_EXT:%.*]] = zext nneg i8 [[Q]] to i16
; CHECK-NEXT:    [[ROUND:%.*]] = zext i1 [[COND]] to i16
; CHECK-NEXT:    [[RESULT:%.*]] = add nuw nsw i16 [[Q_EXT]], [[ROUND]]
; CHECK-NEXT:    ret i16 [[RESULT]]
;
  %q = udiv i8 %x, %y
  %r = urem i8 %x, %y
  %cond = icmp ne i8 %r, 0
  %q_ext = zext i8 %q to i16
  %round = zext i1 %cond to i16
  %result = add i16 %q_ext, %round
  ret i16 %result
}

; Zext form negative: X unbounded -> overflows even with bounded Y.
define i16 @divceil_i8_var_divisor_x_unbounded_zext(i8 %x, i8 range(i8 1, 11) %y) {
; CHECK-LABEL: @divceil_i8_var_divisor_x_unbounded_zext(
; CHECK-NEXT:    [[Q:%.*]] = udiv i8 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT:    [[R:%.*]] = urem i8 [[X]], [[Y]]
; CHECK-NEXT:    [[COND:%.*]] = icmp ne i8 [[R]], 0
; CHECK-NEXT:    [[Q_EXT:%.*]] = zext i8 [[Q]] to i16
; CHECK-NEXT:    [[ROUND:%.*]] = zext i1 [[COND]] to i16
; CHECK-NEXT:    [[RESULT:%.*]] = add nuw nsw i16 [[Q_EXT]], [[ROUND]]
; CHECK-NEXT:    ret i16 [[RESULT]]
;
  %q = udiv i8 %x, %y
  %r = urem i8 %x, %y
  %cond = icmp ne i8 %r, 0
  %q_ext = zext i8 %q to i16
  %round = zext i1 %cond to i16
  %result = add i16 %q_ext, %round
  ret i16 %result
}

; Trunc form: X comes from trunc nuw of an i32 with range info.
define i32 @divceil_trunc_nuw_range(i32 range(i32 0, 33) %x_wide) {
; CHECK-LABEL: @divceil_trunc_nuw_range(
; CHECK-NEXT:    [[X:%.*]] = trunc nuw nsw i32 [[X_WIDE:%.*]] to i8
; CHECK-NEXT:    [[TMP1:%.*]] = add nuw nsw i8 [[X]], 6
; CHECK-NEXT:    [[Q:%.*]] = udiv i8 [[TMP1]], 7
; CHECK-NEXT:    [[Q_EXT:%.*]] = zext nneg i8 [[Q]] to i32
; CHECK-NEXT:    ret i32 [[Q_EXT]]
;
  %x = trunc nuw i32 %x_wide to i8
  %q = udiv i8 %x, 7
  %r = urem i8 %x, 7
  %cond = icmp ne i8 %r, 0
  %q_ext = zext i8 %q to i32
  %round = zext i1 %cond to i32
  %result = add i32 %q_ext, %round
  ret i32 %result
}