llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=wasm32 -mattr=-simd128 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=NO-SIMD
; RUN: llc -mtriple=wasm32 -mattr=+simd128,-fp16 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=SIMD,SIMD-NO-F16
; RUN: llc -mtriple=wasm32 -mattr=+simd128,+fp16 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=SIMD,SIMD-F16

define void @test_v16i8_arg(<16 x i8> %arg) {
  ; NO-SIMD-LABEL: name: test_v16i8_arg
  ; NO-SIMD: bb.1 (%ir-block.0):
  ; NO-SIMD-NEXT:   liveins: $arguments
  ; NO-SIMD-NEXT: {{  $}}
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_:%[0-9]+]]:i32(i32) = ARGUMENT_i32 0, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_1:%[0-9]+]]:i32(i32) = ARGUMENT_i32 1, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_2:%[0-9]+]]:i32(i32) = ARGUMENT_i32 2, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_3:%[0-9]+]]:i32(i32) = ARGUMENT_i32 3, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_4:%[0-9]+]]:i32(i32) = ARGUMENT_i32 4, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_5:%[0-9]+]]:i32(i32) = ARGUMENT_i32 5, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_6:%[0-9]+]]:i32(i32) = ARGUMENT_i32 6, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_7:%[0-9]+]]:i32(i32) = ARGUMENT_i32 7, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_8:%[0-9]+]]:i32(i32) = ARGUMENT_i32 8, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_9:%[0-9]+]]:i32(i32) = ARGUMENT_i32 9, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_10:%[0-9]+]]:i32(i32) = ARGUMENT_i32 10, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_11:%[0-9]+]]:i32(i32) = ARGUMENT_i32 11, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_12:%[0-9]+]]:i32(i32) = ARGUMENT_i32 12, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_13:%[0-9]+]]:i32(i32) = ARGUMENT_i32 13, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_14:%[0-9]+]]:i32(i32) = ARGUMENT_i32 14, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_15:%[0-9]+]]:i32(i32) = ARGUMENT_i32 15, implicit $arguments
  ; NO-SIMD-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<16 x i32>) = G_BUILD_VECTOR [[ARGUMENT_i32_]](i32), [[ARGUMENT_i32_1]](i32), [[ARGUMENT_i32_2]](i32), [[ARGUMENT_i32_3]](i32), [[ARGUMENT_i32_4]](i32), [[ARGUMENT_i32_5]](i32), [[ARGUMENT_i32_6]](i32), [[ARGUMENT_i32_7]](i32), [[ARGUMENT_i32_8]](i32), [[ARGUMENT_i32_9]](i32), [[ARGUMENT_i32_10]](i32), [[ARGUMENT_i32_11]](i32), [[ARGUMENT_i32_12]](i32), [[ARGUMENT_i32_13]](i32), [[ARGUMENT_i32_14]](i32), [[ARGUMENT_i32_15]](i32)
  ; NO-SIMD-NEXT:   [[TRUNC:%[0-9]+]]:_(<16 x i8>) = G_TRUNC [[BUILD_VECTOR]](<16 x i32>)
  ; NO-SIMD-NEXT:   RETURN implicit-def $arguments
  ;
  ; SIMD-LABEL: name: test_v16i8_arg
  ; SIMD: bb.1 (%ir-block.0):
  ; SIMD-NEXT:   liveins: $arguments
  ; SIMD-NEXT: {{  $}}
  ; SIMD-NEXT:   [[ARGUMENT_v16i8_:%[0-9]+]]:v128(<16 x i8>) = ARGUMENT_v16i8 0, implicit $arguments
  ; SIMD-NEXT:   RETURN implicit-def $arguments
  ret void
}

define void @test_v8i16_arg(<8 x i16> %arg) {
  ; NO-SIMD-LABEL: name: test_v8i16_arg
  ; NO-SIMD: bb.1 (%ir-block.0):
  ; NO-SIMD-NEXT:   liveins: $arguments
  ; NO-SIMD-NEXT: {{  $}}
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_:%[0-9]+]]:i32(i32) = ARGUMENT_i32 0, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_1:%[0-9]+]]:i32(i32) = ARGUMENT_i32 1, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_2:%[0-9]+]]:i32(i32) = ARGUMENT_i32 2, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_3:%[0-9]+]]:i32(i32) = ARGUMENT_i32 3, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_4:%[0-9]+]]:i32(i32) = ARGUMENT_i32 4, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_5:%[0-9]+]]:i32(i32) = ARGUMENT_i32 5, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_6:%[0-9]+]]:i32(i32) = ARGUMENT_i32 6, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_7:%[0-9]+]]:i32(i32) = ARGUMENT_i32 7, implicit $arguments
  ; NO-SIMD-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[ARGUMENT_i32_]](i32), [[ARGUMENT_i32_1]](i32), [[ARGUMENT_i32_2]](i32), [[ARGUMENT_i32_3]](i32), [[ARGUMENT_i32_4]](i32), [[ARGUMENT_i32_5]](i32), [[ARGUMENT_i32_6]](i32), [[ARGUMENT_i32_7]](i32)
  ; NO-SIMD-NEXT:   [[TRUNC:%[0-9]+]]:_(<8 x i16>) = G_TRUNC [[BUILD_VECTOR]](<8 x i32>)
  ; NO-SIMD-NEXT:   RETURN implicit-def $arguments
  ;
  ; SIMD-LABEL: name: test_v8i16_arg
  ; SIMD: bb.1 (%ir-block.0):
  ; SIMD-NEXT:   liveins: $arguments
  ; SIMD-NEXT: {{  $}}
  ; SIMD-NEXT:   [[ARGUMENT_v8i16_:%[0-9]+]]:v128(<8 x i16>) = ARGUMENT_v8i16 0, implicit $arguments
  ; SIMD-NEXT:   RETURN implicit-def $arguments
  ret void
}

define void @test_v4i32_arg(<4 x i32> %arg) {
  ; NO-SIMD-LABEL: name: test_v4i32_arg
  ; NO-SIMD: bb.1 (%ir-block.0):
  ; NO-SIMD-NEXT:   liveins: $arguments
  ; NO-SIMD-NEXT: {{  $}}
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_:%[0-9]+]]:i32(i32) = ARGUMENT_i32 0, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_1:%[0-9]+]]:i32(i32) = ARGUMENT_i32 1, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_2:%[0-9]+]]:i32(i32) = ARGUMENT_i32 2, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_3:%[0-9]+]]:i32(i32) = ARGUMENT_i32 3, implicit $arguments
  ; NO-SIMD-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[ARGUMENT_i32_]](i32), [[ARGUMENT_i32_1]](i32), [[ARGUMENT_i32_2]](i32), [[ARGUMENT_i32_3]](i32)
  ; NO-SIMD-NEXT:   RETURN implicit-def $arguments
  ;
  ; SIMD-LABEL: name: test_v4i32_arg
  ; SIMD: bb.1 (%ir-block.0):
  ; SIMD-NEXT:   liveins: $arguments
  ; SIMD-NEXT: {{  $}}
  ; SIMD-NEXT:   [[ARGUMENT_v4i32_:%[0-9]+]]:v128(<4 x i32>) = ARGUMENT_v4i32 0, implicit $arguments
  ; SIMD-NEXT:   RETURN implicit-def $arguments
  ret void
}

define void @test_v2i64_arg(<2 x i64> %arg) {
  ; NO-SIMD-LABEL: name: test_v2i64_arg
  ; NO-SIMD: bb.1 (%ir-block.0):
  ; NO-SIMD-NEXT:   liveins: $arguments
  ; NO-SIMD-NEXT: {{  $}}
  ; NO-SIMD-NEXT:   [[ARGUMENT_i64_:%[0-9]+]]:i64(i64) = ARGUMENT_i64 0, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i64_1:%[0-9]+]]:i64(i64) = ARGUMENT_i64 1, implicit $arguments
  ; NO-SIMD-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[ARGUMENT_i64_]](i64), [[ARGUMENT_i64_1]](i64)
  ; NO-SIMD-NEXT:   RETURN implicit-def $arguments
  ;
  ; SIMD-LABEL: name: test_v2i64_arg
  ; SIMD: bb.1 (%ir-block.0):
  ; SIMD-NEXT:   liveins: $arguments
  ; SIMD-NEXT: {{  $}}
  ; SIMD-NEXT:   [[ARGUMENT_v2i64_:%[0-9]+]]:v128(<2 x i64>) = ARGUMENT_v2i64 0, implicit $arguments
  ; SIMD-NEXT:   RETURN implicit-def $arguments
  ret void
}

define void @test_v8f16_arg(<8 x half> %arg) {
  ; NO-SIMD-LABEL: name: test_v8f16_arg
  ; NO-SIMD: bb.1 (%ir-block.0):
  ; NO-SIMD-NEXT:   liveins: $arguments
  ; NO-SIMD-NEXT: {{  $}}
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_:%[0-9]+]]:i32(i32) = ARGUMENT_i32 0, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_1:%[0-9]+]]:i32(i32) = ARGUMENT_i32 1, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_2:%[0-9]+]]:i32(i32) = ARGUMENT_i32 2, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_3:%[0-9]+]]:i32(i32) = ARGUMENT_i32 3, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_4:%[0-9]+]]:i32(i32) = ARGUMENT_i32 4, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_5:%[0-9]+]]:i32(i32) = ARGUMENT_i32 5, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_6:%[0-9]+]]:i32(i32) = ARGUMENT_i32 6, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_i32_7:%[0-9]+]]:i32(i32) = ARGUMENT_i32 7, implicit $arguments
  ; NO-SIMD-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[ARGUMENT_i32_]](i32), [[ARGUMENT_i32_1]](i32), [[ARGUMENT_i32_2]](i32), [[ARGUMENT_i32_3]](i32), [[ARGUMENT_i32_4]](i32), [[ARGUMENT_i32_5]](i32), [[ARGUMENT_i32_6]](i32), [[ARGUMENT_i32_7]](i32)
  ; NO-SIMD-NEXT:   [[TRUNC:%[0-9]+]]:_(<8 x f16>) = G_TRUNC [[BUILD_VECTOR]](<8 x i32>)
  ; NO-SIMD-NEXT:   RETURN implicit-def $arguments
  ;
  ; SIMD-NO-F16-LABEL: name: test_v8f16_arg
  ; SIMD-NO-F16: bb.1 (%ir-block.0):
  ; SIMD-NO-F16-NEXT:   liveins: $arguments
  ; SIMD-NO-F16-NEXT: {{  $}}
  ; SIMD-NO-F16-NEXT:   [[ARGUMENT_i32_:%[0-9]+]]:i32(i32) = ARGUMENT_i32 0, implicit $arguments
  ; SIMD-NO-F16-NEXT:   [[ARGUMENT_i32_1:%[0-9]+]]:i32(i32) = ARGUMENT_i32 1, implicit $arguments
  ; SIMD-NO-F16-NEXT:   [[ARGUMENT_i32_2:%[0-9]+]]:i32(i32) = ARGUMENT_i32 2, implicit $arguments
  ; SIMD-NO-F16-NEXT:   [[ARGUMENT_i32_3:%[0-9]+]]:i32(i32) = ARGUMENT_i32 3, implicit $arguments
  ; SIMD-NO-F16-NEXT:   [[ARGUMENT_i32_4:%[0-9]+]]:i32(i32) = ARGUMENT_i32 4, implicit $arguments
  ; SIMD-NO-F16-NEXT:   [[ARGUMENT_i32_5:%[0-9]+]]:i32(i32) = ARGUMENT_i32 5, implicit $arguments
  ; SIMD-NO-F16-NEXT:   [[ARGUMENT_i32_6:%[0-9]+]]:i32(i32) = ARGUMENT_i32 6, implicit $arguments
  ; SIMD-NO-F16-NEXT:   [[ARGUMENT_i32_7:%[0-9]+]]:i32(i32) = ARGUMENT_i32 7, implicit $arguments
  ; SIMD-NO-F16-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[ARGUMENT_i32_]](i32), [[ARGUMENT_i32_1]](i32), [[ARGUMENT_i32_2]](i32), [[ARGUMENT_i32_3]](i32), [[ARGUMENT_i32_4]](i32), [[ARGUMENT_i32_5]](i32), [[ARGUMENT_i32_6]](i32), [[ARGUMENT_i32_7]](i32)
  ; SIMD-NO-F16-NEXT:   [[TRUNC:%[0-9]+]]:_(<8 x f16>) = G_TRUNC [[BUILD_VECTOR]](<8 x i32>)
  ; SIMD-NO-F16-NEXT:   RETURN implicit-def $arguments
  ;
  ; SIMD-F16-LABEL: name: test_v8f16_arg
  ; SIMD-F16: bb.1 (%ir-block.0):
  ; SIMD-F16-NEXT:   liveins: $arguments
  ; SIMD-F16-NEXT: {{  $}}
  ; SIMD-F16-NEXT:   [[ARGUMENT_v8f16_:%[0-9]+]]:v128(<8 x f16>) = ARGUMENT_v8f16 0, implicit $arguments
  ; SIMD-F16-NEXT:   RETURN implicit-def $arguments
  ret void
}

define void @test_v4f32_arg(<4 x float> %arg) {
  ; NO-SIMD-LABEL: name: test_v4f32_arg
  ; NO-SIMD: bb.1 (%ir-block.0):
  ; NO-SIMD-NEXT:   liveins: $arguments
  ; NO-SIMD-NEXT: {{  $}}
  ; NO-SIMD-NEXT:   [[ARGUMENT_f32_:%[0-9]+]]:f32(f32) = ARGUMENT_f32 0, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_f32_1:%[0-9]+]]:f32(f32) = ARGUMENT_f32 1, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_f32_2:%[0-9]+]]:f32(f32) = ARGUMENT_f32 2, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_f32_3:%[0-9]+]]:f32(f32) = ARGUMENT_f32 3, implicit $arguments
  ; NO-SIMD-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[ARGUMENT_f32_]](f32), [[ARGUMENT_f32_1]](f32), [[ARGUMENT_f32_2]](f32), [[ARGUMENT_f32_3]](f32)
  ; NO-SIMD-NEXT:   RETURN implicit-def $arguments
  ;
  ; SIMD-LABEL: name: test_v4f32_arg
  ; SIMD: bb.1 (%ir-block.0):
  ; SIMD-NEXT:   liveins: $arguments
  ; SIMD-NEXT: {{  $}}
  ; SIMD-NEXT:   [[ARGUMENT_v4f32_:%[0-9]+]]:v128(<4 x f32>) = ARGUMENT_v4f32 0, implicit $arguments
  ; SIMD-NEXT:   RETURN implicit-def $arguments
  ret void
}

define void @test_v2f64_arg(<2 x double> %arg) {
  ; NO-SIMD-LABEL: name: test_v2f64_arg
  ; NO-SIMD: bb.1 (%ir-block.0):
  ; NO-SIMD-NEXT:   liveins: $arguments
  ; NO-SIMD-NEXT: {{  $}}
  ; NO-SIMD-NEXT:   [[ARGUMENT_f64_:%[0-9]+]]:f64(f64) = ARGUMENT_f64 0, implicit $arguments
  ; NO-SIMD-NEXT:   [[ARGUMENT_f64_1:%[0-9]+]]:f64(f64) = ARGUMENT_f64 1, implicit $arguments
  ; NO-SIMD-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[ARGUMENT_f64_]](f64), [[ARGUMENT_f64_1]](f64)
  ; NO-SIMD-NEXT:   RETURN implicit-def $arguments
  ;
  ; SIMD-LABEL: name: test_v2f64_arg
  ; SIMD: bb.1 (%ir-block.0):
  ; SIMD-NEXT:   liveins: $arguments
  ; SIMD-NEXT: {{  $}}
  ; SIMD-NEXT:   [[ARGUMENT_v2f64_:%[0-9]+]]:v128(<2 x f64>) = ARGUMENT_v2f64 0, implicit $arguments
  ; SIMD-NEXT:   RETURN implicit-def $arguments
  ret void
}