llvm/test/CodeGen/NVPTX/applypriority-async-bulk-tensor-evict-priority.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_107f | FileCheck %s
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_107f -target-abi=shortptr | FileCheck --check-prefixes=CHECK-PTX-SHARED32 %s
; RUN: llvm-as < %s | llvm-dis | FileCheck --check-prefixes=CHECK-FORMAT %s
; RUN: %if ptxas-sm_107f && ptxas-isa-9.4 %{ llc < %s -march=nvptx64 -mcpu=sm_107f -mattr=+ptx94 | %ptxas-verify -arch=sm_107f %}

; CHECK-FORMAT: declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.1d(ptr readonly, i32, i32 immarg range(i32 0, 1)) #0
; CHECK-FORMAT: declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.gather4.2d(ptr readonly, i32, i32, i32, i32, i32, i32 immarg range(i32 0, 1)) #0
; CHECK-FORMAT: declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.5d(ptr readonly, i32, i32, i32, i32, i32, i16, i16, i16, i32 immarg range(i32 0, 1)) #0
; CHECK-FORMAT: declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.5d(ptr readonly, i32, i32, i32, i32, i32, i16, i16, i32 immarg range(i32 0, 1)) #0
; CHECK-FORMAT: declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.128.5d(ptr readonly, i32, i32, i32, i32, i32, i16, i16, i32 immarg range(i32 0, 1)) #0

target triple = "nvptx64-nvidia-cuda"

declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.1d(ptr, i32, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.2d(ptr, i32, i32, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.3d(ptr, i32, i32, i32, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.4d(ptr, i32, i32, i32, i32, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.5d(ptr, i32, i32, i32, i32, i32, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.gather4.2d(ptr, i32, i32, i32, i32, i32, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.3d(ptr, i32, i32, i32, i16, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.4d(ptr, i32, i32, i32, i32, i16, i16, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.5d(ptr, i32, i32, i32, i32, i32, i16, i16, i16, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.3d(ptr, i32, i32, i32, i16, i16, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.4d(ptr, i32, i32, i32, i32, i16, i16, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.5d(ptr, i32, i32, i32, i32, i32, i16, i16, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.128.3d(ptr, i32, i32, i32, i16, i16, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.128.4d(ptr, i32, i32, i32, i32, i16, i16, i32)
declare void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.128.5d(ptr, i32, i32, i32, i32, i32, i16, i16, i32)

define void @tile(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4) {
; CHECK-LABEL: tile(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<6>;
; CHECK-NEXT:    .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param::func.b64 %rd1, [tile_param_0];
; CHECK-NEXT:    ld.param::func.b32 %r1, [tile_param_1];
; CHECK-NEXT:    applypriority.async.bulk.tensor.1d.global.bulk_group.L2::evict_normal.tile [%rd1, {%r1}];
; CHECK-NEXT:    ld.param::func.b32 %r2, [tile_param_2];
; CHECK-NEXT:    applypriority.async.bulk.tensor.2d.global.bulk_group.L2::evict_normal.tile [%rd1, {%r1, %r2}];
; CHECK-NEXT:    ld.param::func.b32 %r3, [tile_param_3];
; CHECK-NEXT:    applypriority.async.bulk.tensor.3d.global.bulk_group.L2::evict_normal.tile [%rd1, {%r1, %r2, %r3}];
; CHECK-NEXT:    ld.param::func.b32 %r4, [tile_param_4];
; CHECK-NEXT:    applypriority.async.bulk.tensor.4d.global.bulk_group.L2::evict_normal.tile [%rd1, {%r1, %r2, %r3, %r4}];
; CHECK-NEXT:    ld.param::func.b32 %r5, [tile_param_5];
; CHECK-NEXT:    applypriority.async.bulk.tensor.5d.global.bulk_group.L2::evict_normal.tile [%rd1, {%r1, %r2, %r3, %r4, %r5}];
; CHECK-NEXT:    ret;
;
; CHECK-PTX-SHARED32-LABEL: tile(
; CHECK-PTX-SHARED32:       {
; CHECK-PTX-SHARED32-NEXT:    .reg .b32 %r<6>;
; CHECK-PTX-SHARED32-NEXT:    .reg .b64 %rd<2>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT:  // %bb.0:
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b64 %rd1, [tile_param_0];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r1, [tile_param_1];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.1d.global.bulk_group.L2::evict_normal.tile [%rd1, {%r1}];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r2, [tile_param_2];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.2d.global.bulk_group.L2::evict_normal.tile [%rd1, {%r1, %r2}];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r3, [tile_param_3];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.3d.global.bulk_group.L2::evict_normal.tile [%rd1, {%r1, %r2, %r3}];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r4, [tile_param_4];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.4d.global.bulk_group.L2::evict_normal.tile [%rd1, {%r1, %r2, %r3, %r4}];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r5, [tile_param_5];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.5d.global.bulk_group.L2::evict_normal.tile [%rd1, {%r1, %r2, %r3, %r4, %r5}];
; CHECK-PTX-SHARED32-NEXT:    ret;
;
; CHECK-FORMAT-LABEL: define void @tile(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4) {
; CHECK-FORMAT:   tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.1d(ptr %tmap, i32 %d0, /* evict_policy=L2::evict_normal */ i32 0)
; CHECK-FORMAT:   tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.2d(ptr %tmap, i32 %d0, i32 %d1, /* evict_policy=L2::evict_normal */ i32 0)
; CHECK-FORMAT:   tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.5d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, /* evict_policy=L2::evict_normal */ i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.1d(ptr %tmap, i32 %d0, i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.2d(ptr %tmap, i32 %d0, i32 %d1, i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.3d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.4d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.5d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i32 0)
  ret void
}

define void @gather4(ptr %tmap, i32 %x0, i32 %y0, i32 %y1, i32 %y2, i32 %y3) {
; CHECK-LABEL: gather4(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<6>;
; CHECK-NEXT:    .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param::func.b64 %rd1, [gather4_param_0];
; CHECK-NEXT:    ld.param::func.b32 %r1, [gather4_param_1];
; CHECK-NEXT:    ld.param::func.b32 %r2, [gather4_param_2];
; CHECK-NEXT:    ld.param::func.b32 %r3, [gather4_param_3];
; CHECK-NEXT:    ld.param::func.b32 %r4, [gather4_param_4];
; CHECK-NEXT:    ld.param::func.b32 %r5, [gather4_param_5];
; CHECK-NEXT:    applypriority.async.bulk.tensor.2d.global.bulk_group.L2::evict_normal.tile::gather4 [%rd1, {%r1, %r2, %r3, %r4, %r5}];
; CHECK-NEXT:    ret;
;
; CHECK-FORMAT-LABEL: define void @gather4(ptr %tmap, i32 %x0, i32 %y0, i32 %y1, i32 %y2, i32 %y3) {
; CHECK-FORMAT:   tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.gather4.2d(ptr %tmap, i32 %x0, i32 %y0, i32 %y1, i32 %y2, i32 %y3, /* evict_policy=L2::evict_normal */ i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.tile.gather4.2d(ptr %tmap, i32 %x0, i32 %y0, i32 %y1, i32 %y2, i32 %y3, i32 0)
  ret void
}

define void @im2col(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %i0, i16 %i1, i16 %i2) {
; CHECK-LABEL: im2col(
; CHECK:       {
; CHECK-NEXT:    .reg .b16 %rs<4>;
; CHECK-NEXT:    .reg .b32 %r<6>;
; CHECK-NEXT:    .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param::func.b64 %rd1, [im2col_param_0];
; CHECK-NEXT:    ld.param::func.b32 %r1, [im2col_param_1];
; CHECK-NEXT:    ld.param::func.b32 %r2, [im2col_param_2];
; CHECK-NEXT:    ld.param::func.b32 %r3, [im2col_param_3];
; CHECK-NEXT:    ld.param::func.b16 %rs1, [im2col_param_6];
; CHECK-NEXT:    applypriority.async.bulk.tensor.3d.global.bulk_group.L2::evict_normal.im2col [%rd1, {%r1, %r2, %r3}], {%rs1};
; CHECK-NEXT:    ld.param::func.b32 %r4, [im2col_param_4];
; CHECK-NEXT:    ld.param::func.b16 %rs2, [im2col_param_7];
; CHECK-NEXT:    applypriority.async.bulk.tensor.4d.global.bulk_group.L2::evict_normal.im2col [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2};
; CHECK-NEXT:    ld.param::func.b32 %r5, [im2col_param_5];
; CHECK-NEXT:    ld.param::func.b16 %rs3, [im2col_param_8];
; CHECK-NEXT:    applypriority.async.bulk.tensor.5d.global.bulk_group.L2::evict_normal.im2col [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2, %rs3};
; CHECK-NEXT:    ret;
;
; CHECK-PTX-SHARED32-LABEL: im2col(
; CHECK-PTX-SHARED32:       {
; CHECK-PTX-SHARED32-NEXT:    .reg .b16 %rs<4>;
; CHECK-PTX-SHARED32-NEXT:    .reg .b32 %r<6>;
; CHECK-PTX-SHARED32-NEXT:    .reg .b64 %rd<2>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT:  // %bb.0:
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b64 %rd1, [im2col_param_0];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r1, [im2col_param_1];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r2, [im2col_param_2];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r3, [im2col_param_3];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b16 %rs1, [im2col_param_6];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.3d.global.bulk_group.L2::evict_normal.im2col [%rd1, {%r1, %r2, %r3}], {%rs1};
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r4, [im2col_param_4];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b16 %rs2, [im2col_param_7];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.4d.global.bulk_group.L2::evict_normal.im2col [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r5, [im2col_param_5];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b16 %rs3, [im2col_param_8];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.5d.global.bulk_group.L2::evict_normal.im2col [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2, %rs3};
; CHECK-PTX-SHARED32-NEXT:    ret;
;
; CHECK-FORMAT-LABEL: define void @im2col(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %i0, i16 %i1, i16 %i2) {
; CHECK-FORMAT:   tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.3d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i16 %i0, /* evict_policy=L2::evict_normal */ i32 0)
; CHECK-FORMAT:   tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.5d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %i0, i16 %i1, i16 %i2, /* evict_policy=L2::evict_normal */ i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.3d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i16 %i0, i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.4d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i16 %i0, i16 %i1, i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.5d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %i0, i16 %i1, i16 %i2, i32 0)
  ret void
}

define void @im2col_w(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %i0, i16 %i1) {
; CHECK-LABEL: im2col_w(
; CHECK:       {
; CHECK-NEXT:    .reg .b16 %rs<3>;
; CHECK-NEXT:    .reg .b32 %r<6>;
; CHECK-NEXT:    .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param::func.b64 %rd1, [im2col_w_param_0];
; CHECK-NEXT:    ld.param::func.b32 %r1, [im2col_w_param_1];
; CHECK-NEXT:    ld.param::func.b32 %r2, [im2col_w_param_2];
; CHECK-NEXT:    ld.param::func.b32 %r3, [im2col_w_param_3];
; CHECK-NEXT:    ld.param::func.b16 %rs1, [im2col_w_param_6];
; CHECK-NEXT:    ld.param::func.b16 %rs2, [im2col_w_param_7];
; CHECK-NEXT:    applypriority.async.bulk.tensor.3d.global.bulk_group.L2::evict_normal.im2col::w [%rd1, {%r1, %r2, %r3}], {%rs1, %rs2};
; CHECK-NEXT:    ld.param::func.b32 %r4, [im2col_w_param_4];
; CHECK-NEXT:    applypriority.async.bulk.tensor.4d.global.bulk_group.L2::evict_normal.im2col::w [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2};
; CHECK-NEXT:    ld.param::func.b32 %r5, [im2col_w_param_5];
; CHECK-NEXT:    applypriority.async.bulk.tensor.5d.global.bulk_group.L2::evict_normal.im2col::w [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2};
; CHECK-NEXT:    ret;
;
; CHECK-PTX-SHARED32-LABEL: im2col_w(
; CHECK-PTX-SHARED32:       {
; CHECK-PTX-SHARED32-NEXT:    .reg .b16 %rs<3>;
; CHECK-PTX-SHARED32-NEXT:    .reg .b32 %r<6>;
; CHECK-PTX-SHARED32-NEXT:    .reg .b64 %rd<2>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT:  // %bb.0:
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b64 %rd1, [im2col_w_param_0];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r1, [im2col_w_param_1];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r2, [im2col_w_param_2];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r3, [im2col_w_param_3];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b16 %rs1, [im2col_w_param_6];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b16 %rs2, [im2col_w_param_7];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.3d.global.bulk_group.L2::evict_normal.im2col::w [%rd1, {%r1, %r2, %r3}], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r4, [im2col_w_param_4];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.4d.global.bulk_group.L2::evict_normal.im2col::w [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r5, [im2col_w_param_5];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.5d.global.bulk_group.L2::evict_normal.im2col::w [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT:    ret;
;
; CHECK-FORMAT-LABEL: define void @im2col_w(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %i0, i16 %i1) {
; CHECK-FORMAT:   tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.5d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %i0, i16 %i1, /* evict_policy=L2::evict_normal */ i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.3d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i16 %i0, i16 %i1, i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.4d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i16 %i0, i16 %i1, i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.5d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %i0, i16 %i1, i32 0)
  ret void
}

define void @im2col_w_128(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %i0, i16 %i1) {
; CHECK-LABEL: im2col_w_128(
; CHECK:       {
; CHECK-NEXT:    .reg .b16 %rs<3>;
; CHECK-NEXT:    .reg .b32 %r<6>;
; CHECK-NEXT:    .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param::func.b64 %rd1, [im2col_w_128_param_0];
; CHECK-NEXT:    ld.param::func.b32 %r1, [im2col_w_128_param_1];
; CHECK-NEXT:    ld.param::func.b32 %r2, [im2col_w_128_param_2];
; CHECK-NEXT:    ld.param::func.b32 %r3, [im2col_w_128_param_3];
; CHECK-NEXT:    ld.param::func.b16 %rs1, [im2col_w_128_param_6];
; CHECK-NEXT:    ld.param::func.b16 %rs2, [im2col_w_128_param_7];
; CHECK-NEXT:    applypriority.async.bulk.tensor.3d.global.bulk_group.L2::evict_normal.im2col::w::128 [%rd1, {%r1, %r2, %r3}], {%rs1, %rs2};
; CHECK-NEXT:    ld.param::func.b32 %r4, [im2col_w_128_param_4];
; CHECK-NEXT:    applypriority.async.bulk.tensor.4d.global.bulk_group.L2::evict_normal.im2col::w::128 [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2};
; CHECK-NEXT:    ld.param::func.b32 %r5, [im2col_w_128_param_5];
; CHECK-NEXT:    applypriority.async.bulk.tensor.5d.global.bulk_group.L2::evict_normal.im2col::w::128 [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2};
; CHECK-NEXT:    ret;
;
; CHECK-PTX-SHARED32-LABEL: im2col_w_128(
; CHECK-PTX-SHARED32:       {
; CHECK-PTX-SHARED32-NEXT:    .reg .b16 %rs<3>;
; CHECK-PTX-SHARED32-NEXT:    .reg .b32 %r<6>;
; CHECK-PTX-SHARED32-NEXT:    .reg .b64 %rd<2>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT:  // %bb.0:
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b64 %rd1, [im2col_w_128_param_0];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r1, [im2col_w_128_param_1];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r2, [im2col_w_128_param_2];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r3, [im2col_w_128_param_3];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b16 %rs1, [im2col_w_128_param_6];
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b16 %rs2, [im2col_w_128_param_7];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.3d.global.bulk_group.L2::evict_normal.im2col::w::128 [%rd1, {%r1, %r2, %r3}], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r4, [im2col_w_128_param_4];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.4d.global.bulk_group.L2::evict_normal.im2col::w::128 [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT:    ld.param::func.b32 %r5, [im2col_w_128_param_5];
; CHECK-PTX-SHARED32-NEXT:    applypriority.async.bulk.tensor.5d.global.bulk_group.L2::evict_normal.im2col::w::128 [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT:    ret;
;
; CHECK-FORMAT-LABEL: define void @im2col_w_128(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %i0, i16 %i1) {
; CHECK-FORMAT:   tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.128.5d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %i0, i16 %i1, /* evict_policy=L2::evict_normal */ i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.128.3d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i16 %i0, i16 %i1, i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.128.4d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i16 %i0, i16 %i1, i32 0)
  tail call void @llvm.nvvm.applypriority.async.bulk.tensor.evict.priority.im2col.w.128.5d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %i0, i16 %i1, i32 0)
  ret void
}