llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir

# RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -run-pass=amdgpu-lower-vgpr-encoding -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -start-before=amdgpu-lower-vgpr-encoding -o - %s | FileCheck --check-prefix=ASM %s
# RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -start-before=amdgpu-lower-vgpr-encoding -o - %s | llvm-mc -triple=amdgpu12.50-amd-amdhsa -mcpu=gfx1250 -filetype=obj -o - | llvm-objdump -d - | FileCheck --check-prefix=DIS %s

---
# Case 1a: Size < 12 (size=4), imm32[12:19]=0
# S_SET_VGPR_MSB format: (src0_msb[0-1], src1_msb[2-3], src2_msb[4-5], dst_msb[6-7])
# MODE register format:  (dst_msb[0-1], src0_msb[2-3], src1_msb[4-5], src2_msb[6-7])
# vgpr256/257 (both MSB=1): S_SET_VGPR_MSB mode = (1 << 0) | (1 << 6) = 65
#                           MODE register mode = (1 << 0) | (1 << 2) = 5
# New setreg imm = 0x5 | (5 << 12) = 0x5005 = 20485

# ASM-LABEL: {{^}}setreg_size_lt_12:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 4), 0x5005 ;  msbs: dst=1 src0=1 src1=0 src2=0

# DIS-LABEL: <setreg_size_lt_12>:

name:            setreg_size_lt_12
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_size_lt_12
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 20485, 6145, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=4, offset=0, hwreg=MODE: simm16 = 0x1801 = 6145
    S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
    S_ENDPGM 0
...

---
# Case 1b: Size == 12 (boundary), imm32[12:19]=0
# Setreg (Size=12 <= 12) resets the mode scope and clears bits[12:19] to 0.
# vgpr256/257: S_SET_VGPR_MSB mode = 65, MODE register mode = 5
# New setreg imm = 0xABC | (5 << 12) = 0x5ABC = 23228

# ASM-LABEL: {{^}}setreg_size_eq_12:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 12), 0x5abc ;  msbs: dst=1 src0=1 src1=0 src2=0

# DIS-LABEL: <setreg_size_eq_12>:

name:            setreg_size_eq_12
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_size_eq_12
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 22529, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=12, offset=0, hwreg=MODE: simm16 = 0x5801 = 22529
    S_SETREG_IMM32_B32 2748, 22529, implicit-def $mode, implicit $mode
    S_ENDPGM 0
...

---
# Case 1c: Size <= 12 with existing non-zero bits in imm32[12:19]
# vgpr256/257: S_SET_VGPR_MSB mode = 65, MODE register mode = 5
# imm32 = 0x23005 (bits 12:19 = 0x23), result = 0x5005 = 20485 (bits 12:19 replaced with 5)

# ASM-LABEL: {{^}}setreg_size_lt_12_nonzero_upper:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 4), 0x5005 ;  msbs: dst=1 src0=1 src1=0 src2=0

# DIS-LABEL: <setreg_size_lt_12_nonzero_upper>:

name:            setreg_size_lt_12_nonzero_upper
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_size_lt_12_nonzero_upper
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 20485, 6145, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=4, offset=0, hwreg=MODE: simm16 = 0x1801 = 6145
    ; imm32 = 0x23005 = 143365 (bits 12:19 = 0x23)
    S_SETREG_IMM32_B32 143365, 6145, implicit-def $mode, implicit $mode
    S_ENDPGM 0
...

---
# Case 2a: Size > 12 (size=16), imm32[12:19] already matches VGPR MSBs
# vgpr256/257: S_SET_VGPR_MSB mode = 65, MODE register mode = 5
# imm32 = 0x5ABC = 23228 (bits 12:19 = 5), no modification needed

# ASM-LABEL: {{^}}setreg_size_gt_12_match:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 16), 0x5abc ;  msbs: dst=1 src0=1 src1=0 src2=0

# DIS-LABEL: <setreg_size_gt_12_match>:

name:            setreg_size_gt_12_match
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_size_gt_12_match
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 30721, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=16, offset=0, hwreg=MODE: simm16 = 0x7801 = 30721
    ; imm32 = 0x5ABC = 23228 (bits 12:19 = 5 = MODE register mode for vgpr256/257)
    S_SETREG_IMM32_B32 23228, 30721, implicit-def $mode, implicit $mode
    S_ENDPGM 0
...

---
# Case 2b: Size > 12 (size=16), imm32[12:19] already matches VGPR MSBs, offset is non-zero
# vgpr256/257: S_SET_VGPR_MSB mode = 65, MODE register mode = 5
# imm32 = 0x5ABC = 23228 (bits 12:19 = 5), no modification needed

# ASM-LABEL: {{^}}setreg_size_gt_12_offset_1_match:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 1, 16), 0x5abc ;  msbs: dst=1 src0=1 src1=0 src2=0

# DIS-LABEL: <setreg_size_gt_12_offset_1_match>:

name:            setreg_size_gt_12_offset_1_match
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_size_gt_12_offset_1_match
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 30785, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=16, offset=1, hwreg=MODE: simm16 = 0x7841 = 30785
    ; imm32 = 0x5ABC = 23228 (bits 12:19 = 5 = MODE register mode for vgpr256/257)
    S_SETREG_IMM32_B32 23228, 30785, implicit-def $mode, implicit $mode
    S_ENDPGM 0
...

---
# Case 3: Size > 12 (size=16), imm32[12:19] doesn't match VGPR MSBs
# vgpr256/257: S_SET_VGPR_MSB mode = 65, MODE register mode = 5
# imm32 = 0x23ABC = 146108 (bits 12:19 = 0x23 != 5), update mode bits

# ASM-LABEL: {{^}}setreg_size_gt_12_mismatch:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 16), 0x5abc ;  msbs: dst=1 src0=1 src1=0 src2=0

# DIS-LABEL: <setreg_size_gt_12_mismatch>:

name:            setreg_size_gt_12_mismatch
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_size_gt_12_mismatch
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 30721, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=16, offset=0, hwreg=MODE: simm16 = 0x7801 = 30721
    ; imm32 = 0x23ABC = 146108 (bits 12:19 = 0x23 != 5)
    S_SETREG_IMM32_B32 146108, 30721, implicit-def $mode, implicit $mode
    S_ENDPGM 0
...

---
# Case 3: Size > 12 (size=16), imm32[12:19] doesn't match VGPR MSBs, offset is non-zero
# vgpr256/257: S_SET_VGPR_MSB mode = 65, MODE register mode = 5
# imm32 = 0x23ABC = 146108 (bits 12:19 = 0x23 != 5), must insert s_set_vgpr_msb after

# ASM-LABEL: {{^}}setreg_size_gt_12_mismatch_offset_1:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 1, 16), 0x23abc ;  msbs: dst=3 src0=0 src1=2 src2=0

# DIS-LABEL: <setreg_size_gt_12_mismatch_offset_1>:

name:            setreg_size_gt_12_mismatch_offset_1
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_size_gt_12_mismatch_offset_1
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 146108, 30785, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_NOP 0
    ; CHECK-NEXT: S_SET_VGPR_MSB 16705, implicit-def $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=16, offset=1, hwreg=MODE: simm16 = 0x7841 = 30785
    ; imm32 = 0x23ABC = 146108 (bits 12:19 = 0x23 != 5)
    S_SETREG_IMM32_B32 146108, 30785, implicit-def $mode, implicit $mode
    S_ENDPGM 0
...

---
# Case 4: Non-MODE hwreg should not be modified
# This uses ID_STATUS=2 instead of ID_MODE=1
# vgpr256/257: S_SET_VGPR_MSB mode = 65

# ASM-LABEL: {{^}}setreg_non_mode_hwreg:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_STATUS, 0, 4), 5{{$}}

# DIS-LABEL: <setreg_non_mode_hwreg>:

name:            setreg_non_mode_hwreg
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_non_mode_hwreg
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 5, 6146, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=4, offset=0, hwreg=STATUS(2): simm16 = 2 | (0 << 6) | (3 << 11) = 0x1802 = 6146
    S_SETREG_IMM32_B32 5, 6146, implicit-def $mode, implicit $mode
    S_ENDPGM 0
...

---
# Case 5: Size <= 12 but VGPR MSBs already present (no change needed)
# vgpr256/257: S_SET_VGPR_MSB mode = 65, MODE register mode = 5
# imm32 = 0x5005 = 20485 (bits 12:19 = 5 = MODE register mode)

# ASM-LABEL: {{^}}setreg_size_lt_12_already_correct:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 4), 0x5005 ;  msbs: dst=1 src0=1 src1=0 src2=0

# DIS-LABEL: <setreg_size_lt_12_already_correct>:

name:            setreg_size_lt_12_already_correct
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_size_lt_12_already_correct
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 20485, 6145, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=4, offset=0, hwreg=MODE: simm16 = 0x1801 = 6145
    ; imm32 = 0x5005 = 20485 (bits 12:19 = 5 = MODE register mode)
    S_SETREG_IMM32_B32 20485, 6145, implicit-def $mode, implicit $mode
    S_ENDPGM 0
...

---
# Case 6: Different VGPR MSB value (using different high VGPRs)
# vgpr512/513 (both MSB=2): S_SET_VGPR_MSB mode = (2 << 0) | (2 << 6) = 130
#                           MODE register mode = (2 << 0) | (2 << 2) = 10
# New setreg imm = 0x5 | (10 << 12) = 0xA005 = 40965

# ASM-LABEL: {{^}}setreg_different_vgpr_msb:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 4), 0xa005 ;  msbs: dst=2 src0=2 src1=0 src2=0

# DIS-LABEL: <setreg_different_vgpr_msb>:

name:            setreg_different_vgpr_msb
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_different_vgpr_msb
    ; CHECK: S_SET_VGPR_MSB 130, implicit-def $mode
    ; CHECK-NEXT: $vgpr512 = V_MOV_B32_e32 $vgpr513, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 40965, 6145, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr512 = V_MOV_B32_e32 $vgpr513, implicit $exec
    ; size=4, offset=0, hwreg=MODE: simm16 = 0x1801 = 6145
    S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
    S_ENDPGM 0
...

---
# Case 7: Piggybacking blocked by s_setreg_imm32_b32 in between.

# ASM-LABEL: {{^}}setreg_size_le_12_piggyback_superset_blocked:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 4), 0x5005 ; msbs: dst=1 src0=1 src1=0 src2=0
# ASM: s_set_vgpr_msb 0x4149

# DIS-LABEL: <setreg_size_le_12_piggyback_superset_blocked>:
# DIS: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 4), 0x5005
# DIS: s_set_vgpr_msb 0x4149
# DIS-NEXT: v_add_nc_u32_e32 v0 /*v256*/, v1 /*v257*/, v0 /*v512*/

name:            setreg_size_le_12_piggyback_superset_blocked
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_size_le_12_piggyback_superset_blocked
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 20485, 6145, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_NOP 0
    ; CHECK-NEXT: S_SET_VGPR_MSB 16713, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_ADD_U32_e32 $vgpr257, $vgpr512, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=4, offset=0, hwreg=MODE: simm16 = 0x1801 = 6145
    S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
    ; Second instruction uses same dst/src0 (MSB=1) but adds src1 (MSB=2)
    $vgpr256 = V_ADD_U32_e32 $vgpr257, $vgpr512, implicit $exec
    S_ENDPGM 0
...

---
# Case 8: s_setreg_imm32_b32 (Size <= 12) followed by VGPR with different mode bits
# First VGPR (V_MOV vgpr256, vgpr0): S_SET_VGPR_MSB mode = 64, MODE register mode = 1
# Second VGPR (V_MOV vgpr256, vgpr256): S_SET_VGPR_MSB mode = 65, MODE register mode = 5
# Setreg gets MODE mode = 1 from first VGPR. Second VGPR needs different src0 bits,
# so a new S_SET_VGPR_MSB is inserted. The new S_SET_VGPR_MSB has mode = 65 | (64 << 8) = 16449.

# ASM-LABEL: {{^}}setreg_size_le_12_then_different_vgpr:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 4), 0x1005 ;  msbs: dst=1 src0=0 src1=0 src2=0

# DIS-LABEL: <setreg_size_le_12_then_different_vgpr>:
# DIS: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 4), 0x1005
# DIS: v_mov_b32_e32 v0 /*v256*/, v0 /*v256*/

name:            setreg_size_le_12_then_different_vgpr
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: setreg_size_le_12_then_different_vgpr
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: S_SET_VGPR_MSB 64, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr0, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 4101, 6145, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_NOP 0
    ; CHECK-NEXT: S_SET_VGPR_MSB 16449, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr256, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr0, implicit $exec
    ; size=4, offset=0, hwreg=MODE: simm16 = 0x1801 = 6145
    S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
    $vgpr256 = V_MOV_B32_e32 $vgpr256, implicit $exec
    S_ENDPGM 0
...

---
# Case 9: After s_setreg_imm32_b32 (Size > 12, matching), new s_set_vgpr_msb needed
# First VGPR (vgpr256/257): S_SET_VGPR_MSB mode = 65, MODE register mode = 5
# Setreg has size=16 with imm32[12:19]=5 (matches MODE register mode).
# handleSetregMode sets MostRecentModeSet = nullptr (can't piggyback on Size > 12).
# Second VGPR (vgpr512/513): S_SET_VGPR_MSB mode = 130, MODE register mode = 10
# Since MostRecentModeSet = nullptr, a new s_set_vgpr_msb is inserted.
# New s_set_vgpr_msb imm = NewMode | (OldMode << 8) = 130 | (65 << 8) = 16770

# ASM-LABEL: {{^}}setreg_size_gt_12_match_then_different_vgpr:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 16), 0x5abc ;  msbs: dst=1 src0=1 src1=0 src2=0

# DIS-LABEL: <setreg_size_gt_12_match_then_different_vgpr>:

name:            setreg_size_gt_12_match_then_different_vgpr
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_size_gt_12_match_then_different_vgpr
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 30721, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_NOP 0
    ; CHECK-NEXT: S_SET_VGPR_MSB 16770, implicit-def $mode
    ; CHECK-NEXT: $vgpr512 = V_MOV_B32_e32 $vgpr513, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=16, offset=0, hwreg=MODE: simm16 = 0x7801 = 30721
    ; imm32 = 0x5ABC = 23228 (bits 12:19 = 5 = MODE register mode, matches!)
    S_SETREG_IMM32_B32 23228, 30721, implicit-def $mode, implicit $mode
    $vgpr512 = V_MOV_B32_e32 $vgpr513, implicit $exec
    S_ENDPGM 0
...

---
# S_SET_VGPR_MSB format: (src0_msb[0-1], src1_msb[2-3], src2_msb[4-5], dst_msb[6-7])
# MODE register format:  (dst_msb[0-1], src0_msb[2-3], src1_msb[4-5], src2_msb[6-7])
# vgpr256/257 (both MSB=1): S_SET_VGPR_MSB mode = (1 << 0) | (1 << 6) = 65
#                           MODE register mode = (1 << 0) | (1 << 2) = 5
# New setreg imm = 0x5 | (5 << 12) = 0x5005 = 20485

# ASM-LABEL: {{^}}setreg_offset_8:
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 8, 4), 0x5005 ;  msbs: dst=1 src0=1 src1=0 src2=0

# DIS-LABEL: <setreg_offset_8>:

name:            setreg_offset_8
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_offset_8
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 20485, 6657, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=4, offset=8, hwreg=MODE: simm16 = 0x1801 = 6145
    S_SETREG_IMM32_B32 5, 6657, implicit-def $mode, implicit $mode
    S_ENDPGM 0
...

---

# ASM-LABEL: {{^}}setreg_offset_25:
# New imm = 1 | (5 << 12) = 0x5001 = 20481

# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 0x5001 ;  msbs: dst=1 src0=1 src1=0 src2=0

# DIS-LABEL: <setreg_offset_25>:

name:            setreg_offset_25
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_offset_25
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 20481, 1601, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=1, offset=25, hwreg=MODE: simm16 = 0x641 = 1601
    S_SETREG_IMM32_B32 1, 1601, implicit-def $mode, implicit $mode
    S_ENDPGM 0
...

# Update multiple SETREG instructions back to the first S_SET_VGPR_MSB

# ASM-LABEL: {{^}}multiple_setreg:
# ASM: s_set_vgpr_msb 0x41                     ;  msbs: dst=1 src0=1 src1=0 src2=0
# ASM: v_mov_b32_e32 v0 /*v256*/, v1 /*v257*/
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 4), 0x5005 ;  msbs: dst=1 src0=1 src1=0 src2=0
# ASM: v_mov_b32_e32 v0 /*v256*/, v1 /*v257*/
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 4), 0x5005 ;  msbs: dst=1 src0=1 src1=0 src2=0
# ASM: v_mov_b32_e32 v0 /*v256*/, v1 /*v257*/
# ASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 0x5001 ;  msbs: dst=1 src0=1 src1=0 src2=0
# ASM: v_mov_b32_e32 v0 /*v256*/, v1 /*v257*/

# DIS-LABEL: <multiple_setreg>:
# DIS: v_mov_b32_e32 v0 /*v256*/, v1 /*v257*/
# DIS: v_mov_b32_e32 v0 /*v256*/, v1 /*v257*/
# DIS: v_mov_b32_e32 v0 /*v256*/, v1 /*v257*/
# DIS: v_mov_b32_e32 v0 /*v256*/, v1 /*v257*/
---
name:            multiple_setreg
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: multiple_setreg
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 20485, 6145, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 20485, 6145, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 20481, 1601, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    S_SETREG_IMM32_B32 5, 6145, implicit-def $mode, implicit $mode
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    S_SETREG_IMM32_B32 1, 1601, implicit-def $mode, implicit $mode
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    S_ENDPGM 0
...

# Piggybacking blocked by s_setreg_imm32_b32.

# ASM-LABEL: {{^}}setreg_size_gt_12_offset_1_match_then_mismatch:
# ASM:      s_set_vgpr_msb 0x41                     ;  msbs: dst=1 src0=1 src1=0 src2=0
# ASM-NEXT: v_mov_b32_e32 v0 /*v256*/, v1 /*v257*/
# ASM-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 1, 16), 0x5abc ;  msbs: dst=1 src0=1 src1=0 src2=0
# ASM-NEXT: v_mov_b32_e32 v0 /*v256*/, v1 /*v257*/
# ASM-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 1, 16), 0x5abc ;  msbs: dst=1 src0=1 src1=0 src2=0
# ASM-NEXT: s_nop 0
# ASM-NEXT: s_set_vgpr_msb 0x4149                   ;  msbs: dst=1 src0=1 src1=2 src2=0
# ASM-NEXT: v_add_nc_u32_e32 v0 /*v256*/, v1 /*v257*/, v0 /*v512*/
# ASM-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 1, 16), 0x5abc ;  msbs: dst=1 src0=1 src1=0 src2=0
# ASM-NEXT: s_nop 0
# ASM-NEXT: s_set_vgpr_msb 0x4949                   ;  msbs: dst=1 src0=1 src1=2 src2=0

# DIS-LABEL: <setreg_size_gt_12_offset_1_match_then_mismatch>:
# DIS-NEXT: s_set_vgpr_msb 0x41
# DIS-NEXT: v_mov_b32_e32 v0 /*v256*/, v1 /*v257*/
# DIS-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 1, 16), 0x5abc
# DIS-NEXT: v_mov_b32_e32 v0 /*v256*/, v1 /*v257*/
# DIS-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 1, 16), 0x5abc
# DIS-NEXT: s_nop 0
# DIS-NEXT: s_set_vgpr_msb 0x4149
# DIS-NEXT: v_add_nc_u32_e32 v0 /*v256*/, v1 /*v257*/, v0 /*v512*/
# DIS-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 1, 16), 0x5abc
# DIS-NEXT: s_nop 0
# DIS-NEXT: s_set_vgpr_msb 0x49

---
name:            setreg_size_gt_12_offset_1_match_then_mismatch
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: setreg_size_gt_12_offset_1_match_then_mismatch
    ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 30785, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 30785, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_NOP 0
    ; CHECK-NEXT: S_SET_VGPR_MSB 16713, implicit-def $mode
    ; CHECK-NEXT: $vgpr256 = V_ADD_U32_e32 $vgpr257, $vgpr512, implicit $exec
    ; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 30785, implicit-def $mode, implicit $mode
    ; CHECK-NEXT: S_NOP 0
    ; CHECK-NEXT: S_SET_VGPR_MSB 18761, implicit-def $mode
    ; CHECK-NEXT: S_ENDPGM 0
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    ; size=16, offset=1, hwreg=MODE: simm16 = 0x7841 = 30785
    ; imm32 = 0x5ABC = 23228 (bits 12:19 = 5 = MODE register mode for vgpr256/257)
    S_SETREG_IMM32_B32 23228, 30785, implicit-def $mode, implicit $mode
    $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
    S_SETREG_IMM32_B32 23228, 30785, implicit-def $mode, implicit $mode
    $vgpr256 = V_ADD_U32_e32 $vgpr257, $vgpr512, implicit $exec
    S_SETREG_IMM32_B32 23228, 30785, implicit-def $mode, implicit $mode
    S_ENDPGM 0
...