llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s

# Check that we don't hang on this.
---
name:            fold_reg_sequence
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2

    ; CHECK-LABEL: name: fold_reg_sequence
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 429
    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1
    ; CHECK-NEXT: [[V_MUL_HI_U32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32_e64 $vgpr2, [[REG_SEQUENCE]].sub0, implicit $exec
    ; CHECK-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec :: (load (s32), addrspace 1)
    ; CHECK-NEXT: [[V_MUL_HI_U32_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32_e64 [[GLOBAL_LOAD_DWORD]], [[REG_SEQUENCE]].sub0, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %0:sreg_32 = S_MOV_B32 0
    %1:sreg_32 = S_MOV_B32 429
    %2:sreg_64 = REG_SEQUENCE killed %1, %subreg.sub0, %0, %subreg.sub1
    %3:vgpr_32 = V_MUL_HI_U32_e64 $vgpr2, %2.sub0, implicit $exec
    %4:vgpr_32 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec :: (load (s32), addrspace 1)
    %5:vgpr_32 = V_MUL_HI_U32_e64 %4, %2.sub0, implicit $exec
    S_ENDPGM 0
...

# Fold through a COPY of REG_SEQUENCE.
---
name: fold_through_copy
body:             |
  bb.0:
    ; CHECK-LABEL: name: fold_through_copy
    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
    ; CHECK-NEXT: [[V_PK_ADD_F32_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_PK_ADD_F32 8, [[DEF]], 8, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
    %0:sreg_32 = S_MOV_B32 0
    %1:sreg_64 = REG_SEQUENCE %0:sreg_32, %subreg.sub0, %0:sreg_32, %subreg.sub1
    %2:sreg_64_xexec = IMPLICIT_DEF
    %3:vreg_64_align2 = COPY %1:sreg_64
    %4:vreg_64_align2 = nofpexcept V_PK_ADD_F32 8, %2:sreg_64_xexec, 8, %3:vreg_64_align2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
...

---
name: regseq_with_phys_source
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr2

    ; CHECK-LABEL: name: regseq_with_phys_source
    ; CHECK: liveins: $vgpr0, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE $vgpr0, %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1
    ; CHECK-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[REG_SEQUENCE]].sub0, $vgpr2, implicit-def $vcc, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
    %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
    %1:vreg_64 = REG_SEQUENCE $vgpr0, %subreg.sub0, %0, %subreg.sub1
    %2:vgpr_32 = V_ADD_CO_U32_e32 %1.sub0, $vgpr2, implicit-def $vcc, implicit $exec
    S_ENDPGM 0, implicit %2

...