llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,FAKE16 %s
; xUN: llc -global-isel=1 -mtriple=amdgpu12.50 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,REAL16 %s
; xUN: llc -global-isel=1 -mtriple=amdgpu12.50 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,REAL16 %s

; FIXME: GlobalISel does not work with bf16

declare bfloat @llvm.amdgcn.sin.bf16(bfloat) #0

define amdgpu_kernel void @sin_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
; FAKE16-LABEL: sin_bf16:
; FAKE16:       ; %bb.0:
; FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; FAKE16-NEXT:    s_mov_b64 s[64:65], 0
; FAKE16-NEXT:    v_nop
; FAKE16-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; FAKE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24 nv
; FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; FAKE16-NEXT:    s_wait_kmcnt 0x0
; FAKE16-NEXT:    v_sin_bf16_e32 v0, s2
; FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; FAKE16-NEXT:    s_endpgm
;
; REAL16-LABEL: sin_bf16:
; REAL16:       ; %bb.0:
; REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; REAL16-NEXT:    s_mov_b64 s[64:65], 0
; REAL16-NEXT:    v_nop
; REAL16-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; REAL16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24 nv
; REAL16-NEXT:    v_mov_b32_e32 v1, 0
; REAL16-NEXT:    s_wait_kmcnt 0x0
; REAL16-NEXT:    v_sin_bf16_e32 v0.l, s2
; REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; REAL16-NEXT:    s_endpgm
  %sin = call bfloat @llvm.amdgcn.sin.bf16(bfloat %src) #0
  store bfloat %sin, ptr addrspace(1) %out, align 2
  ret void
}

define amdgpu_kernel void @sin_bf16_constant_4_strictfp(ptr addrspace(1) %out) #2 {
; FAKE16-LABEL: sin_bf16_constant_4_strictfp:
; FAKE16:       ; %bb.0:
; FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; FAKE16-NEXT:    s_mov_b64 s[64:65], 0
; FAKE16-NEXT:    v_nop
; FAKE16-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24 nv
; FAKE16-NEXT:    v_sin_bf16_e64 v0, 4.0 op_sel:[1,0]
; FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; FAKE16-NEXT:    s_wait_kmcnt 0x0
; FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; FAKE16-NEXT:    s_endpgm
;
; REAL16-LABEL: sin_bf16_constant_4_strictfp:
; REAL16:       ; %bb.0:
; REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; REAL16-NEXT:    s_mov_b64 s[64:65], 0
; REAL16-NEXT:    v_nop
; REAL16-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; REAL16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24 nv
; REAL16-NEXT:    v_sin_bf16_e64 v0.l, 4.0 op_sel:[1,0]
; REAL16-NEXT:    v_mov_b32_e32 v1, 0
; REAL16-NEXT:    s_wait_kmcnt 0x0
; REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; REAL16-NEXT:    s_endpgm
  %sin = call bfloat @llvm.amdgcn.sin.bf16(bfloat 4.0) strictfp
  store bfloat %sin, ptr addrspace(1) %out, align 2
  ret void
}

define amdgpu_kernel void @sin_bf16_constant_100_strictfp(ptr addrspace(1) %out) #2 {
; FAKE16-LABEL: sin_bf16_constant_100_strictfp:
; FAKE16:       ; %bb.0:
; FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; FAKE16-NEXT:    s_mov_b64 s[64:65], 0
; FAKE16-NEXT:    v_nop
; FAKE16-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24 nv
; FAKE16-NEXT:    v_sin_bf16_e32 v0, 0x42c8
; FAKE16-NEXT:    v_mov_b32_e32 v1, 0
; FAKE16-NEXT:    s_wait_kmcnt 0x0
; FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
; FAKE16-NEXT:    s_endpgm
;
; REAL16-LABEL: sin_bf16_constant_100_strictfp:
; REAL16:       ; %bb.0:
; REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; REAL16-NEXT:    s_mov_b64 s[64:65], 0
; REAL16-NEXT:    v_nop
; REAL16-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; REAL16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24 nv
; REAL16-NEXT:    v_sin_bf16_e32 v0.l, 0x42c8
; REAL16-NEXT:    v_mov_b32_e32 v1, 0
; REAL16-NEXT:    s_wait_kmcnt 0x0
; REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; REAL16-NEXT:    s_endpgm
  %sin = call bfloat @llvm.amdgcn.sin.bf16(bfloat 100.0) strictfp
  store bfloat %sin, ptr addrspace(1) %out, align 2
  ret void
}

define amdgpu_kernel void @sin_bf16_constant_0.3(ptr addrspace(1) %out) #1 {
; FAKE16-LABEL: sin_bf16_constant_0.3:
; FAKE16:       ; %bb.0:
; FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; FAKE16-NEXT:    s_mov_b64 s[64:65], 0
; FAKE16-NEXT:    v_nop
; FAKE16-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24 nv
; FAKE16-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3f73
; FAKE16-NEXT:    s_wait_kmcnt 0x0
; FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
; FAKE16-NEXT:    s_endpgm
;
; REAL16-LABEL: sin_bf16_constant_0.3:
; REAL16:       ; %bb.0:
; REAL16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; REAL16-NEXT:    s_mov_b64 s[64:65], 0
; REAL16-NEXT:    v_nop
; REAL16-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; REAL16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24 nv
; REAL16-NEXT:    v_mov_b32_e32 v1, 0
; REAL16-NEXT:    v_mov_b16_e32 v0.l, 0x3f73
; REAL16-NEXT:    s_wait_kmcnt 0x0
; REAL16-NEXT:    global_store_b16 v1, v0, s[0:1]
; REAL16-NEXT:    s_endpgm
  %sin = call bfloat @llvm.amdgcn.sin.bf16(bfloat 0.3)
  store bfloat %sin, ptr addrspace(1) %out, align 2
  ret void
}

attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }
attributes #2 = { nounwind strictfp }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}