| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s |
| |
| # This example is actually equivalent as there's a sub in the loop, which is |
| # then used by the add in the exit - making the vctp operands equivalent. |
| |
| --- | |
| define dso_local i32 @wrong_vctp_liveout(i16* nocapture readonly %a, i16* nocapture readonly %b, i32 %N) local_unnamed_addr #0 { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %0 = add i32 %N, 3 |
| %1 = lshr i32 %0, 2 |
| %2 = shl nuw i32 %1, 2 |
| %3 = add i32 %2, -4 |
| %4 = lshr i32 %3, 2 |
| %5 = add nuw nsw i32 %4, 1 |
| br i1 %cmp9, label %for.cond.cleanup, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] |
| %lsr.iv18 = phi i16* [ %scevgep19, %vector.body ], [ %b, %vector.ph ] |
| %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ] |
| %6 = phi i32 [ %N, %vector.ph ], [ %8, %vector.body ] |
| %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* |
| %lsr.iv1820 = bitcast i16* %lsr.iv18 to <4 x i16>* |
| %7 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %6) |
| %8 = sub i32 %6, 4 |
| %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %7, <4 x i16> undef) |
| %9 = sext <4 x i16> %wide.masked.load to <4 x i32> |
| %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1820, i32 2, <4 x i1> %7, <4 x i16> undef) |
| %10 = sext <4 x i16> %wide.masked.load14 to <4 x i32> |
| %11 = mul nsw <4 x i32> %10, %9 |
| %12 = add <4 x i32> %11, %vec.phi |
| %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 |
| %scevgep19 = getelementptr i16, i16* %lsr.iv18, i32 4 |
| %13 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %14 = icmp ne i32 %13, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %14, label %vector.body, label %middle.block |
| |
| middle.block: ; preds = %vector.body |
| %15 = add i32 %8, 4 |
| %16 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %15) |
| %17 = select <4 x i1> %16, <4 x i32> %12, <4 x i32> %vec.phi |
| %18 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %17) |
| br label %for.cond.cleanup |
| |
| for.cond.cleanup: ; preds = %middle.block, %entry |
| %res.0.lcssa = phi i32 [ 0, %entry ], [ %18, %middle.block ] |
| ret i32 %res.0.lcssa |
| } |
| declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) |
| declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) |
| declare i32 @llvm.start.loop.iterations.i32(i32) |
| declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) |
| declare <4 x i1> @llvm.arm.mve.vctp32(i32) |
| |
| ... |
| --- |
| name: wrong_vctp_liveout |
| alignment: 2 |
| exposesReturnsTwice: false |
| legalized: false |
| regBankSelected: false |
| selected: false |
| failedISel: false |
| tracksRegLiveness: true |
| hasWinCFI: false |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| isFrameAddressTaken: false |
| isReturnAddressTaken: false |
| hasStackMap: false |
| hasPatchPoint: false |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| adjustsStack: false |
| hasCalls: false |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| hasOpaqueSPAdjustment: false |
| hasVAStart: false |
| hasMustTailInVarArgFunc: false |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: wrong_vctp_liveout |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 |
| ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 0, 4, implicit-def $itstate |
| ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate |
| ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate |
| ; CHECK: bb.1.vector.ph: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 |
| ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: dead $lr = t2DLS renamable $r12 |
| ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| ; CHECK: bb.2.vector.body: |
| ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3 |
| ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg |
| ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0 |
| ; CHECK: MVE_VPST 4, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) |
| ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) |
| ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 |
| ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 |
| ; CHECK: bb.3.middle.block: |
| ; CHECK: liveins: $q0, $q1, $r2 |
| ; CHECK: renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg, $noreg |
| ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg |
| ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| bb.0.entry: |
| successors: %bb.1(0x80000000) |
| liveins: $r0, $r1, $r2, $lr, $r7 |
| |
| tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr |
| t2IT 0, 4, implicit-def $itstate |
| renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate |
| tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate |
| |
| bb.1.vector.ph: |
| successors: %bb.2(0x80000000) |
| liveins: $r0, $r1, $r2, $lr, $r7 |
| |
| frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg |
| renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 |
| renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg |
| renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg |
| renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg |
| $lr = t2DoLoopStart renamable $r12 |
| $r3 = tMOVr killed $r12, 14, $noreg |
| |
| bb.2.vector.body: |
| successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| liveins: $q1, $r0, $r1, $r2, $r3 |
| |
| renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg |
| $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q0 |
| MVE_VPST 4, implicit $vpr |
| renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) |
| renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) |
| $lr = tMOVr $r3, 14, $noreg |
| renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 |
| renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg |
| renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.3, 14, $noreg |
| |
| bb.3.middle.block: |
| liveins: $q0, $q1, $r2 |
| |
| renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14, $noreg |
| renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg, $noreg |
| renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg |
| renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg |
| tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| ... |