| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zfh -verify-machineinstrs \ |
| ; RUN: < %s | FileCheck %s |
| declare <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1( |
| i64); |
| |
| define <vscale x 1 x i1> @intrinsic_vmset_m_pseudo_nxv1i1(i64 %0) nounwind { |
| ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv1i1: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu |
| ; CHECK-NEXT: vmset.m v0 |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1( |
| i64 %0) |
| |
| ret <vscale x 1 x i1> %a |
| } |
| |
| declare <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1( |
| i64); |
| |
| define <vscale x 2 x i1> @intrinsic_vmset_m_pseudo_nxv2i1(i64 %0) nounwind { |
| ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv2i1: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu |
| ; CHECK-NEXT: vmset.m v0 |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1( |
| i64 %0) |
| |
| ret <vscale x 2 x i1> %a |
| } |
| |
| declare <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1( |
| i64); |
| |
| define <vscale x 4 x i1> @intrinsic_vmset_m_pseudo_nxv4i1(i64 %0) nounwind { |
| ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv4i1: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu |
| ; CHECK-NEXT: vmset.m v0 |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1( |
| i64 %0) |
| |
| ret <vscale x 4 x i1> %a |
| } |
| |
| declare <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1( |
| i64); |
| |
| define <vscale x 8 x i1> @intrinsic_vmset_m_pseudo_nxv8i1(i64 %0) nounwind { |
| ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv8i1: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu |
| ; CHECK-NEXT: vmset.m v0 |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1( |
| i64 %0) |
| |
| ret <vscale x 8 x i1> %a |
| } |
| |
| declare <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1( |
| i64); |
| |
| define <vscale x 16 x i1> @intrinsic_vmset_m_pseudo_nxv16i1(i64 %0) nounwind { |
| ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv16i1: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu |
| ; CHECK-NEXT: vmset.m v0 |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1( |
| i64 %0) |
| |
| ret <vscale x 16 x i1> %a |
| } |
| |
| declare <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1( |
| i64); |
| |
| define <vscale x 32 x i1> @intrinsic_vmset_m_pseudo_nxv32i1(i64 %0) nounwind { |
| ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv32i1: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu |
| ; CHECK-NEXT: vmset.m v0 |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1( |
| i64 %0) |
| |
| ret <vscale x 32 x i1> %a |
| } |
| |
| declare <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1( |
| i64); |
| |
| define <vscale x 64 x i1> @intrinsic_vmset_m_pseudo_nxv64i1(i64 %0) nounwind { |
| ; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv64i1: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu |
| ; CHECK-NEXT: vmset.m v0 |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1( |
| i64 %0) |
| |
| ret <vscale x 64 x i1> %a |
| } |