| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck -check-prefix=SI %s |
| # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=legalizer -o - %s | FileCheck -check-prefix=CI %s |
| # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck -check-prefix=VI %s |
| # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s |
| # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s |
| |
| --- |
| name: test_fceil_s16 |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; SI-LABEL: name: test_fceil_s16 |
| ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) |
| ; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) |
| ; SI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]] |
| ; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32) |
| ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16) |
| ; SI: $vgpr0 = COPY [[ANYEXT]](s32) |
| ; CI-LABEL: name: test_fceil_s16 |
| ; CI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) |
| ; CI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) |
| ; CI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]] |
| ; CI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32) |
| ; CI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16) |
| ; CI: $vgpr0 = COPY [[ANYEXT]](s32) |
| ; VI-LABEL: name: test_fceil_s16 |
| ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) |
| ; VI: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]] |
| ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16) |
| ; VI: $vgpr0 = COPY [[ANYEXT]](s32) |
| ; GFX9-LABEL: name: test_fceil_s16 |
| ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) |
| ; GFX9: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]] |
| ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16) |
| ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s16) = G_TRUNC %0 |
| %2:_(s16) = G_FCEIL %1 |
| %3:_(s32) = G_ANYEXT %2 |
| $vgpr0 = COPY %3 |
| ... |
| |
| --- |
| name: test_fceil_s32 |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; SI-LABEL: name: test_fceil_s32 |
| ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; SI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]] |
| ; SI: $vgpr0 = COPY [[FCEIL]](s32) |
| ; CI-LABEL: name: test_fceil_s32 |
| ; CI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]] |
| ; CI: $vgpr0 = COPY [[FCEIL]](s32) |
| ; VI-LABEL: name: test_fceil_s32 |
| ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; VI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]] |
| ; VI: $vgpr0 = COPY [[FCEIL]](s32) |
| ; GFX9-LABEL: name: test_fceil_s32 |
| ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; GFX9: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]] |
| ; GFX9: $vgpr0 = COPY [[FCEIL]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_FCEIL %0 |
| $vgpr0 = COPY %1 |
| ... |
| |
| --- |
| name: test_fceil_s64 |
| body: | |
| bb.0: |
| liveins: $vgpr0_vgpr1 |
| |
| ; SI-LABEL: name: test_fceil_s64 |
| ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 |
| ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) |
| ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20 |
| ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11 |
| ; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV1]](s32), [[C]](s32), [[C1]](s32) |
| ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023 |
| ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]] |
| ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 |
| ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]] |
| ; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495 |
| ; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32) |
| ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32) |
| ; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 |
| ; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]] |
| ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[XOR]] |
| ; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 |
| ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]] |
| ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]] |
| ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]] |
| ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[COPY]], [[SELECT]] |
| ; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00 |
| ; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00 |
| ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s64), [[C8]] |
| ; SI: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](s64), [[SELECT1]] |
| ; SI: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]] |
| ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s1), [[C9]], [[C8]] |
| ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[SELECT1]], [[SELECT2]] |
| ; SI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]] |
| ; SI: $vgpr0_vgpr1 = COPY [[FCEIL]](s64) |
| ; CI-LABEL: name: test_fceil_s64 |
| ; CI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 |
| ; CI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]] |
| ; CI: $vgpr0_vgpr1 = COPY [[FCEIL]](s64) |
| ; VI-LABEL: name: test_fceil_s64 |
| ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 |
| ; VI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]] |
| ; VI: $vgpr0_vgpr1 = COPY [[FCEIL]](s64) |
| ; GFX9-LABEL: name: test_fceil_s64 |
| ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 |
| ; GFX9: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]] |
| ; GFX9: $vgpr0_vgpr1 = COPY [[FCEIL]](s64) |
| %0:_(s64) = COPY $vgpr0_vgpr1 |
| %1:_(s64) = G_FCEIL %0 |
| $vgpr0_vgpr1 = COPY %1 |
| ... |
| |
| --- |
| name: test_fceil_v2s16 |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; SI-LABEL: name: test_fceil_v2s16 |
| ; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 |
| ; SI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) |
| ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) |
| ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) |
| ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) |
| ; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) |
| ; SI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]] |
| ; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32) |
| ; SI: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16) |
| ; SI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT1]] |
| ; SI: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL1]](s32) |
| ; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16) |
| ; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16) |
| ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32) |
| ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]] |
| ; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) |
| ; SI: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) |
| ; CI-LABEL: name: test_fceil_v2s16 |
| ; CI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 |
| ; CI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) |
| ; CI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) |
| ; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) |
| ; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) |
| ; CI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) |
| ; CI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]] |
| ; CI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32) |
| ; CI: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16) |
| ; CI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT1]] |
| ; CI: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL1]](s32) |
| ; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC]](s16) |
| ; CI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16) |
| ; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32) |
| ; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]] |
| ; CI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) |
| ; CI: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) |
| ; VI-LABEL: name: test_fceil_v2s16 |
| ; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 |
| ; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) |
| ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) |
| ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) |
| ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) |
| ; VI: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]] |
| ; VI: [[FCEIL1:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC1]] |
| ; VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FCEIL]](s16) |
| ; VI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FCEIL1]](s16) |
| ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32) |
| ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]] |
| ; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) |
| ; VI: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) |
| ; GFX9-LABEL: name: test_fceil_v2s16 |
| ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 |
| ; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) |
| ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) |
| ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) |
| ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) |
| ; GFX9: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]] |
| ; GFX9: [[FCEIL1:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC1]] |
| ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16) |
| ; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL1]](s16) |
| ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32) |
| ; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>) |
| %0:_(<2 x s16>) = COPY $vgpr0 |
| %1:_(<2 x s16>) = G_FCEIL %0 |
| $vgpr0 = COPY %1 |
| ... |
| |
| --- |
| name: test_fceil_v2s32 |
| body: | |
| bb.0: |
| liveins: $vgpr0_vgpr1 |
| |
| ; SI-LABEL: name: test_fceil_v2s32 |
| ; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 |
| ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) |
| ; SI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]] |
| ; SI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]] |
| ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32) |
| ; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) |
| ; CI-LABEL: name: test_fceil_v2s32 |
| ; CI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 |
| ; CI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) |
| ; CI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]] |
| ; CI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]] |
| ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32) |
| ; CI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) |
| ; VI-LABEL: name: test_fceil_v2s32 |
| ; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 |
| ; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) |
| ; VI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]] |
| ; VI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]] |
| ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32) |
| ; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) |
| ; GFX9-LABEL: name: test_fceil_v2s32 |
| ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 |
| ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) |
| ; GFX9: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]] |
| ; GFX9: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]] |
| ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32) |
| ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) |
| %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 |
| %1:_(<2 x s32>) = G_FCEIL %0 |
| $vgpr0_vgpr1 = COPY %1 |
| ... |
| |
| --- |
| name: test_fceil_v2s64 |
| body: | |
| bb.0: |
| liveins: $vgpr0_vgpr1_vgpr2_vgpr3 |
| |
| ; SI-LABEL: name: test_fceil_v2s64 |
| ; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) |
| ; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) |
| ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20 |
| ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11 |
| ; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV3]](s32), [[C]](s32), [[C1]](s32) |
| ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023 |
| ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]] |
| ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 |
| ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]] |
| ; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495 |
| ; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32) |
| ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32) |
| ; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 |
| ; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]] |
| ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV]], [[XOR]] |
| ; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 |
| ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]] |
| ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]] |
| ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]] |
| ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV]], [[SELECT]] |
| ; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00 |
| ; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00 |
| ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s64), [[C8]] |
| ; SI: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV]](s64), [[SELECT1]] |
| ; SI: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]] |
| ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s1), [[C9]], [[C8]] |
| ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[SELECT1]], [[SELECT2]] |
| ; SI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]] |
| ; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) |
| ; SI: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV5]](s32), [[C]](s32), [[C1]](s32) |
| ; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[INT1]], [[C2]] |
| ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]] |
| ; SI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND3]](s32) |
| ; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB1]](s32) |
| ; SI: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[ASHR1]], [[C6]] |
| ; SI: [[AND4:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[XOR1]] |
| ; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB1]](s32), [[C5]] |
| ; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB1]](s32), [[C7]] |
| ; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[MV1]], [[AND4]] |
| ; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV1]], [[SELECT3]] |
| ; SI: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](s64), [[C8]] |
| ; SI: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV1]](s64), [[SELECT4]] |
| ; SI: [[AND5:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]] |
| ; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[AND5]](s1), [[C9]], [[C8]] |
| ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[SELECT4]], [[SELECT5]] |
| ; SI: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]] |
| ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64) |
| ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) |
| ; CI-LABEL: name: test_fceil_v2s64 |
| ; CI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; CI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) |
| ; CI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]] |
| ; CI: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]] |
| ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64) |
| ; CI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) |
| ; VI-LABEL: name: test_fceil_v2s64 |
| ; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) |
| ; VI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]] |
| ; VI: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]] |
| ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64) |
| ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) |
| ; GFX9-LABEL: name: test_fceil_v2s64 |
| ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) |
| ; GFX9: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]] |
| ; GFX9: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]] |
| ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64) |
| ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) |
| %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 |
| %1:_(<2 x s64>) = G_FCEIL %0 |
| $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1 |
| ... |