| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py |
| // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbe -emit-llvm %s -o - \ |
| // RUN: | FileCheck %s -check-prefix=RV32ZBE |
| |
| // RV32ZBE-LABEL: @bcompress( |
| // RV32ZBE-NEXT: entry: |
| // RV32ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 |
| // RV32ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 |
| // RV32ZBE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4 |
| // RV32ZBE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4 |
| // RV32ZBE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4 |
| // RV32ZBE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4 |
| // RV32ZBE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.bcompress.i32(i32 [[TMP0]], i32 [[TMP1]]) |
| // RV32ZBE-NEXT: ret i32 [[TMP2]] |
| // |
| long bcompress(long rs1, long rs2) { |
| return __builtin_riscv_bcompress_32(rs1, rs2); |
| } |
| |
| // RV32ZBE-LABEL: @bdecompress( |
| // RV32ZBE-NEXT: entry: |
| // RV32ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 |
| // RV32ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 |
| // RV32ZBE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4 |
| // RV32ZBE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4 |
| // RV32ZBE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4 |
| // RV32ZBE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4 |
| // RV32ZBE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.bdecompress.i32(i32 [[TMP0]], i32 [[TMP1]]) |
| // RV32ZBE-NEXT: ret i32 [[TMP2]] |
| // |
| long bdecompress(long rs1, long rs2) { |
| return __builtin_riscv_bdecompress_32(rs1, rs2); |
| } |
